tjh.dev / kernel
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kernel / drivers / video / i810 / i810_regs.h
at v2.6.13 274 lines 8.9 kB view raw
1/*-*- linux-c -*- 2 * linux/drivers/video/i810_regs.h -- Intel 810/815 Register List 3 * 4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net> 5 * All Rights Reserved 6 * 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file COPYING in the main directory of this archive for 10 * more details. 11 */ 12 13 14/* 15 * Intel 810 Chipset Family PRM 15 3.1 16 * GC Register Memory Address Map 17 * 18 * Based on: 19 * Intel (R) 810 Chipset Family 20 * Programmer s Reference Manual 21 * November 1999 22 * Revision 1.0 23 * Order Number: 298026-001 R 24 * 25 * All GC registers are memory-mapped. In addition, the VGA and extended VGA registers 26 * are I/O mapped. 27 */ 28 29#ifndef __I810_REGS_H__ 30#define __I810_REGS_H__ 31 32/* Instruction and Interrupt Control Registers (01000h 02FFFh) */ 33#define FENCE 0x02000 34#define PGTBL_CTL 0x02020 35#define PGTBL_ER 0x02024 36#define LRING 0x02030 37#define IRING 0x02040 38#define HWS_PGA 0x02080 39#define IPEIR 0x02088 40#define IPEHR 0x0208C 41#define INSTDONE 0x02090 42#define NOPID 0x02094 43#define HWSTAM 0x02098 44#define IER 0x020A0 45#define IIR 0x020A4 46#define IMR 0x020A8 47#define ISR 0x020AC 48#define EIR 0x020B0 49#define EMR 0x020B4 50#define ESR 0x020B8 51#define INSTPM 0x020C0 52#define INSTPS 0x020C4 53#define BBP_PTR 0x020C8 54#define ABB_SRT 0x020CC 55#define ABB_END 0x020D0 56#define DMA_FADD 0x020D4 57#define FW_BLC 0x020D8 58#define MEM_MODE 0x020DC 59 60/* Memory Control Registers (03000h 03FFFh) */ 61#define DRT 0x03000 62#define DRAMCL 0x03001 63#define DRAMCH 0x03002 64 65 66/* Span Cursor Registers (04000h 04FFFh) */ 67#define UI_SC_CTL 0x04008 68 69/* I/O Control Registers (05000h 05FFFh) */ 70#define HVSYNC 0x05000 71#define GPIOA 0x05010 72#define GPIOB 0x05014 73 74/* Clock Control and Power Management Registers (06000h 06FFFh) */ 75#define DCLK_0D 0x06000 76#define DCLK_1D 0x06004 77#define DCLK_2D 0x06008 78#define LCD_CLKD 0x0600C 79#define DCLK_0DS 0x06010 80#define PWR_CLKC 0x06014 81 82/* Graphics Translation Table Range Definition (10000h 1FFFFh) */ 83#define GTT 0x10000 84 85/* Overlay Registers (30000h 03FFFFh) */ 86#define OVOADDR 0x30000 87#define DOVOSTA 0x30008 88#define GAMMA 0x30010 89#define OBUF_0Y 0x30100 90#define OBUF_1Y 0x30104 91#define OBUF_0U 0x30108 92#define OBUF_0V 0x3010C 93#define OBUF_1U 0x30110 94#define OBUF_1V 0x30114 95#define OVOSTRIDE 0x30118 96#define YRGB_VPH 0x3011C 97#define UV_VPH 0x30120 98#define HORZ_PH 0x30124 99#define INIT_PH 0x30128 100#define DWINPOS 0x3012C 101#define DWINSZ 0x30130 102#define SWID 0x30134 103#define SWIDQW 0x30138 104#define SHEIGHT 0x3013F 105#define YRGBSCALE 0x30140 106#define UVSCALE 0x30144 107#define OVOCLRCO 0x30148 108#define OVOCLRC1 0x3014C 109#define DCLRKV 0x30150 110#define DLCRKM 0x30154 111#define SCLRKVH 0x30158 112#define SCLRKVL 0x3015C 113#define SCLRKM 0x30160 114#define OVOCONF 0x30164 115#define OVOCMD 0x30168 116#define AWINPOS 0x30170 117#define AWINZ 0x30174 118 119/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */ 120#define BR00 0x40000 121#define BRO1 0x40004 122#define BR02 0x40008 123#define BR03 0x4000C 124#define BR04 0x40010 125#define BR05 0x40014 126#define BR06 0x40018 127#define BR07 0x4001C 128#define BR08 0x40020 129#define BR09 0x40024 130#define BR10 0x40028 131#define BR11 0x4002C 132#define BR12 0x40030 133#define BR13 0x40034 134#define BR14 0x40038 135#define BR15 0x4003C 136#define BR16 0x40040 137#define BR17 0x40044 138#define BR18 0x40048 139#define BR19 0x4004C 140#define SSLADD 0x40074 141#define DSLH 0x40078 142#define DSLRADD 0x4007C 143 144 145/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */ 146/* LCD/TV-Out */ 147#define HTOTAL 0x60000 148#define HBLANK 0x60004 149#define HSYNC 0x60008 150#define VTOTAL 0x6000C 151#define VBLANK 0x60010 152#define VSYNC 0x60014 153#define LCDTV_C 0x60018 154#define OVRACT 0x6001C 155#define BCLRPAT 0x60020 156 157/* Display and Cursor Control Registers (70000h 7FFFFh) */ 158#define DISP_SL 0x70000 159#define DISP_SLC 0x70004 160#define PIXCONF 0x70008 161#define PIXCONF1 0x70009 162#define BLTCNTL 0x7000C 163#define SWF 0x70014 164#define DPLYBASE 0x70020 165#define DPLYSTAS 0x70024 166#define CURCNTR 0x70080 167#define CURBASE 0x70084 168#define CURPOS 0x70088 169 170 171/* VGA Registers */ 172 173/* SMRAM Registers */ 174#define SMRAM 0x10 175 176/* Graphics Control Registers */ 177#define GR_INDEX 0x3CE 178#define GR_DATA 0x3CF 179 180#define GR10 0x10 181#define GR11 0x11 182 183/* CRT Controller Registers */ 184#define CR_INDEX_MDA 0x3B4 185#define CR_INDEX_CGA 0x3D4 186#define CR_DATA_MDA 0x3B5 187#define CR_DATA_CGA 0x3D5 188 189#define CR30 0x30 190#define CR31 0x31 191#define CR32 0x32 192#define CR33 0x33 193#define CR35 0x35 194#define CR39 0x39 195#define CR40 0x40 196#define CR41 0x41 197#define CR42 0x42 198#define CR70 0x70 199#define CR80 0x80 200#define CR81 0x82 201 202/* Extended VGA Registers */ 203 204/* General Control and Status Registers */ 205#define ST00 0x3C2 206#define ST01_MDA 0x3BA 207#define ST01_CGA 0x3DA 208#define FRC_READ 0x3CA 209#define FRC_WRITE_MDA 0x3BA 210#define FRC_WRITE_CGA 0x3DA 211#define MSR_READ 0x3CC 212#define MSR_WRITE 0x3C2 213 214/* Sequencer Registers */ 215#define SR_INDEX 0x3C4 216#define SR_DATA 0x3C5 217 218#define SR01 0x01 219#define SR02 0x02 220#define SR03 0x03 221#define SR04 0x04 222#define SR07 0x07 223 224/* Graphics Controller Registers */ 225#define GR00 0x00 226#define GR01 0x01 227#define GR02 0x02 228#define GR03 0x03 229#define GR04 0x04 230#define GR05 0x05 231#define GR06 0x06 232#define GR07 0x07 233#define GR08 0x08 234 235/* Attribute Controller Registers */ 236#define ATTR_WRITE 0x3C0 237#define ATTR_READ 0x3C1 238 239/* VGA Color Palette Registers */ 240 241/* CLUT */ 242#define CLUT_DATA 0x3C9 /* DACDATA */ 243#define CLUT_INDEX_READ 0x3C7 /* DACRX */ 244#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */ 245#define DACMASK 0x3C6 246 247/* CRT Controller Registers */ 248#define CR00 0x00 249#define CR01 0x01 250#define CR02 0x02 251#define CR03 0x03 252#define CR04 0x04 253#define CR05 0x05 254#define CR06 0x06 255#define CR07 0x07 256#define CR08 0x08 257#define CR09 0x09 258#define CR0A 0x0A 259#define CR0B 0x0B 260#define CR0C 0x0C 261#define CR0D 0x0D 262#define CR0E 0x0E 263#define CR0F 0x0F 264#define CR10 0x10 265#define CR11 0x11 266#define CR12 0x12 267#define CR13 0x13 268#define CR14 0x14 269#define CR15 0x15 270#define CR16 0x16 271#define CR17 0x17 272#define CR18 0x18 273 274#endif /* __I810_REGS_H__ */