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Linux kernel mirror (for testing)
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linux
1#ifndef __ASM_SH_IRQ_SH73180_H
2#define __ASM_SH_IRQ_SH73180_H
3
4/*
5 * linux/include/asm-sh/irq-sh73180.h
6 *
7 * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp>
8 */
9
10#undef INTC_IPRA
11#undef INTC_IPRB
12#undef INTC_IPRC
13#undef INTC_IPRD
14
15#undef DMTE0_IRQ
16#undef DMTE1_IRQ
17#undef DMTE2_IRQ
18#undef DMTE3_IRQ
19#undef DMTE4_IRQ
20#undef DMTE5_IRQ
21#undef DMTE6_IRQ
22#undef DMTE7_IRQ
23#undef DMAE_IRQ
24#undef DMA_IPR_ADDR
25#undef DMA_IPR_POS
26#undef DMA_PRIORITY
27
28#undef NR_IRQS
29
30#undef __irq_demux
31#undef irq_demux
32
33#undef INTC_IMCR0
34#undef INTC_IMCR1
35#undef INTC_IMCR2
36#undef INTC_IMCR3
37#undef INTC_IMCR4
38#undef INTC_IMCR5
39#undef INTC_IMCR6
40#undef INTC_IMCR7
41#undef INTC_IMCR8
42#undef INTC_IMCR9
43#undef INTC_IMCR10
44
45
46#define INTC_IPRA 0xA4080000UL
47#define INTC_IPRB 0xA4080004UL
48#define INTC_IPRC 0xA4080008UL
49#define INTC_IPRD 0xA408000CUL
50#define INTC_IPRE 0xA4080010UL
51#define INTC_IPRF 0xA4080014UL
52#define INTC_IPRG 0xA4080018UL
53#define INTC_IPRH 0xA408001CUL
54#define INTC_IPRI 0xA4080020UL
55#define INTC_IPRJ 0xA4080024UL
56#define INTC_IPRK 0xA4080028UL
57
58#define INTC_IMR0 0xA4080080UL
59#define INTC_IMR1 0xA4080084UL
60#define INTC_IMR2 0xA4080088UL
61#define INTC_IMR3 0xA408008CUL
62#define INTC_IMR4 0xA4080090UL
63#define INTC_IMR5 0xA4080094UL
64#define INTC_IMR6 0xA4080098UL
65#define INTC_IMR7 0xA408009CUL
66#define INTC_IMR8 0xA40800A0UL
67#define INTC_IMR9 0xA40800A4UL
68#define INTC_IMR10 0xA40800A8UL
69#define INTC_IMR11 0xA40800ACUL
70
71#define INTC_IMCR0 0xA40800C0UL
72#define INTC_IMCR1 0xA40800C4UL
73#define INTC_IMCR2 0xA40800C8UL
74#define INTC_IMCR3 0xA40800CCUL
75#define INTC_IMCR4 0xA40800D0UL
76#define INTC_IMCR5 0xA40800D4UL
77#define INTC_IMCR6 0xA40800D8UL
78#define INTC_IMCR7 0xA40800DCUL
79#define INTC_IMCR8 0xA40800E0UL
80#define INTC_IMCR9 0xA40800E4UL
81#define INTC_IMCR10 0xA40800E8UL
82#define INTC_IMCR11 0xA40800ECUL
83
84#define INTC_ICR0 0xA4140000UL
85#define INTC_ICR1 0xA414001CUL
86
87#define INTMSK0 0xa4140044
88#define INTMSKCLR0 0xa4140064
89#define INTC_INTPRI0 0xa4140010
90
91/*
92 NOTE:
93
94 *_IRQ = (INTEVT2 - 0x200)/0x20
95*/
96
97/* TMU0 */
98#define TMU0_IRQ 16
99#define TMU0_IPR_ADDR INTC_IPRA
100#define TMU0_IPR_POS 3
101#define TMU0_PRIORITY 2
102
103#define TIMER_IRQ 16
104#define TIMER_IPR_ADDR INTC_IPRA
105#define TIMER_IPR_POS 3
106#define TIMER_PRIORITY 2
107
108/* TMU1 */
109#define TMU1_IRQ 17
110#define TMU1_IPR_ADDR INTC_IPRA
111#define TMU1_IPR_POS 2
112#define TMU1_PRIORITY 2
113
114/* TMU2 */
115#define TMU2_IRQ 18
116#define TMU2_IPR_ADDR INTC_IPRA
117#define TMU2_IPR_POS 1
118#define TMU2_PRIORITY 2
119
120/* LCDC */
121#define LCDC_IRQ 28
122#define LCDC_IPR_ADDR INTC_IPRB
123#define LCDC_IPR_POS 2
124#define LCDC_PRIORITY 2
125
126/* VIO (Video I/O) */
127#define CEU_IRQ 52
128#define BEU_IRQ 53
129#define VEU_IRQ 54
130#define VOU_IRQ 55
131#define VIO_IPR_ADDR INTC_IPRE
132#define VIO_IPR_POS 2
133#define VIO_PRIORITY 2
134
135/* MFI (Multi Functional Interface) */
136#define MFI_IRQ 56
137#define MFI_IPR_ADDR INTC_IPRE
138#define MFI_IPR_POS 1
139#define MFI_PRIORITY 2
140
141/* VPU (Video Processing Unit) */
142#define VPU_IRQ 60
143#define VPU_IPR_ADDR INTC_IPRE
144#define VPU_IPR_POS 0
145#define VPU_PRIORITY 2
146
147/* 3DG */
148#define TDG_IRQ 63
149#define TDG_IPR_ADDR INTC_IPRJ
150#define TDG_IPR_POS 2
151#define TDG_PRIORITY 2
152
153/* DMAC(1) */
154#define DMTE0_IRQ 48
155#define DMTE1_IRQ 49
156#define DMTE2_IRQ 50
157#define DMTE3_IRQ 51
158#define DMA1_IPR_ADDR INTC_IPRE
159#define DMA1_IPR_POS 3
160#define DMA1_PRIORITY 7
161
162/* DMAC(2) */
163#define DMTE4_IRQ 76
164#define DMTE5_IRQ 77
165#define DMA2_IPR_ADDR INTC_IPRF
166#define DMA2_IPR_POS 2
167#define DMA2_PRIORITY 7
168
169/* SCIF0 */
170#define SCIF_ERI_IRQ 80
171#define SCIF_RXI_IRQ 81
172#define SCIF_BRI_IRQ 82
173#define SCIF_TXI_IRQ 83
174#define SCIF_IPR_ADDR INTC_IPRG
175#define SCIF_IPR_POS 3
176#define SCIF_PRIORITY 3
177
178/* SIOF0 */
179#define SIOF0_IRQ 84
180#define SIOF0_IPR_ADDR INTC_IPRH
181#define SIOF0_IPR_POS 3
182#define SIOF0_PRIORITY 3
183
184/* FLCTL (Flash Memory Controller) */
185#define FLSTE_IRQ 92
186#define FLTEND_IRQ 93
187#define FLTRQ0_IRQ 94
188#define FLTRQ1_IRQ 95
189#define FLCTL_IPR_ADDR INTC_IPRH
190#define FLCTL_IPR_POS 1
191#define FLCTL_PRIORITY 3
192
193/* IIC(0) (IIC Bus Interface) */
194#define IIC0_ALI_IRQ 96
195#define IIC0_TACKI_IRQ 97
196#define IIC0_WAITI_IRQ 98
197#define IIC0_DTEI_IRQ 99
198#define IIC0_IPR_ADDR INTC_IPRH
199#define IIC0_IPR_POS 0
200#define IIC0_PRIORITY 3
201
202/* IIC(1) (IIC Bus Interface) */
203#define IIC1_ALI_IRQ 44
204#define IIC1_TACKI_IRQ 45
205#define IIC1_WAITI_IRQ 46
206#define IIC1_DTEI_IRQ 47
207#define IIC1_IPR_ADDR INTC_IPRG
208#define IIC1_IPR_POS 0
209#define IIC1_PRIORITY 3
210
211/* SIO0 */
212#define SIO0_IRQ 88
213#define SIO0_IPR_ADDR INTC_IPRI
214#define SIO0_IPR_POS 3
215#define SIO0_PRIORITY 3
216
217/* SDHI */
218#define SDHI_SDHII0_IRQ 100
219#define SDHI_SDHII1_IRQ 101
220#define SDHI_SDHII2_IRQ 102
221#define SDHI_SDHII3_IRQ 103
222#define SDHI_IPR_ADDR INTC_IPRK
223#define SDHI_IPR_POS 0
224#define SDHI_PRIORITY 3
225
226/* SIU (Sound Interface Unit) */
227#define SIU_IRQ 108
228#define SIU_IPR_ADDR INTC_IPRJ
229#define SIU_IPR_POS 1
230#define SIU_PRIORITY 3
231
232
233/* ONCHIP_NR_IRQS */
234#define NR_IRQS 109
235
236/* In a generic kernel, NR_IRQS is an upper bound, and we should use
237 * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
238 */
239#define ACTUAL_NR_IRQS NR_IRQS
240
241
242extern void disable_irq(unsigned int);
243extern void disable_irq_nosync(unsigned int);
244extern void enable_irq(unsigned int);
245
246/*
247 * Simple Mask Register Support
248 */
249extern void make_maskreg_irq(unsigned int irq);
250extern unsigned short *irq_mask_register;
251
252/*
253 * Function for "on chip support modules".
254 */
255extern void make_ipr_irq(unsigned int irq, unsigned int addr,
256 int pos, int priority);
257extern void make_imask_irq(unsigned int irq);
258
259#define PORT_PACR 0xA4050100UL
260#define PORT_PBCR 0xA4050102UL
261#define PORT_PCCR 0xA4050104UL
262#define PORT_PDCR 0xA4050106UL
263#define PORT_PECR 0xA4050108UL
264#define PORT_PFCR 0xA405010AUL
265#define PORT_PGCR 0xA405010CUL
266#define PORT_PHCR 0xA405010EUL
267#define PORT_PJCR 0xA4050110UL
268#define PORT_PKCR 0xA4050112UL
269#define PORT_PLCR 0xA4050114UL
270#define PORT_SCPCR 0xA4050116UL
271#define PORT_PMCR 0xA4050118UL
272#define PORT_PNCR 0xA405011AUL
273#define PORT_PQCR 0xA405011CUL
274#define PORT_PRCR 0xA405011EUL
275#define PORT_PTCR 0xA405014CUL
276#define PORT_PUCR 0xA405014EUL
277#define PORT_PVCR 0xA4050150UL
278
279#define PORT_PSELA 0xA4050140UL
280#define PORT_PSELB 0xA4050142UL
281#define PORT_PSELC 0xA4050144UL
282#define PORT_PSELE 0xA4050158UL
283
284#define PORT_HIZCRA 0xA4050146UL
285#define PORT_HIZCRB 0xA4050148UL
286#define PORT_DRVCR 0xA405014AUL
287
288#define PORT_PADR 0xA4050120UL
289#define PORT_PBDR 0xA4050122UL
290#define PORT_PCDR 0xA4050124UL
291#define PORT_PDDR 0xA4050126UL
292#define PORT_PEDR 0xA4050128UL
293#define PORT_PFDR 0xA405012AUL
294#define PORT_PGDR 0xA405012CUL
295#define PORT_PHDR 0xA405012EUL
296#define PORT_PJDR 0xA4050130UL
297#define PORT_PKDR 0xA4050132UL
298#define PORT_PLDR 0xA4050134UL
299#define PORT_SCPDR 0xA4050136UL
300#define PORT_PMDR 0xA4050138UL
301#define PORT_PNDR 0xA405013AUL
302#define PORT_PQDR 0xA405013CUL
303#define PORT_PRDR 0xA405013EUL
304#define PORT_PTDR 0xA405016CUL
305#define PORT_PUDR 0xA405016EUL
306#define PORT_PVDR 0xA4050170UL
307
308#define IRQ0_IRQ 32
309#define IRQ1_IRQ 33
310#define IRQ2_IRQ 34
311#define IRQ3_IRQ 35
312#define IRQ4_IRQ 36
313#define IRQ5_IRQ 37
314#define IRQ6_IRQ 38
315#define IRQ7_IRQ 39
316
317#define INTPRI00 0xA4140010UL
318
319#define IRQ0_IPR_ADDR INTPRI00
320#define IRQ1_IPR_ADDR INTPRI00
321#define IRQ2_IPR_ADDR INTPRI00
322#define IRQ3_IPR_ADDR INTPRI00
323#define IRQ4_IPR_ADDR INTPRI00
324#define IRQ5_IPR_ADDR INTPRI00
325#define IRQ6_IPR_ADDR INTPRI00
326#define IRQ7_IPR_ADDR INTPRI00
327
328#define IRQ0_IPR_POS 7
329#define IRQ1_IPR_POS 6
330#define IRQ2_IPR_POS 5
331#define IRQ3_IPR_POS 4
332#define IRQ4_IPR_POS 3
333#define IRQ5_IPR_POS 2
334#define IRQ6_IPR_POS 1
335#define IRQ7_IPR_POS 0
336
337#define IRQ0_PRIORITY 1
338#define IRQ1_PRIORITY 1
339#define IRQ2_PRIORITY 1
340#define IRQ3_PRIORITY 1
341#define IRQ4_PRIORITY 1
342#define IRQ5_PRIORITY 1
343#define IRQ6_PRIORITY 1
344#define IRQ7_PRIORITY 1
345
346extern int shmse_irq_demux(int irq);
347#define __irq_demux(irq) shmse_irq_demux(irq)
348#define irq_demux(irq) __irq_demux(irq)
349
350#endif /* __ASM_SH_IRQ_SH73180_H */