Linux kernel mirror (for testing)
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linux
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12#include <linux/config.h>
13
14/*
15 * This assumes you have a 1.8432 MHz clock for your UART.
16 *
17 * It'd be nice if someone built a serial card with a 24.576 MHz
18 * clock, since the 16550A is capable of handling a top speed of 1.5
19 * megabits/second; but this requires the faster clock.
20 */
21#define BASE_BAUD (1843200 / 16)
22
23/* Standard COM flags (except for COM4, because of the 8514 problem) */
24#ifdef CONFIG_SERIAL_DETECT_IRQ
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
26#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
27#else
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif
31
32#ifdef CONFIG_MACH_JAZZ
33#include <asm/jazz.h>
34
35#ifndef CONFIG_OLIVETTI_M700
36 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
37 exactly which ones ... XXX */
38#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
39#else
40/* but the M700 isn't such a strange beast */
41#define JAZZ_BASE_BAUD BASE_BAUD
42#endif
43
44#define _JAZZ_SERIAL_INIT(int, base) \
45 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
46 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
47 .io_type = SERIAL_IO_MEM }
48#define JAZZ_SERIAL_PORT_DEFNS \
49 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
50 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
51#else
52#define JAZZ_SERIAL_PORT_DEFNS
53#endif
54
55#ifdef CONFIG_MIPS_COBALT
56#include <asm/cobalt/cobalt.h>
57#define COBALT_BASE_BAUD (18432000 / 16)
58#define COBALT_SERIAL_PORT_DEFNS \
59 /* UART CLK PORT IRQ FLAGS */ \
60 { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
61#else
62#define COBALT_SERIAL_PORT_DEFNS
63#endif
64
65/*
66 * Both Galileo boards have the same UART mappings.
67 */
68#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
69#include <asm/galileo-boards/ev96100.h>
70#include <asm/galileo-boards/ev96100int.h>
71#define EV96100_SERIAL_PORT_DEFNS \
72 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
73 .flags = STD_COM_FLAGS, \
74 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
75 .io_type = SERIAL_IO_MEM }, \
76 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
77 .flags = STD_COM_FLAGS, \
78 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
79 .io_type = SERIAL_IO_MEM },
80#else
81#define EV96100_SERIAL_PORT_DEFNS
82#endif
83
84#ifdef CONFIG_MIPS_ITE8172
85#include <asm/it8172/it8172.h>
86#include <asm/it8172/it8172_int.h>
87#include <asm/it8712.h>
88#define ITE_SERIAL_PORT_DEFNS \
89 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
90 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
91 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
92 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
93 /* Smart Card Reader 0 */ \
94 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
95 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
96 /* Smart Card Reader 1 */ \
97 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
98 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
99#else
100#define ITE_SERIAL_PORT_DEFNS
101#endif
102
103#ifdef CONFIG_MIPS_IVR
104#include <asm/it8172/it8172.h>
105#include <asm/it8172/it8172_int.h>
106#define IVR_SERIAL_PORT_DEFNS \
107 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
108 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
109 /* Smart Card Reader 1 */ \
110 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
111 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
112#else
113#define IVR_SERIAL_PORT_DEFNS
114#endif
115
116#ifdef CONFIG_TOSHIBA_JMR3927
117#include <asm/jmr3927/jmr3927.h>
118#define TXX927_SERIAL_PORT_DEFNS \
119 { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
120 .flags = UART0_FLAGS, .type = 1 }, \
121 { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
122 .flags = UART1_FLAGS, .type = 1 },
123#else
124#define TXX927_SERIAL_PORT_DEFNS
125#endif
126
127#ifdef CONFIG_SERIAL_AU1X00
128#include <asm/mach-au1x00/au1000.h>
129#ifdef CONFIG_SOC_AU1000
130#define AU1000_SERIAL_PORT_DEFNS \
131 { .baud_base = 0, .port = UART0_ADDR, \
132 .iomem_base = (unsigned char *)UART0_ADDR, \
133 .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
134 .iomem_reg_shift = 2 }, \
135 { .baud_base = 0, .port = UART1_ADDR, \
136 .iomem_base = (unsigned char *)UART1_ADDR, \
137 .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
138 .iomem_reg_shift = 2 }, \
139 { .baud_base = 0, .port = UART2_ADDR, \
140 .iomem_base = (unsigned char *)UART2_ADDR, \
141 .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
142 .iomem_reg_shift = 2 }, \
143 { .baud_base = 0, .port = UART3_ADDR, \
144 .iomem_base = (unsigned char *)UART3_ADDR, \
145 .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
146 .iomem_reg_shift = 2 },
147#endif
148
149#ifdef CONFIG_SOC_AU1500
150#define AU1000_SERIAL_PORT_DEFNS \
151 { .baud_base = 0, .port = UART0_ADDR, \
152 .iomem_base = (unsigned char *)UART0_ADDR, \
153 .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
154 .iomem_reg_shift = 2 }, \
155 { .baud_base = 0, .port = UART3_ADDR, \
156 .iomem_base = (unsigned char *)UART3_ADDR, \
157 .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
158 .iomem_reg_shift = 2 },
159#endif
160
161#ifdef CONFIG_SOC_AU1100
162#define AU1000_SERIAL_PORT_DEFNS \
163 { .baud_base = 0, .port = UART0_ADDR, \
164 .iomem_base = (unsigned char *)UART0_ADDR, \
165 .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
166 .iomem_reg_shift = 2 }, \
167 { .baud_base = 0, .port = UART1_ADDR, \
168 .iomem_base = (unsigned char *)UART1_ADDR, \
169 .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
170 .iomem_reg_shift = 2 }, \
171 { .baud_base = 0, .port = UART3_ADDR, \
172 .iomem_base = (unsigned char *)UART3_ADDR, \
173 .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
174 .iomem_reg_shift = 2 },
175#endif
176
177#ifdef CONFIG_SOC_AU1550
178#define AU1000_SERIAL_PORT_DEFNS \
179 { .baud_base = 0, .port = UART0_ADDR, \
180 .iomem_base = (unsigned char *)UART0_ADDR, \
181 .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
182 .iomem_reg_shift = 2 }, \
183 { .baud_base = 0, .port = UART1_ADDR, \
184 .iomem_base = (unsigned char *)UART1_ADDR, \
185 .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
186 .iomem_reg_shift = 2 }, \
187 { .baud_base = 0, .port = UART3_ADDR, \
188 .iomem_base = (unsigned char *)UART3_ADDR, \
189 .irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
190 .iomem_reg_shift = 2 },
191#endif
192
193#ifdef CONFIG_SOC_AU1200
194#define AU1000_SERIAL_PORT_DEFNS \
195 { .baud_base = 0, .port = UART0_ADDR, \
196 .iomem_base = (unsigned char *)UART0_ADDR, \
197 .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
198 .iomem_reg_shift = 2 }, \
199 { .baud_base = 0, .port = UART1_ADDR, \
200 .iomem_base = (unsigned char *)UART1_ADDR, \
201 .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
202 .iomem_reg_shift = 2 },
203#endif
204
205#else
206#define AU1000_SERIAL_PORT_DEFNS
207#endif
208
209#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
210#define STD_SERIAL_PORT_DEFNS \
211 /* UART CLK PORT IRQ FLAGS */ \
212 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
213 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
214 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
215 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
216
217#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
218#define STD_SERIAL_PORT_DEFNS
219#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
220
221#ifdef CONFIG_MOMENCO_JAGUAR_ATX
222/* Ordinary NS16552 duart with a 20MHz crystal. */
223#define JAGUAR_ATX_UART_CLK 20000000
224#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
225
226#define JAGUAR_ATX_SERIAL1_IRQ 6
227#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
228
229#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
230 { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
231 flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
232 iomem_base: (u8 *) base, iomem_reg_shift: 2, \
233 io_type: SERIAL_IO_MEM }
234#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
235 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
236#else
237#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
238#endif
239
240#ifdef CONFIG_MOMENCO_OCELOT_3
241#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
242#define OCELOT_3_SERIAL_IRQ 6
243#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
244
245#define _OCELOT_3_SERIAL_INIT(int, base) \
246 { baud_base: OCELOT_3_BASE_BAUD, irq: int, \
247 flags: STD_COM_FLAGS, \
248 iomem_base: (u8 *) base, iomem_reg_shift: 2, \
249 io_type: SERIAL_IO_MEM }
250
251#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
252 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
253#else
254#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
255#endif
256
257#ifdef CONFIG_MOMENCO_OCELOT
258/* Ordinary NS16552 duart with a 20MHz crystal. */
259#define OCELOT_BASE_BAUD ( 20000000 / 16 )
260
261#define OCELOT_SERIAL1_IRQ 4
262#define OCELOT_SERIAL1_BASE 0xe0001020
263
264#define _OCELOT_SERIAL_INIT(int, base) \
265 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
266 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
267 .io_type = SERIAL_IO_MEM }
268#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
269 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
270#else
271#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
272#endif
273
274#ifdef CONFIG_MOMENCO_OCELOT_G
275/* Ordinary NS16552 duart with a 20MHz crystal. */
276#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
277
278#define OCELOT_G_SERIAL1_IRQ 4
279#if 0
280#define OCELOT_G_SERIAL1_BASE 0xe0001020
281#else
282#define OCELOT_G_SERIAL1_BASE 0xfd000020
283#endif
284
285#define _OCELOT_G_SERIAL_INIT(int, base) \
286 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
287 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
288 .io_type = SERIAL_IO_MEM }
289#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
290 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
291#else
292#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
293#endif
294
295#ifdef CONFIG_MOMENCO_OCELOT_C
296/* Ordinary NS16552 duart with a 20MHz crystal. */
297#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
298
299#define OCELOT_C_SERIAL1_IRQ 80
300#define OCELOT_C_SERIAL1_BASE 0xfd000020
301
302#define OCELOT_C_SERIAL2_IRQ 81
303#define OCELOT_C_SERIAL2_BASE 0xfd000000
304
305#define _OCELOT_C_SERIAL_INIT(int, base) \
306 { .baud_base = OCELOT_C_BASE_BAUD, \
307 .irq = (int), \
308 .flags = STD_COM_FLAGS, \
309 .iomem_base = (u8 *) base, \
310 .iomem_reg_shift = 2, \
311 .io_type = SERIAL_IO_MEM \
312 }
313#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
314 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
315 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
316#else
317#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
318#endif
319
320#ifdef CONFIG_DDB5477
321#include <asm/ddb5xxx/ddb5477.h>
322#define DDB5477_SERIAL_PORT_DEFNS \
323 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
324 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
325 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
326 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
327 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
328 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
329#else
330#define DDB5477_SERIAL_PORT_DEFNS
331#endif
332
333#ifdef CONFIG_SGI_IP32
334/*
335 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
336 * They are initialized in ip32_setup
337 */
338#define IP32_SERIAL_PORT_DEFNS \
339 {},{},
340#else
341#define IP32_SERIAL_PORT_DEFNS
342#endif /* CONFIG_SGI_IP32 */
343
344#define SERIAL_PORT_DFNS \
345 COBALT_SERIAL_PORT_DEFNS \
346 DDB5477_SERIAL_PORT_DEFNS \
347 EV96100_SERIAL_PORT_DEFNS \
348 IP32_SERIAL_PORT_DEFNS \
349 ITE_SERIAL_PORT_DEFNS \
350 IVR_SERIAL_PORT_DEFNS \
351 JAZZ_SERIAL_PORT_DEFNS \
352 STD_SERIAL_PORT_DEFNS \
353 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
354 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
355 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
356 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
357 TXX927_SERIAL_PORT_DEFNS \
358 AU1000_SERIAL_PORT_DEFNS
359
360#endif /* _ASM_SERIAL_H */