tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
14
15/* CPM Command register.
16*/
17#define CPM_CR_RST ((uint)0x80000000)
18#define CPM_CR_PAGE ((uint)0x7c000000)
19#define CPM_CR_SBLOCK ((uint)0x03e00000)
20#define CPM_CR_FLG ((uint)0x00010000)
21#define CPM_CR_MCN ((uint)0x00003fc0)
22#define CPM_CR_OPCODE ((uint)0x0000000f)
23
24/* Device sub-block and page codes.
25*/
26#define CPM_CR_SCC1_SBLOCK (0x04)
27#define CPM_CR_SCC2_SBLOCK (0x05)
28#define CPM_CR_SCC3_SBLOCK (0x06)
29#define CPM_CR_SCC4_SBLOCK (0x07)
30#define CPM_CR_SMC1_SBLOCK (0x08)
31#define CPM_CR_SMC2_SBLOCK (0x09)
32#define CPM_CR_SPI_SBLOCK (0x0a)
33#define CPM_CR_I2C_SBLOCK (0x0b)
34#define CPM_CR_TIMER_SBLOCK (0x0f)
35#define CPM_CR_RAND_SBLOCK (0x0e)
36#define CPM_CR_FCC1_SBLOCK (0x10)
37#define CPM_CR_FCC2_SBLOCK (0x11)
38#define CPM_CR_FCC3_SBLOCK (0x12)
39#define CPM_CR_IDMA1_SBLOCK (0x14)
40#define CPM_CR_IDMA2_SBLOCK (0x15)
41#define CPM_CR_IDMA3_SBLOCK (0x16)
42#define CPM_CR_IDMA4_SBLOCK (0x17)
43#define CPM_CR_MCC1_SBLOCK (0x1c)
44
45#define CPM_CR_SCC1_PAGE (0x00)
46#define CPM_CR_SCC2_PAGE (0x01)
47#define CPM_CR_SCC3_PAGE (0x02)
48#define CPM_CR_SCC4_PAGE (0x03)
49#define CPM_CR_SMC1_PAGE (0x07)
50#define CPM_CR_SMC2_PAGE (0x08)
51#define CPM_CR_SPI_PAGE (0x09)
52#define CPM_CR_I2C_PAGE (0x0a)
53#define CPM_CR_TIMER_PAGE (0x0a)
54#define CPM_CR_RAND_PAGE (0x0a)
55#define CPM_CR_FCC1_PAGE (0x04)
56#define CPM_CR_FCC2_PAGE (0x05)
57#define CPM_CR_FCC3_PAGE (0x06)
58#define CPM_CR_IDMA1_PAGE (0x07)
59#define CPM_CR_IDMA2_PAGE (0x08)
60#define CPM_CR_IDMA3_PAGE (0x09)
61#define CPM_CR_IDMA4_PAGE (0x0a)
62#define CPM_CR_MCC1_PAGE (0x07)
63#define CPM_CR_MCC2_PAGE (0x08)
64
65/* Some opcodes (there are more...later)
66*/
67#define CPM_CR_INIT_TRX ((ushort)0x0000)
68#define CPM_CR_INIT_RX ((ushort)0x0001)
69#define CPM_CR_INIT_TX ((ushort)0x0002)
70#define CPM_CR_HUNT_MODE ((ushort)0x0003)
71#define CPM_CR_STOP_TX ((ushort)0x0004)
72#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
73#define CPM_CR_RESTART_TX ((ushort)0x0006)
74#define CPM_CR_SET_GADDR ((ushort)0x0008)
75#define CPM_CR_START_IDMA ((ushort)0x0009)
76#define CPM_CR_STOP_IDMA ((ushort)0x000b)
77
78#define mk_cr_cmd(PG, SBC, MCN, OP) \
79 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
80
81/* Dual Port RAM addresses. The first 16K is available for almost
82 * any CPM use, so we put the BDs there. The first 128 bytes are
83 * used for SMC1 and SMC2 parameter RAM, so we start allocating
84 * BDs above that. All of this must change when we start
85 * downloading RAM microcode.
86 */
87#define CPM_DATAONLY_BASE ((uint)128)
88#define CPM_DP_NOSPACE ((uint)0x7fffffff)
89#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
90#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
91#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
92#else
93#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
94#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
95#endif
96
97/* The number of pages of host memory we allocate for CPM. This is
98 * done early in kernel initialization to get physically contiguous
99 * pages.
100 */
101#define NUM_CPM_HOST_PAGES 2
102
103static inline long IS_DPERR(const uint offset)
104{
105 return (uint)offset > (uint)-1000L;
106}
107
108/* Export the base address of the communication processor registers
109 * and dual port ram.
110 */
111extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */
112extern uint cpm_dpalloc(uint size, uint align);
113extern int cpm_dpfree(uint offset);
114extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
115extern void cpm_dpdump(void);
116extern void *cpm_dpram_addr(uint offset);
117extern void cpm_setbrg(uint brg, uint rate);
118extern void cpm2_fastbrg(uint brg, uint rate, int div16);
119
120/* Buffer descriptors used by many of the CPM protocols.
121*/
122typedef struct cpm_buf_desc {
123 ushort cbd_sc; /* Status and Control */
124 ushort cbd_datlen; /* Data length in buffer */
125 uint cbd_bufaddr; /* Buffer address in host memory */
126} cbd_t;
127
128#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
129#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
130#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
131#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
132#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
133#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
134#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
135#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
136#define BD_SC_BR ((ushort)0x0020) /* Break received */
137#define BD_SC_FR ((ushort)0x0010) /* Framing error */
138#define BD_SC_PR ((ushort)0x0008) /* Parity error */
139#define BD_SC_OV ((ushort)0x0002) /* Overrun */
140#define BD_SC_CD ((ushort)0x0001) /* ?? */
141
142/* Function code bits, usually generic to devices.
143*/
144#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
145#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
146#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
147#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
148#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
149
150/* Parameter RAM offsets from the base.
151*/
152#define PROFF_SCC1 ((uint)0x8000)
153#define PROFF_SCC2 ((uint)0x8100)
154#define PROFF_SCC3 ((uint)0x8200)
155#define PROFF_SCC4 ((uint)0x8300)
156#define PROFF_FCC1 ((uint)0x8400)
157#define PROFF_FCC2 ((uint)0x8500)
158#define PROFF_FCC3 ((uint)0x8600)
159#define PROFF_MCC1 ((uint)0x8700)
160#define PROFF_SMC1_BASE ((uint)0x87fc)
161#define PROFF_IDMA1_BASE ((uint)0x87fe)
162#define PROFF_MCC2 ((uint)0x8800)
163#define PROFF_SMC2_BASE ((uint)0x88fc)
164#define PROFF_IDMA2_BASE ((uint)0x88fe)
165#define PROFF_SPI_BASE ((uint)0x89fc)
166#define PROFF_IDMA3_BASE ((uint)0x89fe)
167#define PROFF_TIMERS ((uint)0x8ae0)
168#define PROFF_REVNUM ((uint)0x8af0)
169#define PROFF_RAND ((uint)0x8af8)
170#define PROFF_I2C_BASE ((uint)0x8afc)
171#define PROFF_IDMA4_BASE ((uint)0x8afe)
172
173/* The SMCs are relocated to any of the first eight DPRAM pages.
174 * We will fix these at the first locations of DPRAM, until we
175 * get some microcode patches :-).
176 * The parameter ram space for the SMCs is fifty-some bytes, and
177 * they are required to start on a 64 byte boundary.
178 */
179#define PROFF_SMC1 (0)
180#define PROFF_SMC2 (64)
181
182
183/* Define enough so I can at least use the serial port as a UART.
184 */
185typedef struct smc_uart {
186 ushort smc_rbase; /* Rx Buffer descriptor base address */
187 ushort smc_tbase; /* Tx Buffer descriptor base address */
188 u_char smc_rfcr; /* Rx function code */
189 u_char smc_tfcr; /* Tx function code */
190 ushort smc_mrblr; /* Max receive buffer length */
191 uint smc_rstate; /* Internal */
192 uint smc_idp; /* Internal */
193 ushort smc_rbptr; /* Internal */
194 ushort smc_ibc; /* Internal */
195 uint smc_rxtmp; /* Internal */
196 uint smc_tstate; /* Internal */
197 uint smc_tdp; /* Internal */
198 ushort smc_tbptr; /* Internal */
199 ushort smc_tbc; /* Internal */
200 uint smc_txtmp; /* Internal */
201 ushort smc_maxidl; /* Maximum idle characters */
202 ushort smc_tmpidl; /* Temporary idle counter */
203 ushort smc_brklen; /* Last received break length */
204 ushort smc_brkec; /* rcv'd break condition counter */
205 ushort smc_brkcr; /* xmt break count register */
206 ushort smc_rmask; /* Temporary bit mask */
207 uint smc_stmp; /* SDMA Temp */
208} smc_uart_t;
209
210/* SMC uart mode register (Internal memory map).
211*/
212#define SMCMR_REN ((ushort)0x0001)
213#define SMCMR_TEN ((ushort)0x0002)
214#define SMCMR_DM ((ushort)0x000c)
215#define SMCMR_SM_GCI ((ushort)0x0000)
216#define SMCMR_SM_UART ((ushort)0x0020)
217#define SMCMR_SM_TRANS ((ushort)0x0030)
218#define SMCMR_SM_MASK ((ushort)0x0030)
219#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
220#define SMCMR_REVD SMCMR_PM_EVEN
221#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
222#define SMCMR_BS SMCMR_PEN
223#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
224#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
225#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
226
227/* SMC Event and Mask register.
228*/
229#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
230#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
231#define SMCM_TXE ((unsigned char)0x10)
232#define SMCM_BSY ((unsigned char)0x04)
233#define SMCM_TX ((unsigned char)0x02)
234#define SMCM_RX ((unsigned char)0x01)
235
236/* Baud rate generators.
237*/
238#define CPM_BRG_RST ((uint)0x00020000)
239#define CPM_BRG_EN ((uint)0x00010000)
240#define CPM_BRG_EXTC_INT ((uint)0x00000000)
241#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
242#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
243#define CPM_BRG_ATB ((uint)0x00002000)
244#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
245#define CPM_BRG_DIV16 ((uint)0x00000001)
246
247/* SCCs.
248*/
249#define SCC_GSMRH_IRP ((uint)0x00040000)
250#define SCC_GSMRH_GDE ((uint)0x00010000)
251#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
252#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
253#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
254#define SCC_GSMRH_REVD ((uint)0x00002000)
255#define SCC_GSMRH_TRX ((uint)0x00001000)
256#define SCC_GSMRH_TTX ((uint)0x00000800)
257#define SCC_GSMRH_CDP ((uint)0x00000400)
258#define SCC_GSMRH_CTSP ((uint)0x00000200)
259#define SCC_GSMRH_CDS ((uint)0x00000100)
260#define SCC_GSMRH_CTSS ((uint)0x00000080)
261#define SCC_GSMRH_TFL ((uint)0x00000040)
262#define SCC_GSMRH_RFW ((uint)0x00000020)
263#define SCC_GSMRH_TXSY ((uint)0x00000010)
264#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
265#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
266#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
267#define SCC_GSMRH_RTSM ((uint)0x00000002)
268#define SCC_GSMRH_RSYN ((uint)0x00000001)
269
270#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
271#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
272#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
273#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
274#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
275#define SCC_GSMRL_TCI ((uint)0x10000000)
276#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
277#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
278#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
279#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
280#define SCC_GSMRL_RINV ((uint)0x02000000)
281#define SCC_GSMRL_TINV ((uint)0x01000000)
282#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
283#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
284#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
285#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
286#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
287#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
288#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
289#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
290#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
291#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
292#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
293#define SCC_GSMRL_TEND ((uint)0x00040000)
294#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
295#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
296#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
297#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
298#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
299#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
300#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
301#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
302#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
303#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
304#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
305#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
306#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
307#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
308#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
309#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
310#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
311#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
312#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
313#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
314#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
315#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
316#define SCC_GSMRL_ENR ((uint)0x00000020)
317#define SCC_GSMRL_ENT ((uint)0x00000010)
318#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
319#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
320#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
321#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
322#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
323#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
324#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
325#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
326#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
327#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
328
329#define SCC_TODR_TOD ((ushort)0x8000)
330
331/* SCC Event and Mask register.
332*/
333#define SCCM_TXE ((unsigned char)0x10)
334#define SCCM_BSY ((unsigned char)0x04)
335#define SCCM_TX ((unsigned char)0x02)
336#define SCCM_RX ((unsigned char)0x01)
337
338typedef struct scc_param {
339 ushort scc_rbase; /* Rx Buffer descriptor base address */
340 ushort scc_tbase; /* Tx Buffer descriptor base address */
341 u_char scc_rfcr; /* Rx function code */
342 u_char scc_tfcr; /* Tx function code */
343 ushort scc_mrblr; /* Max receive buffer length */
344 uint scc_rstate; /* Internal */
345 uint scc_idp; /* Internal */
346 ushort scc_rbptr; /* Internal */
347 ushort scc_ibc; /* Internal */
348 uint scc_rxtmp; /* Internal */
349 uint scc_tstate; /* Internal */
350 uint scc_tdp; /* Internal */
351 ushort scc_tbptr; /* Internal */
352 ushort scc_tbc; /* Internal */
353 uint scc_txtmp; /* Internal */
354 uint scc_rcrc; /* Internal */
355 uint scc_tcrc; /* Internal */
356} sccp_t;
357
358/* CPM Ethernet through SCC1.
359 */
360typedef struct scc_enet {
361 sccp_t sen_genscc;
362 uint sen_cpres; /* Preset CRC */
363 uint sen_cmask; /* Constant mask for CRC */
364 uint sen_crcec; /* CRC Error counter */
365 uint sen_alec; /* alignment error counter */
366 uint sen_disfc; /* discard frame counter */
367 ushort sen_pads; /* Tx short frame pad character */
368 ushort sen_retlim; /* Retry limit threshold */
369 ushort sen_retcnt; /* Retry limit counter */
370 ushort sen_maxflr; /* maximum frame length register */
371 ushort sen_minflr; /* minimum frame length register */
372 ushort sen_maxd1; /* maximum DMA1 length */
373 ushort sen_maxd2; /* maximum DMA2 length */
374 ushort sen_maxd; /* Rx max DMA */
375 ushort sen_dmacnt; /* Rx DMA counter */
376 ushort sen_maxb; /* Max BD byte count */
377 ushort sen_gaddr1; /* Group address filter */
378 ushort sen_gaddr2;
379 ushort sen_gaddr3;
380 ushort sen_gaddr4;
381 uint sen_tbuf0data0; /* Save area 0 - current frame */
382 uint sen_tbuf0data1; /* Save area 1 - current frame */
383 uint sen_tbuf0rba; /* Internal */
384 uint sen_tbuf0crc; /* Internal */
385 ushort sen_tbuf0bcnt; /* Internal */
386 ushort sen_paddrh; /* physical address (MSB) */
387 ushort sen_paddrm;
388 ushort sen_paddrl; /* physical address (LSB) */
389 ushort sen_pper; /* persistence */
390 ushort sen_rfbdptr; /* Rx first BD pointer */
391 ushort sen_tfbdptr; /* Tx first BD pointer */
392 ushort sen_tlbdptr; /* Tx last BD pointer */
393 uint sen_tbuf1data0; /* Save area 0 - current frame */
394 uint sen_tbuf1data1; /* Save area 1 - current frame */
395 uint sen_tbuf1rba; /* Internal */
396 uint sen_tbuf1crc; /* Internal */
397 ushort sen_tbuf1bcnt; /* Internal */
398 ushort sen_txlen; /* Tx Frame length counter */
399 ushort sen_iaddr1; /* Individual address filter */
400 ushort sen_iaddr2;
401 ushort sen_iaddr3;
402 ushort sen_iaddr4;
403 ushort sen_boffcnt; /* Backoff counter */
404
405 /* NOTE: Some versions of the manual have the following items
406 * incorrectly documented. Below is the proper order.
407 */
408 ushort sen_taddrh; /* temp address (MSB) */
409 ushort sen_taddrm;
410 ushort sen_taddrl; /* temp address (LSB) */
411} scc_enet_t;
412
413
414/* SCC Event register as used by Ethernet.
415*/
416#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
417#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
418#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
419#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
420#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
421#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
422
423/* SCC Mode Register (PSMR) as used by Ethernet.
424*/
425#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
426#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
427#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
428#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
429#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
430#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
431#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
432#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
433#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
434#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
435#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
436#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
437#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
438
439/* Buffer descriptor control/status used by Ethernet receive.
440 * Common to SCC and FCC.
441 */
442#define BD_ENET_RX_EMPTY ((ushort)0x8000)
443#define BD_ENET_RX_WRAP ((ushort)0x2000)
444#define BD_ENET_RX_INTR ((ushort)0x1000)
445#define BD_ENET_RX_LAST ((ushort)0x0800)
446#define BD_ENET_RX_FIRST ((ushort)0x0400)
447#define BD_ENET_RX_MISS ((ushort)0x0100)
448#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
449#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
450#define BD_ENET_RX_LG ((ushort)0x0020)
451#define BD_ENET_RX_NO ((ushort)0x0010)
452#define BD_ENET_RX_SH ((ushort)0x0008)
453#define BD_ENET_RX_CR ((ushort)0x0004)
454#define BD_ENET_RX_OV ((ushort)0x0002)
455#define BD_ENET_RX_CL ((ushort)0x0001)
456#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
457
458/* Buffer descriptor control/status used by Ethernet transmit.
459 * Common to SCC and FCC.
460 */
461#define BD_ENET_TX_READY ((ushort)0x8000)
462#define BD_ENET_TX_PAD ((ushort)0x4000)
463#define BD_ENET_TX_WRAP ((ushort)0x2000)
464#define BD_ENET_TX_INTR ((ushort)0x1000)
465#define BD_ENET_TX_LAST ((ushort)0x0800)
466#define BD_ENET_TX_TC ((ushort)0x0400)
467#define BD_ENET_TX_DEF ((ushort)0x0200)
468#define BD_ENET_TX_HB ((ushort)0x0100)
469#define BD_ENET_TX_LC ((ushort)0x0080)
470#define BD_ENET_TX_RL ((ushort)0x0040)
471#define BD_ENET_TX_RCMASK ((ushort)0x003c)
472#define BD_ENET_TX_UN ((ushort)0x0002)
473#define BD_ENET_TX_CSL ((ushort)0x0001)
474#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
475
476/* SCC as UART
477*/
478typedef struct scc_uart {
479 sccp_t scc_genscc;
480 uint scc_res1; /* Reserved */
481 uint scc_res2; /* Reserved */
482 ushort scc_maxidl; /* Maximum idle chars */
483 ushort scc_idlc; /* temp idle counter */
484 ushort scc_brkcr; /* Break count register */
485 ushort scc_parec; /* receive parity error counter */
486 ushort scc_frmec; /* receive framing error counter */
487 ushort scc_nosec; /* receive noise counter */
488 ushort scc_brkec; /* receive break condition counter */
489 ushort scc_brkln; /* last received break length */
490 ushort scc_uaddr1; /* UART address character 1 */
491 ushort scc_uaddr2; /* UART address character 2 */
492 ushort scc_rtemp; /* Temp storage */
493 ushort scc_toseq; /* Transmit out of sequence char */
494 ushort scc_char1; /* control character 1 */
495 ushort scc_char2; /* control character 2 */
496 ushort scc_char3; /* control character 3 */
497 ushort scc_char4; /* control character 4 */
498 ushort scc_char5; /* control character 5 */
499 ushort scc_char6; /* control character 6 */
500 ushort scc_char7; /* control character 7 */
501 ushort scc_char8; /* control character 8 */
502 ushort scc_rccm; /* receive control character mask */
503 ushort scc_rccr; /* receive control character register */
504 ushort scc_rlbc; /* receive last break character */
505} scc_uart_t;
506
507/* SCC Event and Mask registers when it is used as a UART.
508*/
509#define UART_SCCM_GLR ((ushort)0x1000)
510#define UART_SCCM_GLT ((ushort)0x0800)
511#define UART_SCCM_AB ((ushort)0x0200)
512#define UART_SCCM_IDL ((ushort)0x0100)
513#define UART_SCCM_GRA ((ushort)0x0080)
514#define UART_SCCM_BRKE ((ushort)0x0040)
515#define UART_SCCM_BRKS ((ushort)0x0020)
516#define UART_SCCM_CCR ((ushort)0x0008)
517#define UART_SCCM_BSY ((ushort)0x0004)
518#define UART_SCCM_TX ((ushort)0x0002)
519#define UART_SCCM_RX ((ushort)0x0001)
520
521/* The SCC PSMR when used as a UART.
522*/
523#define SCU_PSMR_FLC ((ushort)0x8000)
524#define SCU_PSMR_SL ((ushort)0x4000)
525#define SCU_PSMR_CL ((ushort)0x3000)
526#define SCU_PSMR_UM ((ushort)0x0c00)
527#define SCU_PSMR_FRZ ((ushort)0x0200)
528#define SCU_PSMR_RZS ((ushort)0x0100)
529#define SCU_PSMR_SYN ((ushort)0x0080)
530#define SCU_PSMR_DRT ((ushort)0x0040)
531#define SCU_PSMR_PEN ((ushort)0x0010)
532#define SCU_PSMR_RPM ((ushort)0x000c)
533#define SCU_PSMR_REVP ((ushort)0x0008)
534#define SCU_PSMR_TPM ((ushort)0x0003)
535#define SCU_PSMR_TEVP ((ushort)0x0002)
536
537/* CPM Transparent mode SCC.
538 */
539typedef struct scc_trans {
540 sccp_t st_genscc;
541 uint st_cpres; /* Preset CRC */
542 uint st_cmask; /* Constant mask for CRC */
543} scc_trans_t;
544
545#define BD_SCC_TX_LAST ((ushort)0x0800)
546
547/* How about some FCCs.....
548*/
549#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
550#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
551#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
552#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
553#define FCC_GFMR_TCI ((uint)0x20000000)
554#define FCC_GFMR_TRX ((uint)0x10000000)
555#define FCC_GFMR_TTX ((uint)0x08000000)
556#define FCC_GFMR_TTX ((uint)0x08000000)
557#define FCC_GFMR_CDP ((uint)0x04000000)
558#define FCC_GFMR_CTSP ((uint)0x02000000)
559#define FCC_GFMR_CDS ((uint)0x01000000)
560#define FCC_GFMR_CTSS ((uint)0x00800000)
561#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
562#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
563#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
564#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
565#define FCC_GFMR_RTSM ((uint)0x00002000)
566#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
567#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
568#define FCC_GFMR_REVD ((uint)0x00000400)
569#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
570#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
571#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
572#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
573#define FCC_GFMR_ENR ((uint)0x00000020)
574#define FCC_GFMR_ENT ((uint)0x00000010)
575#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
576#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
577#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
578
579/* Generic FCC parameter ram.
580*/
581typedef struct fcc_param {
582 ushort fcc_riptr; /* Rx Internal temp pointer */
583 ushort fcc_tiptr; /* Tx Internal temp pointer */
584 ushort fcc_res1;
585 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
586 uint fcc_rstate; /* Upper byte is Func code, must be set */
587 uint fcc_rbase; /* Receive BD base */
588 ushort fcc_rbdstat; /* RxBD status */
589 ushort fcc_rbdlen; /* RxBD down counter */
590 uint fcc_rdptr; /* RxBD internal data pointer */
591 uint fcc_tstate; /* Upper byte is Func code, must be set */
592 uint fcc_tbase; /* Transmit BD base */
593 ushort fcc_tbdstat; /* TxBD status */
594 ushort fcc_tbdlen; /* TxBD down counter */
595 uint fcc_tdptr; /* TxBD internal data pointer */
596 uint fcc_rbptr; /* Rx BD Internal buf pointer */
597 uint fcc_tbptr; /* Tx BD Internal buf pointer */
598 uint fcc_rcrc; /* Rx temp CRC */
599 uint fcc_res2;
600 uint fcc_tcrc; /* Tx temp CRC */
601} fccp_t;
602
603
604/* Ethernet controller through FCC.
605*/
606typedef struct fcc_enet {
607 fccp_t fen_genfcc;
608 uint fen_statbuf; /* Internal status buffer */
609 uint fen_camptr; /* CAM address */
610 uint fen_cmask; /* Constant mask for CRC */
611 uint fen_cpres; /* Preset CRC */
612 uint fen_crcec; /* CRC Error counter */
613 uint fen_alec; /* alignment error counter */
614 uint fen_disfc; /* discard frame counter */
615 ushort fen_retlim; /* Retry limit */
616 ushort fen_retcnt; /* Retry counter */
617 ushort fen_pper; /* Persistence */
618 ushort fen_boffcnt; /* backoff counter */
619 uint fen_gaddrh; /* Group address filter, high 32-bits */
620 uint fen_gaddrl; /* Group address filter, low 32-bits */
621 ushort fen_tfcstat; /* out of sequence TxBD */
622 ushort fen_tfclen;
623 uint fen_tfcptr;
624 ushort fen_mflr; /* Maximum frame length (1518) */
625 ushort fen_paddrh; /* MAC address */
626 ushort fen_paddrm;
627 ushort fen_paddrl;
628 ushort fen_ibdcount; /* Internal BD counter */
629 ushort fen_ibdstart; /* Internal BD start pointer */
630 ushort fen_ibdend; /* Internal BD end pointer */
631 ushort fen_txlen; /* Internal Tx frame length counter */
632 uint fen_ibdbase[8]; /* Internal use */
633 uint fen_iaddrh; /* Individual address filter */
634 uint fen_iaddrl;
635 ushort fen_minflr; /* Minimum frame length (64) */
636 ushort fen_taddrh; /* Filter transfer MAC address */
637 ushort fen_taddrm;
638 ushort fen_taddrl;
639 ushort fen_padptr; /* Pointer to pad byte buffer */
640 ushort fen_cftype; /* control frame type */
641 ushort fen_cfrange; /* control frame range */
642 ushort fen_maxb; /* maximum BD count */
643 ushort fen_maxd1; /* Max DMA1 length (1520) */
644 ushort fen_maxd2; /* Max DMA2 length (1520) */
645 ushort fen_maxd; /* internal max DMA count */
646 ushort fen_dmacnt; /* internal DMA counter */
647 uint fen_octc; /* Total octect counter */
648 uint fen_colc; /* Total collision counter */
649 uint fen_broc; /* Total broadcast packet counter */
650 uint fen_mulc; /* Total multicast packet count */
651 uint fen_uspc; /* Total packets < 64 bytes */
652 uint fen_frgc; /* Total packets < 64 bytes with errors */
653 uint fen_ospc; /* Total packets > 1518 */
654 uint fen_jbrc; /* Total packets > 1518 with errors */
655 uint fen_p64c; /* Total packets == 64 bytes */
656 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
657 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
658 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
659 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
660 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
661 uint fen_cambuf; /* Internal CAM buffer poiner */
662 ushort fen_rfthr; /* Received frames threshold */
663 ushort fen_rfcnt; /* Received frames count */
664} fcc_enet_t;
665
666/* FCC Event/Mask register as used by Ethernet.
667*/
668#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
669#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
670#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
671#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
672#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
673#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
674#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
675#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
676
677/* FCC Mode Register (FPSMR) as used by Ethernet.
678*/
679#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
680#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
681#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
682#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
683#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
684#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
685#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
686#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
687#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
688#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
689#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
690#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
691#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
692
693/* IIC parameter RAM.
694*/
695typedef struct iic {
696 ushort iic_rbase; /* Rx Buffer descriptor base address */
697 ushort iic_tbase; /* Tx Buffer descriptor base address */
698 u_char iic_rfcr; /* Rx function code */
699 u_char iic_tfcr; /* Tx function code */
700 ushort iic_mrblr; /* Max receive buffer length */
701 uint iic_rstate; /* Internal */
702 uint iic_rdp; /* Internal */
703 ushort iic_rbptr; /* Internal */
704 ushort iic_rbc; /* Internal */
705 uint iic_rxtmp; /* Internal */
706 uint iic_tstate; /* Internal */
707 uint iic_tdp; /* Internal */
708 ushort iic_tbptr; /* Internal */
709 ushort iic_tbc; /* Internal */
710 uint iic_txtmp; /* Internal */
711} iic_t;
712
713/* SPI parameter RAM.
714*/
715typedef struct spi {
716 ushort spi_rbase; /* Rx Buffer descriptor base address */
717 ushort spi_tbase; /* Tx Buffer descriptor base address */
718 u_char spi_rfcr; /* Rx function code */
719 u_char spi_tfcr; /* Tx function code */
720 ushort spi_mrblr; /* Max receive buffer length */
721 uint spi_rstate; /* Internal */
722 uint spi_rdp; /* Internal */
723 ushort spi_rbptr; /* Internal */
724 ushort spi_rbc; /* Internal */
725 uint spi_rxtmp; /* Internal */
726 uint spi_tstate; /* Internal */
727 uint spi_tdp; /* Internal */
728 ushort spi_tbptr; /* Internal */
729 ushort spi_tbc; /* Internal */
730 uint spi_txtmp; /* Internal */
731 uint spi_res; /* Tx temp. */
732 uint spi_res1[4]; /* SDMA temp. */
733} spi_t;
734
735/* SPI Mode register.
736*/
737#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
738#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
739#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
740#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
741#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
742#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
743#define SPMODE_EN ((ushort)0x0100) /* Enable */
744#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
745#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
746
747#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
748#define SPMODE_PM(x) ((x) &0xF)
749
750#define SPI_EB ((u_char)0x10) /* big endian byte order */
751
752#define BD_IIC_START ((ushort)0x0400)
753
754/* IDMA parameter RAM
755*/
756typedef struct idma {
757 ushort ibase; /* IDMA buffer descriptor table base address */
758 ushort dcm; /* DMA channel mode */
759 ushort ibdptr; /* IDMA current buffer descriptor pointer */
760 ushort dpr_buf; /* IDMA transfer buffer base address */
761 ushort buf_inv; /* internal buffer inventory */
762 ushort ss_max; /* steady-state maximum transfer size */
763 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
764 ushort sts; /* source transfer size */
765 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
766 ushort seob; /* source end of burst */
767 ushort deob; /* destination end of burst */
768 ushort dts; /* destination transfer size */
769 ushort ret_add; /* return address when working in ERM=1 mode */
770 ushort res0; /* reserved */
771 uint bd_cnt; /* internal byte count */
772 uint s_ptr; /* source internal data pointer */
773 uint d_ptr; /* destination internal data pointer */
774 uint istate; /* internal state */
775 u_char res1[20]; /* pad to 64-byte length */
776} idma_t;
777
778/* DMA channel mode bit fields
779*/
780#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
781#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
782#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
783#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
784#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
785#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
786#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
787#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
788#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
789#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
790#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
791#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
792#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
793#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
794#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
795#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
796#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
797#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
798
799/* IDMA Buffer Descriptors
800*/
801typedef struct idma_bd {
802 uint flags;
803 uint len; /* data length */
804 uint src; /* source data buffer pointer */
805 uint dst; /* destination data buffer pointer */
806} idma_bd_t;
807
808/* IDMA buffer descriptor flag bit fields
809*/
810#define IDMA_BD_V ((uint)0x80000000) /* valid */
811#define IDMA_BD_W ((uint)0x20000000) /* wrap */
812#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
813#define IDMA_BD_L ((uint)0x08000000) /* last */
814#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
815#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
816#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
817#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
818#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
819#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
820#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
821#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
822#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
823#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
824#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
825
826/* per-channel IDMA registers
827*/
828typedef struct im_idma {
829 u_char idsr; /* IDMAn event status register */
830 u_char res0[3];
831 u_char idmr; /* IDMAn event mask register */
832 u_char res1[3];
833} im_idma_t;
834
835/* IDMA event register bit fields
836*/
837#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
838#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
839#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
840#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
841
842/* RISC Controller Configuration Register (RCCR) bit fields
843*/
844#define RCCR_TIME ((uint)0x80000000) /* timer enable */
845#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
846#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
847#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
848#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
849#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
850#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
851#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
852#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
853#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
854#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
855#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
856#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
857#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
858#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
859#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
860#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
861#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
862#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
863#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
864#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
865#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
866#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
867#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
868#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
869#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
870#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
871#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
872#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
873#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
874#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
875#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
876#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
877#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
878#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
879#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
880#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
881#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
882
883/*-----------------------------------------------------------------------
884 * CMXFCR - CMX FCC Clock Route Register
885 */
886#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
887#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
888#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
889#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
890#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
891#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
892#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
893#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
894#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
895
896#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
897#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
898#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
899#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
900#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
901#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
902#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
903#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
904
905#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
906#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
907#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
908#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
909#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
910#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
911#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
912#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
913
914#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
915#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
916#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
917#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
918#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
919#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
920#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
921#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
922
923#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
924#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
925#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
926#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
927#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
928#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
929#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
930#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
931
932#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
933#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
934#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
935#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
936#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
937#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
938#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
939#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
940
941#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
942#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
943#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
944#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
945#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
946#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
947#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
948#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
949
950/*-----------------------------------------------------------------------
951 * CMXSCR - CMX SCC Clock Route Register
952 */
953#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
954#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
955#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
956#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
957#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
958#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
959#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
960#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
961#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
962#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
963#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
964#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
965#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
966#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
967#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
968#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
969
970#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
971#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
972#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
973#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
974#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
975#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
976#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
977#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
978
979#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
980#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
981#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
982#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
983#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
984#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
985#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
986#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
987
988#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
989#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
990#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
991#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
992#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
993#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
994#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
995#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
996
997#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
998#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
999#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
1000#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
1001#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
1002#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
1003#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
1004#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
1005
1006#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
1007#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
1008#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
1009#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
1010#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
1011#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
1012#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
1013#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
1014
1015#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
1016#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
1017#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
1018#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
1019#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
1020#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
1021#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
1022#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
1023
1024#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
1025#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
1026#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
1027#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
1028#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
1029#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
1030#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
1031#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
1032
1033#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
1034#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
1035#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
1036#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
1037#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
1038#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
1039#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1040#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1041
1042/*-----------------------------------------------------------------------
1043 * SIUMCR - SIU Module Configuration Register 4-31
1044 */
1045#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1046#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1047#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1048#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1049#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1050#define SIUMCR_DPPC01 0x04000000 /* - " - */
1051#define SIUMCR_DPPC10 0x08000000 /* - " - */
1052#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1053#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1054#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1055#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1056#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1057#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1058#define SIUMCR_LBPC01 0x00400000 /* - " - */
1059#define SIUMCR_LBPC10 0x00800000 /* - " - */
1060#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1061#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1062#define SIUMCR_APPC01 0x00100000 /* - " - */
1063#define SIUMCR_APPC10 0x00200000 /* - " - */
1064#define SIUMCR_APPC11 0x00300000 /* - " - */
1065#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1066#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1067#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1068#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1069#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1070#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1071#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1072#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1073#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1074#define SIUMCR_MMR01 0x00004000 /* - " - */
1075#define SIUMCR_MMR10 0x00008000 /* - " - */
1076#define SIUMCR_MMR11 0x0000c000 /* - " - */
1077#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1078
1079/*-----------------------------------------------------------------------
1080 * SCCR - System Clock Control Register 9-8
1081*/
1082#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1083#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1084#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1085#define SCCR_PCIDF_SHIFT 3
1086
1087
1088#endif /* __CPM2__ */
1089#endif /* __KERNEL__ */
1090
1091