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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
9 */
10#ifndef _ASM_PGTABLE_BITS_H
11#define _ASM_PGTABLE_BITS_H
12
13#include <linux/config.h>
14
15/*
16 * Note that we shift the lower 32bits of each EntryLo[01] entry
17 * 6 bits to the left. That way we can convert the PFN into the
18 * physical address by a single 'and' operation and gain 6 additional
19 * bits for storing information which isn't present in a normal
20 * MIPS page table.
21 *
22 * Similar to the Alpha port, we need to keep track of the ref
23 * and mod bits in software. We have a software "yeah you can read
24 * from this page" bit, and a hardware one which actually lets the
25 * process read from the page. On the same token we have a software
26 * writable bit and the real hardware one which actually lets the
27 * process write to the page, this keeps a mod bit via the hardware
28 * dirty bit.
29 *
30 * Certain revisions of the R4000 and R5000 have a bug where if a
31 * certain sequence occurs in the last 3 instructions of an executable
32 * page, and the following page is not mapped, the cpu can do
33 * unpredictable things. The code (when it is written) to deal with
34 * this problem will be in the update_mmu_cache() code for the r4k.
35 */
36#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
37
38#define _PAGE_PRESENT (1<<6) /* implemented in software */
39#define _PAGE_READ (1<<7) /* implemented in software */
40#define _PAGE_WRITE (1<<8) /* implemented in software */
41#define _PAGE_ACCESSED (1<<9) /* implemented in software */
42#define _PAGE_MODIFIED (1<<10) /* implemented in software */
43#define _PAGE_FILE (1<<10) /* set:pagecache unset:swap */
44
45#define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
46#define _PAGE_GLOBAL (1<<0)
47#define _PAGE_VALID (1<<1)
48#define _PAGE_SILENT_READ (1<<1) /* synonym */
49#define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
50#define _PAGE_SILENT_WRITE (1<<2)
51#define _CACHE_MASK (7<<3)
52
53/* MIPS32 defines only values 2 and 3. The rest are implementation
54 * dependent.
55 */
56#define _CACHE_UNCACHED (2<<3)
57#define _CACHE_CACHABLE_NONCOHERENT (3<<3)
58#define _CACHE_CACHABLE_COW (3<<3) /* Au1x */
59
60#else
61
62#define _PAGE_PRESENT (1<<0) /* implemented in software */
63#define _PAGE_READ (1<<1) /* implemented in software */
64#define _PAGE_WRITE (1<<2) /* implemented in software */
65#define _PAGE_ACCESSED (1<<3) /* implemented in software */
66#define _PAGE_MODIFIED (1<<4) /* implemented in software */
67#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */
68
69#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
70
71#define _PAGE_GLOBAL (1<<8)
72#define _PAGE_VALID (1<<9)
73#define _PAGE_SILENT_READ (1<<9) /* synonym */
74#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */
75#define _PAGE_SILENT_WRITE (1<<10)
76#define _CACHE_UNCACHED (1<<11)
77#define _CACHE_MASK (1<<11)
78#define _CACHE_CACHABLE_NONCOHERENT 0
79
80#else
81#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
82#define _PAGE_GLOBAL (1<<6)
83#define _PAGE_VALID (1<<7)
84#define _PAGE_SILENT_READ (1<<7) /* synonym */
85#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
86#define _PAGE_SILENT_WRITE (1<<8)
87#define _CACHE_MASK (7<<9)
88
89#ifdef CONFIG_CPU_SB1
90
91/* No penalty for being coherent on the SB1, so just
92 use it for "noncoherent" spaces, too. Shouldn't hurt. */
93
94#define _CACHE_UNCACHED (2<<9)
95#define _CACHE_CACHABLE_COW (5<<9)
96#define _CACHE_CACHABLE_NONCOHERENT (5<<9)
97#define _CACHE_UNCACHED_ACCELERATED (7<<9)
98
99#elif defined(CONFIG_CPU_RM9000)
100
101#define _CACHE_WT (0 << 9)
102#define _CACHE_WTWA (1 << 9)
103#define _CACHE_UC_B (2 << 9)
104#define _CACHE_WB (3 << 9)
105#define _CACHE_CWBEA (4 << 9)
106#define _CACHE_CWB (5 << 9)
107#define _CACHE_UCNB (6 << 9)
108#define _CACHE_FPC (7 << 9)
109
110#define _CACHE_UNCACHED _CACHE_UC_B
111#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
112
113#else
114
115#define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */
116#define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */
117#define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */
118#define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */
119#define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */
120#define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */
121#define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */
122#define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */
123
124#endif
125#endif
126#endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
127
128#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
129#define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
130
131#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
132
133#ifdef CONFIG_MIPS_UNCACHED
134#define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
135#elif defined(CONFIG_DMA_NONCOHERENT)
136#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
137#elif defined(CONFIG_CPU_RM9000)
138#define PAGE_CACHABLE_DEFAULT _CACHE_CWB
139#else
140#define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
141#endif
142
143#if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
144#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
145#else
146#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
147#endif
148
149#endif /* _ASM_PGTABLE_BITS_H */