Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1#ifndef _M68K_SYSTEM_H
2#define _M68K_SYSTEM_H
3
4#include <linux/config.h> /* get configuration macros */
5#include <linux/linkage.h>
6#include <linux/kernel.h>
7#include <asm/segment.h>
8#include <asm/entry.h>
9
10#ifdef __KERNEL__
11
12/*
13 * switch_to(n) should switch tasks to task ptr, first checking that
14 * ptr isn't the current task, in which case it does nothing. This
15 * also clears the TS-flag if the task we switched to has used the
16 * math co-processor latest.
17 */
18/*
19 * switch_to() saves the extra registers, that are not saved
20 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
21 * a0-a1. Some of these are used by schedule() and its predecessors
22 * and so we might get see unexpected behaviors when a task returns
23 * with unexpected register values.
24 *
25 * syscall stores these registers itself and none of them are used
26 * by syscall after the function in the syscall has been called.
27 *
28 * Beware that resume now expects *next to be in d1 and the offset of
29 * tss to be in a1. This saves a few instructions as we no longer have
30 * to push them onto the stack and read them back right after.
31 *
32 * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
33 *
34 * Changed 96/09/19 by Andreas Schwab
35 * pass prev in a0, next in a1
36 */
37asmlinkage void resume(void);
38#define switch_to(prev,next,last) do { \
39 register void *_prev __asm__ ("a0") = (prev); \
40 register void *_next __asm__ ("a1") = (next); \
41 register void *_last __asm__ ("d1"); \
42 __asm__ __volatile__("jbsr resume" \
43 : "=a" (_prev), "=a" (_next), "=d" (_last) \
44 : "0" (_prev), "1" (_next) \
45 : "d0", "d2", "d3", "d4", "d5"); \
46 (last) = _last; \
47} while (0)
48
49
50/* interrupt control.. */
51#if 0
52#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory")
53#else
54#include <linux/hardirq.h>
55#define local_irq_enable() ({ \
56 if (MACH_IS_Q40 || !hardirq_count()) \
57 asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory"); \
58})
59#endif
60#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory")
61#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory")
62#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory")
63
64static inline int irqs_disabled(void)
65{
66 unsigned long flags;
67 local_save_flags(flags);
68 return flags & ~ALLOWINT;
69}
70
71/* For spinlocks etc */
72#define local_irq_save(x) ({ local_save_flags(x); local_irq_disable(); })
73
74/*
75 * Force strict CPU ordering.
76 * Not really required on m68k...
77 */
78#define nop() do { asm volatile ("nop"); barrier(); } while (0)
79#define mb() barrier()
80#define rmb() barrier()
81#define wmb() barrier()
82#define read_barrier_depends() do { } while(0)
83#define set_mb(var, value) do { xchg(&var, value); } while (0)
84#define set_wmb(var, value) do { var = value; wmb(); } while (0)
85
86#define smp_mb() barrier()
87#define smp_rmb() barrier()
88#define smp_wmb() barrier()
89#define smp_read_barrier_depends() do { } while(0)
90
91
92#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
93#define tas(ptr) (xchg((ptr),1))
94
95struct __xchg_dummy { unsigned long a[100]; };
96#define __xg(x) ((volatile struct __xchg_dummy *)(x))
97
98#ifndef CONFIG_RMW_INSNS
99static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
100{
101 unsigned long flags, tmp;
102
103 local_irq_save(flags);
104
105 switch (size) {
106 case 1:
107 tmp = *(u8 *)ptr;
108 *(u8 *)ptr = x;
109 x = tmp;
110 break;
111 case 2:
112 tmp = *(u16 *)ptr;
113 *(u16 *)ptr = x;
114 x = tmp;
115 break;
116 case 4:
117 tmp = *(u32 *)ptr;
118 *(u32 *)ptr = x;
119 x = tmp;
120 break;
121 default:
122 BUG();
123 }
124
125 local_irq_restore(flags);
126 return x;
127}
128#else
129static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
130{
131 switch (size) {
132 case 1:
133 __asm__ __volatile__
134 ("moveb %2,%0\n\t"
135 "1:\n\t"
136 "casb %0,%1,%2\n\t"
137 "jne 1b"
138 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
139 break;
140 case 2:
141 __asm__ __volatile__
142 ("movew %2,%0\n\t"
143 "1:\n\t"
144 "casw %0,%1,%2\n\t"
145 "jne 1b"
146 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
147 break;
148 case 4:
149 __asm__ __volatile__
150 ("movel %2,%0\n\t"
151 "1:\n\t"
152 "casl %0,%1,%2\n\t"
153 "jne 1b"
154 : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory");
155 break;
156 }
157 return x;
158}
159#endif
160
161/*
162 * Atomic compare and exchange. Compare OLD with MEM, if identical,
163 * store NEW in MEM. Return the initial value in MEM. Success is
164 * indicated by comparing RETURN with OLD.
165 */
166#ifdef CONFIG_RMW_INSNS
167#define __HAVE_ARCH_CMPXCHG 1
168
169static inline unsigned long __cmpxchg(volatile void *p, unsigned long old,
170 unsigned long new, int size)
171{
172 switch (size) {
173 case 1:
174 __asm__ __volatile__ ("casb %0,%2,%1"
175 : "=d" (old), "=m" (*(char *)p)
176 : "d" (new), "0" (old), "m" (*(char *)p));
177 break;
178 case 2:
179 __asm__ __volatile__ ("casw %0,%2,%1"
180 : "=d" (old), "=m" (*(short *)p)
181 : "d" (new), "0" (old), "m" (*(short *)p));
182 break;
183 case 4:
184 __asm__ __volatile__ ("casl %0,%2,%1"
185 : "=d" (old), "=m" (*(int *)p)
186 : "d" (new), "0" (old), "m" (*(int *)p));
187 break;
188 }
189 return old;
190}
191
192#define cmpxchg(ptr,o,n)\
193 ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
194 (unsigned long)(n),sizeof(*(ptr))))
195#endif
196
197#define arch_align_stack(x) (x)
198
199#endif /* __KERNEL__ */
200
201#endif /* _M68K_SYSTEM_H */