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1/*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
6
7#ifndef __ASM_I386_PROCESSOR_H
8#define __ASM_I386_PROCESSOR_H
9
10#include <asm/vm86.h>
11#include <asm/math_emu.h>
12#include <asm/segment.h>
13#include <asm/page.h>
14#include <asm/types.h>
15#include <asm/sigcontext.h>
16#include <asm/cpufeature.h>
17#include <asm/msr.h>
18#include <asm/system.h>
19#include <linux/cache.h>
20#include <linux/config.h>
21#include <linux/threads.h>
22#include <asm/percpu.h>
23
24/* flag for disabling the tsc */
25extern int tsc_disable;
26
27struct desc_struct {
28 unsigned long a,b;
29};
30
31#define desc_empty(desc) \
32 (!((desc)->a + (desc)->b))
33
34#define desc_equal(desc1, desc2) \
35 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
36/*
37 * Default implementation of macro that returns current
38 * instruction pointer ("program counter").
39 */
40#define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
41
42/*
43 * CPU type and hardware bug flags. Kept separately for each CPU.
44 * Members of this structure are referenced in head.S, so think twice
45 * before touching them. [mj]
46 */
47
48struct cpuinfo_x86 {
49 __u8 x86; /* CPU family */
50 __u8 x86_vendor; /* CPU vendor */
51 __u8 x86_model;
52 __u8 x86_mask;
53 char wp_works_ok; /* It doesn't on 386's */
54 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
55 char hard_math;
56 char rfu;
57 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
58 unsigned long x86_capability[NCAPINTS];
59 char x86_vendor_id[16];
60 char x86_model_id[64];
61 int x86_cache_size; /* in KB - valid for CPUS which support this
62 call */
63 int x86_cache_alignment; /* In bytes */
64 int fdiv_bug;
65 int f00f_bug;
66 int coma_bug;
67 unsigned long loops_per_jiffy;
68 unsigned char x86_num_cores;
69} __attribute__((__aligned__(SMP_CACHE_BYTES)));
70
71#define X86_VENDOR_INTEL 0
72#define X86_VENDOR_CYRIX 1
73#define X86_VENDOR_AMD 2
74#define X86_VENDOR_UMC 3
75#define X86_VENDOR_NEXGEN 4
76#define X86_VENDOR_CENTAUR 5
77#define X86_VENDOR_RISE 6
78#define X86_VENDOR_TRANSMETA 7
79#define X86_VENDOR_NSC 8
80#define X86_VENDOR_NUM 9
81#define X86_VENDOR_UNKNOWN 0xff
82
83/*
84 * capabilities of CPUs
85 */
86
87extern struct cpuinfo_x86 boot_cpu_data;
88extern struct cpuinfo_x86 new_cpu_data;
89extern struct tss_struct doublefault_tss;
90DECLARE_PER_CPU(struct tss_struct, init_tss);
91
92#ifdef CONFIG_SMP
93extern struct cpuinfo_x86 cpu_data[];
94#define current_cpu_data cpu_data[smp_processor_id()]
95#else
96#define cpu_data (&boot_cpu_data)
97#define current_cpu_data boot_cpu_data
98#endif
99
100extern int phys_proc_id[NR_CPUS];
101extern int cpu_core_id[NR_CPUS];
102extern char ignore_fpu_irq;
103
104extern void identify_cpu(struct cpuinfo_x86 *);
105extern void print_cpu_info(struct cpuinfo_x86 *);
106extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
107
108#ifdef CONFIG_X86_HT
109extern void detect_ht(struct cpuinfo_x86 *c);
110#else
111static inline void detect_ht(struct cpuinfo_x86 *c) {}
112#endif
113
114/*
115 * EFLAGS bits
116 */
117#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
118#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
119#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
120#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
121#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
122#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
123#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
124#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
125#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
126#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
127#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
128#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
129#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
130#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
131#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
132#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
133#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
134
135/*
136 * Generic CPUID function
137 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
138 * resulting in stale register contents being returned.
139 */
140static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
141{
142 __asm__("cpuid"
143 : "=a" (*eax),
144 "=b" (*ebx),
145 "=c" (*ecx),
146 "=d" (*edx)
147 : "0" (op), "c"(0));
148}
149
150/* Some CPUID calls want 'count' to be placed in ecx */
151static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
152 int *edx)
153{
154 __asm__("cpuid"
155 : "=a" (*eax),
156 "=b" (*ebx),
157 "=c" (*ecx),
158 "=d" (*edx)
159 : "0" (op), "c" (count));
160}
161
162/*
163 * CPUID functions returning a single datum
164 */
165static inline unsigned int cpuid_eax(unsigned int op)
166{
167 unsigned int eax;
168
169 __asm__("cpuid"
170 : "=a" (eax)
171 : "0" (op)
172 : "bx", "cx", "dx");
173 return eax;
174}
175static inline unsigned int cpuid_ebx(unsigned int op)
176{
177 unsigned int eax, ebx;
178
179 __asm__("cpuid"
180 : "=a" (eax), "=b" (ebx)
181 : "0" (op)
182 : "cx", "dx" );
183 return ebx;
184}
185static inline unsigned int cpuid_ecx(unsigned int op)
186{
187 unsigned int eax, ecx;
188
189 __asm__("cpuid"
190 : "=a" (eax), "=c" (ecx)
191 : "0" (op)
192 : "bx", "dx" );
193 return ecx;
194}
195static inline unsigned int cpuid_edx(unsigned int op)
196{
197 unsigned int eax, edx;
198
199 __asm__("cpuid"
200 : "=a" (eax), "=d" (edx)
201 : "0" (op)
202 : "bx", "cx");
203 return edx;
204}
205
206#define load_cr3(pgdir) \
207 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)))
208
209
210/*
211 * Intel CPU features in CR4
212 */
213#define X86_CR4_VME 0x0001 /* enable vm86 extensions */
214#define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
215#define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
216#define X86_CR4_DE 0x0008 /* enable debugging extensions */
217#define X86_CR4_PSE 0x0010 /* enable page size extensions */
218#define X86_CR4_PAE 0x0020 /* enable physical address extensions */
219#define X86_CR4_MCE 0x0040 /* Machine check enable */
220#define X86_CR4_PGE 0x0080 /* enable global pages */
221#define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
222#define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
223#define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
224
225/*
226 * Save the cr4 feature set we're using (ie
227 * Pentium 4MB enable and PPro Global page
228 * enable), so that any CPU's that boot up
229 * after us can get the correct flags.
230 */
231extern unsigned long mmu_cr4_features;
232
233static inline void set_in_cr4 (unsigned long mask)
234{
235 mmu_cr4_features |= mask;
236 __asm__("movl %%cr4,%%eax\n\t"
237 "orl %0,%%eax\n\t"
238 "movl %%eax,%%cr4\n"
239 : : "irg" (mask)
240 :"ax");
241}
242
243static inline void clear_in_cr4 (unsigned long mask)
244{
245 mmu_cr4_features &= ~mask;
246 __asm__("movl %%cr4,%%eax\n\t"
247 "andl %0,%%eax\n\t"
248 "movl %%eax,%%cr4\n"
249 : : "irg" (~mask)
250 :"ax");
251}
252
253/*
254 * NSC/Cyrix CPU configuration register indexes
255 */
256
257#define CX86_PCR0 0x20
258#define CX86_GCR 0xb8
259#define CX86_CCR0 0xc0
260#define CX86_CCR1 0xc1
261#define CX86_CCR2 0xc2
262#define CX86_CCR3 0xc3
263#define CX86_CCR4 0xe8
264#define CX86_CCR5 0xe9
265#define CX86_CCR6 0xea
266#define CX86_CCR7 0xeb
267#define CX86_PCR1 0xf0
268#define CX86_DIR0 0xfe
269#define CX86_DIR1 0xff
270#define CX86_ARR_BASE 0xc4
271#define CX86_RCR_BASE 0xdc
272
273/*
274 * NSC/Cyrix CPU indexed register access macros
275 */
276
277#define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
278
279#define setCx86(reg, data) do { \
280 outb((reg), 0x22); \
281 outb((data), 0x23); \
282} while (0)
283
284static inline void __monitor(const void *eax, unsigned long ecx,
285 unsigned long edx)
286{
287 /* "monitor %eax,%ecx,%edx;" */
288 asm volatile(
289 ".byte 0x0f,0x01,0xc8;"
290 : :"a" (eax), "c" (ecx), "d"(edx));
291}
292
293static inline void __mwait(unsigned long eax, unsigned long ecx)
294{
295 /* "mwait %eax,%ecx;" */
296 asm volatile(
297 ".byte 0x0f,0x01,0xc9;"
298 : :"a" (eax), "c" (ecx));
299}
300
301/* from system description table in BIOS. Mostly for MCA use, but
302others may find it useful. */
303extern unsigned int machine_id;
304extern unsigned int machine_submodel_id;
305extern unsigned int BIOS_revision;
306extern unsigned int mca_pentium_flag;
307
308/* Boot loader type from the setup header */
309extern int bootloader_type;
310
311/*
312 * User space process size: 3GB (default).
313 */
314#define TASK_SIZE (PAGE_OFFSET)
315
316/* This decides where the kernel will search for a free chunk of vm
317 * space during mmap's.
318 */
319#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
320
321#define HAVE_ARCH_PICK_MMAP_LAYOUT
322
323/*
324 * Size of io_bitmap.
325 */
326#define IO_BITMAP_BITS 65536
327#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
328#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
329#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
330#define INVALID_IO_BITMAP_OFFSET 0x8000
331#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
332
333struct i387_fsave_struct {
334 long cwd;
335 long swd;
336 long twd;
337 long fip;
338 long fcs;
339 long foo;
340 long fos;
341 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
342 long status; /* software status information */
343};
344
345struct i387_fxsave_struct {
346 unsigned short cwd;
347 unsigned short swd;
348 unsigned short twd;
349 unsigned short fop;
350 long fip;
351 long fcs;
352 long foo;
353 long fos;
354 long mxcsr;
355 long mxcsr_mask;
356 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
357 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
358 long padding[56];
359} __attribute__ ((aligned (16)));
360
361struct i387_soft_struct {
362 long cwd;
363 long swd;
364 long twd;
365 long fip;
366 long fcs;
367 long foo;
368 long fos;
369 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
370 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
371 struct info *info;
372 unsigned long entry_eip;
373};
374
375union i387_union {
376 struct i387_fsave_struct fsave;
377 struct i387_fxsave_struct fxsave;
378 struct i387_soft_struct soft;
379};
380
381typedef struct {
382 unsigned long seg;
383} mm_segment_t;
384
385struct thread_struct;
386
387struct tss_struct {
388 unsigned short back_link,__blh;
389 unsigned long esp0;
390 unsigned short ss0,__ss0h;
391 unsigned long esp1;
392 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
393 unsigned long esp2;
394 unsigned short ss2,__ss2h;
395 unsigned long __cr3;
396 unsigned long eip;
397 unsigned long eflags;
398 unsigned long eax,ecx,edx,ebx;
399 unsigned long esp;
400 unsigned long ebp;
401 unsigned long esi;
402 unsigned long edi;
403 unsigned short es, __esh;
404 unsigned short cs, __csh;
405 unsigned short ss, __ssh;
406 unsigned short ds, __dsh;
407 unsigned short fs, __fsh;
408 unsigned short gs, __gsh;
409 unsigned short ldt, __ldth;
410 unsigned short trace, io_bitmap_base;
411 /*
412 * The extra 1 is there because the CPU will access an
413 * additional byte beyond the end of the IO permission
414 * bitmap. The extra byte must be all 1 bits, and must
415 * be within the limit.
416 */
417 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
418 /*
419 * Cache the current maximum and the last task that used the bitmap:
420 */
421 unsigned long io_bitmap_max;
422 struct thread_struct *io_bitmap_owner;
423 /*
424 * pads the TSS to be cacheline-aligned (size is 0x100)
425 */
426 unsigned long __cacheline_filler[35];
427 /*
428 * .. and then another 0x100 bytes for emergency kernel stack
429 */
430 unsigned long stack[64];
431} __attribute__((packed));
432
433#define ARCH_MIN_TASKALIGN 16
434
435struct thread_struct {
436/* cached TLS descriptors. */
437 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
438 unsigned long esp0;
439 unsigned long sysenter_cs;
440 unsigned long eip;
441 unsigned long esp;
442 unsigned long fs;
443 unsigned long gs;
444/* Hardware debugging registers */
445 unsigned long debugreg[8]; /* %%db0-7 debug registers */
446/* fault info */
447 unsigned long cr2, trap_no, error_code;
448/* floating point info */
449 union i387_union i387;
450/* virtual 86 mode info */
451 struct vm86_struct __user * vm86_info;
452 unsigned long screen_bitmap;
453 unsigned long v86flags, v86mask, saved_esp0;
454 unsigned int saved_fs, saved_gs;
455/* IO permissions */
456 unsigned long *io_bitmap_ptr;
457/* max allowed port in the bitmap, in bytes: */
458 unsigned long io_bitmap_max;
459};
460
461#define INIT_THREAD { \
462 .vm86_info = NULL, \
463 .sysenter_cs = __KERNEL_CS, \
464 .io_bitmap_ptr = NULL, \
465}
466
467/*
468 * Note that the .io_bitmap member must be extra-big. This is because
469 * the CPU will access an additional byte beyond the end of the IO
470 * permission bitmap. The extra byte must be all 1 bits, and must
471 * be within the limit.
472 */
473#define INIT_TSS { \
474 .esp0 = sizeof(init_stack) + (long)&init_stack, \
475 .ss0 = __KERNEL_DS, \
476 .ss1 = __KERNEL_CS, \
477 .ldt = GDT_ENTRY_LDT, \
478 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
479 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
480}
481
482static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
483{
484 tss->esp0 = thread->esp0;
485 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
486 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
487 tss->ss1 = thread->sysenter_cs;
488 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
489 }
490}
491
492#define start_thread(regs, new_eip, new_esp) do { \
493 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
494 set_fs(USER_DS); \
495 regs->xds = __USER_DS; \
496 regs->xes = __USER_DS; \
497 regs->xss = __USER_DS; \
498 regs->xcs = __USER_CS; \
499 regs->eip = new_eip; \
500 regs->esp = new_esp; \
501} while (0)
502
503/*
504 * This special macro can be used to load a debugging register
505 */
506#define loaddebug(thread,register) \
507 __asm__("movl %0,%%db" #register \
508 : /* no output */ \
509 :"r" ((thread)->debugreg[register]))
510
511/* Forward declaration, a strange C thing */
512struct task_struct;
513struct mm_struct;
514
515/* Free all resources held by a thread. */
516extern void release_thread(struct task_struct *);
517
518/* Prepare to copy thread state - unlazy all lazy status */
519extern void prepare_to_copy(struct task_struct *tsk);
520
521/*
522 * create a kernel thread without removing it from tasklists
523 */
524extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
525
526extern unsigned long thread_saved_pc(struct task_struct *tsk);
527void show_trace(struct task_struct *task, unsigned long *stack);
528
529unsigned long get_wchan(struct task_struct *p);
530
531#define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
532#define KSTK_TOP(info) \
533({ \
534 unsigned long *__ptr = (unsigned long *)(info); \
535 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
536})
537
538#define task_pt_regs(task) \
539({ \
540 struct pt_regs *__regs__; \
541 __regs__ = (struct pt_regs *)KSTK_TOP((task)->thread_info); \
542 __regs__ - 1; \
543})
544
545#define KSTK_EIP(task) (task_pt_regs(task)->eip)
546#define KSTK_ESP(task) (task_pt_regs(task)->esp)
547
548
549struct microcode_header {
550 unsigned int hdrver;
551 unsigned int rev;
552 unsigned int date;
553 unsigned int sig;
554 unsigned int cksum;
555 unsigned int ldrver;
556 unsigned int pf;
557 unsigned int datasize;
558 unsigned int totalsize;
559 unsigned int reserved[3];
560};
561
562struct microcode {
563 struct microcode_header hdr;
564 unsigned int bits[0];
565};
566
567typedef struct microcode microcode_t;
568typedef struct microcode_header microcode_header_t;
569
570/* microcode format is extended from prescott processors */
571struct extended_signature {
572 unsigned int sig;
573 unsigned int pf;
574 unsigned int cksum;
575};
576
577struct extended_sigtable {
578 unsigned int count;
579 unsigned int cksum;
580 unsigned int reserved[3];
581 struct extended_signature sigs[0];
582};
583/* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
584#define MICROCODE_IOCFREE _IO('6',0)
585
586/* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
587static inline void rep_nop(void)
588{
589 __asm__ __volatile__("rep;nop": : :"memory");
590}
591
592#define cpu_relax() rep_nop()
593
594/* generic versions from gas */
595#define GENERIC_NOP1 ".byte 0x90\n"
596#define GENERIC_NOP2 ".byte 0x89,0xf6\n"
597#define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
598#define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
599#define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
600#define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
601#define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
602#define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
603
604/* Opteron nops */
605#define K8_NOP1 GENERIC_NOP1
606#define K8_NOP2 ".byte 0x66,0x90\n"
607#define K8_NOP3 ".byte 0x66,0x66,0x90\n"
608#define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
609#define K8_NOP5 K8_NOP3 K8_NOP2
610#define K8_NOP6 K8_NOP3 K8_NOP3
611#define K8_NOP7 K8_NOP4 K8_NOP3
612#define K8_NOP8 K8_NOP4 K8_NOP4
613
614/* K7 nops */
615/* uses eax dependencies (arbitary choice) */
616#define K7_NOP1 GENERIC_NOP1
617#define K7_NOP2 ".byte 0x8b,0xc0\n"
618#define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
619#define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
620#define K7_NOP5 K7_NOP4 ASM_NOP1
621#define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
622#define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
623#define K7_NOP8 K7_NOP7 ASM_NOP1
624
625#ifdef CONFIG_MK8
626#define ASM_NOP1 K8_NOP1
627#define ASM_NOP2 K8_NOP2
628#define ASM_NOP3 K8_NOP3
629#define ASM_NOP4 K8_NOP4
630#define ASM_NOP5 K8_NOP5
631#define ASM_NOP6 K8_NOP6
632#define ASM_NOP7 K8_NOP7
633#define ASM_NOP8 K8_NOP8
634#elif defined(CONFIG_MK7)
635#define ASM_NOP1 K7_NOP1
636#define ASM_NOP2 K7_NOP2
637#define ASM_NOP3 K7_NOP3
638#define ASM_NOP4 K7_NOP4
639#define ASM_NOP5 K7_NOP5
640#define ASM_NOP6 K7_NOP6
641#define ASM_NOP7 K7_NOP7
642#define ASM_NOP8 K7_NOP8
643#else
644#define ASM_NOP1 GENERIC_NOP1
645#define ASM_NOP2 GENERIC_NOP2
646#define ASM_NOP3 GENERIC_NOP3
647#define ASM_NOP4 GENERIC_NOP4
648#define ASM_NOP5 GENERIC_NOP5
649#define ASM_NOP6 GENERIC_NOP6
650#define ASM_NOP7 GENERIC_NOP7
651#define ASM_NOP8 GENERIC_NOP8
652#endif
653
654#define ASM_NOP_MAX 8
655
656/* Prefetch instructions for Pentium III and AMD Athlon */
657/* It's not worth to care about 3dnow! prefetches for the K6
658 because they are microcoded there and very slow.
659 However we don't do prefetches for pre XP Athlons currently
660 That should be fixed. */
661#define ARCH_HAS_PREFETCH
662extern inline void prefetch(const void *x)
663{
664 alternative_input(ASM_NOP4,
665 "prefetchnta (%1)",
666 X86_FEATURE_XMM,
667 "r" (x));
668}
669
670#define ARCH_HAS_PREFETCH
671#define ARCH_HAS_PREFETCHW
672#define ARCH_HAS_SPINLOCK_PREFETCH
673
674/* 3dnow! prefetch to get an exclusive cache line. Useful for
675 spinlocks to avoid one state transition in the cache coherency protocol. */
676extern inline void prefetchw(const void *x)
677{
678 alternative_input(ASM_NOP4,
679 "prefetchw (%1)",
680 X86_FEATURE_3DNOW,
681 "r" (x));
682}
683#define spin_lock_prefetch(x) prefetchw(x)
684
685extern void select_idle_routine(const struct cpuinfo_x86 *c);
686
687#define cache_line_size() (boot_cpu_data.x86_cache_alignment)
688
689extern unsigned long boot_option_idle_override;
690
691#endif /* __ASM_I386_PROCESSOR_H */