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1/* 2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware 3 * 4 * Copyright 2004 Red Hat, Inc. 5 * 6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com> 7 * 8 * This file is subject to the terms and conditions of the GNU General Public 9 * License. See the file "COPYING" in the main directory of this archive 10 * for more details. 11 */ 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/init.h> 16#include <linux/pci.h> 17#include <linux/slab.h> 18#include <linux/spinlock.h> 19#include <linux/blkdev.h> 20#include <linux/sched.h> 21#include <linux/devfs_fs_kernel.h> 22#include <linux/interrupt.h> 23#include <linux/compiler.h> 24#include <linux/workqueue.h> 25#include <linux/bitops.h> 26#include <linux/delay.h> 27#include <linux/time.h> 28#include <linux/hdreg.h> 29#include <asm/io.h> 30#include <asm/semaphore.h> 31#include <asm/uaccess.h> 32 33MODULE_AUTHOR("Jeff Garzik"); 34MODULE_LICENSE("GPL"); 35MODULE_DESCRIPTION("Promise SATA SX8 block driver"); 36 37#if 0 38#define CARM_DEBUG 39#define CARM_VERBOSE_DEBUG 40#else 41#undef CARM_DEBUG 42#undef CARM_VERBOSE_DEBUG 43#endif 44#undef CARM_NDEBUG 45 46#define DRV_NAME "sx8" 47#define DRV_VERSION "0.8" 48#define PFX DRV_NAME ": " 49 50#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) 51 52/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ 53#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) 54#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) 55#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) 56 57/* note: prints function name for you */ 58#ifdef CARM_DEBUG 59#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 60#ifdef CARM_VERBOSE_DEBUG 61#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args) 62#else 63#define VPRINTK(fmt, args...) 64#endif /* CARM_VERBOSE_DEBUG */ 65#else 66#define DPRINTK(fmt, args...) 67#define VPRINTK(fmt, args...) 68#endif /* CARM_DEBUG */ 69 70#ifdef CARM_NDEBUG 71#define assert(expr) 72#else 73#define assert(expr) \ 74 if(unlikely(!(expr))) { \ 75 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ 76 #expr,__FILE__,__FUNCTION__,__LINE__); \ 77 } 78#endif 79 80/* defines only for the constants which don't work well as enums */ 81struct carm_host; 82 83enum { 84 /* adapter-wide limits */ 85 CARM_MAX_PORTS = 8, 86 CARM_SHM_SIZE = (4096 << 7), 87 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, 88 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, 89 90 /* command message queue limits */ 91 CARM_MAX_REQ = 64, /* max command msgs per host */ 92 CARM_MAX_Q = 1, /* one command at a time */ 93 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ 94 95 /* S/G limits, host-wide and per-request */ 96 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ 97 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ 98 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ 99 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ 100 101 /* hardware registers */ 102 CARM_IHQP = 0x1c, 103 CARM_INT_STAT = 0x10, /* interrupt status */ 104 CARM_INT_MASK = 0x14, /* interrupt mask */ 105 CARM_HMUC = 0x18, /* host message unit control */ 106 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ 107 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ 108 RBUF_BYTE_SZ = 0x28, 109 CARM_RESP_IDX = 0x2c, 110 CARM_CMS0 = 0x30, /* command message size reg 0 */ 111 CARM_LMUC = 0x48, 112 CARM_HMPHA = 0x6c, 113 CARM_INITC = 0xb5, 114 115 /* bits in CARM_INT_{STAT,MASK} */ 116 INT_RESERVED = 0xfffffff0, 117 INT_WATCHDOG = (1 << 3), /* watchdog timer */ 118 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ 119 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ 120 INT_RESPONSE = (1 << 0), /* response msg available */ 121 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, 122 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | 123 INT_RESPONSE, 124 125 /* command messages, and related register bits */ 126 CARM_HAVE_RESP = 0x01, 127 CARM_MSG_READ = 1, 128 CARM_MSG_WRITE = 2, 129 CARM_MSG_VERIFY = 3, 130 CARM_MSG_GET_CAPACITY = 4, 131 CARM_MSG_FLUSH = 5, 132 CARM_MSG_IOCTL = 6, 133 CARM_MSG_ARRAY = 8, 134 CARM_MSG_MISC = 9, 135 CARM_CME = (1 << 2), 136 CARM_RME = (1 << 1), 137 CARM_WZBC = (1 << 0), 138 CARM_RMI = (1 << 0), 139 CARM_Q_FULL = (1 << 3), 140 CARM_MSG_SIZE = 288, 141 CARM_Q_LEN = 48, 142 143 /* CARM_MSG_IOCTL messages */ 144 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ 145 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ 146 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ 147 148 IOC_SCAN_CHAN_NODEV = 0x1f, 149 IOC_SCAN_CHAN_OFFSET = 0x40, 150 151 /* CARM_MSG_ARRAY messages */ 152 CARM_ARRAY_INFO = 0, 153 154 ARRAY_NO_EXIST = (1 << 31), 155 156 /* response messages */ 157 RMSG_SZ = 8, /* sizeof(struct carm_response) */ 158 RMSG_Q_LEN = 48, /* resp. msg list length */ 159 RMSG_OK = 1, /* bit indicating msg was successful */ 160 /* length of entire resp. msg buffer */ 161 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, 162 163 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ 164 165 /* CARM_MSG_MISC messages */ 166 MISC_GET_FW_VER = 2, 167 MISC_ALLOC_MEM = 3, 168 MISC_SET_TIME = 5, 169 170 /* MISC_GET_FW_VER feature bits */ 171 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ 172 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ 173 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ 174 175 /* carm_host flags */ 176 FL_NON_RAID = FW_VER_NON_RAID, 177 FL_4PORT = FW_VER_4PORT, 178 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), 179 FL_DAC = (1 << 16), 180 FL_DYN_MAJOR = (1 << 17), 181}; 182 183enum scatter_gather_types { 184 SGT_32BIT = 0, 185 SGT_64BIT = 1, 186}; 187 188enum host_states { 189 HST_INVALID, /* invalid state; never used */ 190 HST_ALLOC_BUF, /* setting up master SHM area */ 191 HST_ERROR, /* we never leave here */ 192 HST_PORT_SCAN, /* start dev scan */ 193 HST_DEV_SCAN_START, /* start per-device probe */ 194 HST_DEV_SCAN, /* continue per-device probe */ 195 HST_DEV_ACTIVATE, /* activate devices we found */ 196 HST_PROBE_FINISHED, /* probe is complete */ 197 HST_PROBE_START, /* initiate probe */ 198 HST_SYNC_TIME, /* tell firmware what time it is */ 199 HST_GET_FW_VER, /* get firmware version, adapter port cnt */ 200}; 201 202#ifdef CARM_DEBUG 203static const char *state_name[] = { 204 "HST_INVALID", 205 "HST_ALLOC_BUF", 206 "HST_ERROR", 207 "HST_PORT_SCAN", 208 "HST_DEV_SCAN_START", 209 "HST_DEV_SCAN", 210 "HST_DEV_ACTIVATE", 211 "HST_PROBE_FINISHED", 212 "HST_PROBE_START", 213 "HST_SYNC_TIME", 214 "HST_GET_FW_VER", 215}; 216#endif 217 218struct carm_port { 219 unsigned int port_no; 220 unsigned int n_queued; 221 struct gendisk *disk; 222 struct carm_host *host; 223 224 /* attached device characteristics */ 225 u64 capacity; 226 char name[41]; 227 u16 dev_geom_head; 228 u16 dev_geom_sect; 229 u16 dev_geom_cyl; 230}; 231 232struct carm_request { 233 unsigned int tag; 234 int n_elem; 235 unsigned int msg_type; 236 unsigned int msg_subtype; 237 unsigned int msg_bucket; 238 struct request *rq; 239 struct carm_port *port; 240 struct scatterlist sg[CARM_MAX_REQ_SG]; 241}; 242 243struct carm_host { 244 unsigned long flags; 245 void __iomem *mmio; 246 void *shm; 247 dma_addr_t shm_dma; 248 249 int major; 250 int id; 251 char name[32]; 252 253 spinlock_t lock; 254 struct pci_dev *pdev; 255 unsigned int state; 256 u32 fw_ver; 257 258 request_queue_t *oob_q; 259 unsigned int n_oob; 260 261 unsigned int hw_sg_used; 262 263 unsigned int resp_idx; 264 265 unsigned int wait_q_prod; 266 unsigned int wait_q_cons; 267 request_queue_t *wait_q[CARM_MAX_WAIT_Q]; 268 269 unsigned int n_msgs; 270 u64 msg_alloc; 271 struct carm_request req[CARM_MAX_REQ]; 272 void *msg_base; 273 dma_addr_t msg_dma; 274 275 int cur_scan_dev; 276 unsigned long dev_active; 277 unsigned long dev_present; 278 struct carm_port port[CARM_MAX_PORTS]; 279 280 struct work_struct fsm_task; 281 282 struct semaphore probe_sem; 283}; 284 285struct carm_response { 286 __le32 ret_handle; 287 __le32 status; 288} __attribute__((packed)); 289 290struct carm_msg_sg { 291 __le32 start; 292 __le32 len; 293} __attribute__((packed)); 294 295struct carm_msg_rw { 296 u8 type; 297 u8 id; 298 u8 sg_count; 299 u8 sg_type; 300 __le32 handle; 301 __le32 lba; 302 __le16 lba_count; 303 __le16 lba_high; 304 struct carm_msg_sg sg[32]; 305} __attribute__((packed)); 306 307struct carm_msg_allocbuf { 308 u8 type; 309 u8 subtype; 310 u8 n_sg; 311 u8 sg_type; 312 __le32 handle; 313 __le32 addr; 314 __le32 len; 315 __le32 evt_pool; 316 __le32 n_evt; 317 __le32 rbuf_pool; 318 __le32 n_rbuf; 319 __le32 msg_pool; 320 __le32 n_msg; 321 struct carm_msg_sg sg[8]; 322} __attribute__((packed)); 323 324struct carm_msg_ioctl { 325 u8 type; 326 u8 subtype; 327 u8 array_id; 328 u8 reserved1; 329 __le32 handle; 330 __le32 data_addr; 331 u32 reserved2; 332} __attribute__((packed)); 333 334struct carm_msg_sync_time { 335 u8 type; 336 u8 subtype; 337 u16 reserved1; 338 __le32 handle; 339 u32 reserved2; 340 __le32 timestamp; 341} __attribute__((packed)); 342 343struct carm_msg_get_fw_ver { 344 u8 type; 345 u8 subtype; 346 u16 reserved1; 347 __le32 handle; 348 __le32 data_addr; 349 u32 reserved2; 350} __attribute__((packed)); 351 352struct carm_fw_ver { 353 __le32 version; 354 u8 features; 355 u8 reserved1; 356 u16 reserved2; 357} __attribute__((packed)); 358 359struct carm_array_info { 360 __le32 size; 361 362 __le16 size_hi; 363 __le16 stripe_size; 364 365 __le32 mode; 366 367 __le16 stripe_blk_sz; 368 __le16 reserved1; 369 370 __le16 cyl; 371 __le16 head; 372 373 __le16 sect; 374 u8 array_id; 375 u8 reserved2; 376 377 char name[40]; 378 379 __le32 array_status; 380 381 /* device list continues beyond this point? */ 382} __attribute__((packed)); 383 384static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); 385static void carm_remove_one (struct pci_dev *pdev); 386static int carm_bdev_ioctl(struct inode *ino, struct file *fil, 387 unsigned int cmd, unsigned long arg); 388 389static struct pci_device_id carm_pci_tbl[] = { 390 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 391 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 392 { } /* terminate list */ 393}; 394MODULE_DEVICE_TABLE(pci, carm_pci_tbl); 395 396static struct pci_driver carm_driver = { 397 .name = DRV_NAME, 398 .id_table = carm_pci_tbl, 399 .probe = carm_init_one, 400 .remove = carm_remove_one, 401}; 402 403static struct block_device_operations carm_bd_ops = { 404 .owner = THIS_MODULE, 405 .ioctl = carm_bdev_ioctl, 406}; 407 408static unsigned int carm_host_id; 409static unsigned long carm_major_alloc; 410 411 412 413static int carm_bdev_ioctl(struct inode *ino, struct file *fil, 414 unsigned int cmd, unsigned long arg) 415{ 416 void __user *usermem = (void __user *) arg; 417 struct carm_port *port = ino->i_bdev->bd_disk->private_data; 418 struct hd_geometry geom; 419 420 switch (cmd) { 421 case HDIO_GETGEO: 422 if (!usermem) 423 return -EINVAL; 424 425 geom.heads = (u8) port->dev_geom_head; 426 geom.sectors = (u8) port->dev_geom_sect; 427 geom.cylinders = port->dev_geom_cyl; 428 geom.start = get_start_sect(ino->i_bdev); 429 430 if (copy_to_user(usermem, &geom, sizeof(geom))) 431 return -EFAULT; 432 return 0; 433 434 default: 435 break; 436 } 437 438 return -EOPNOTSUPP; 439} 440 441static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; 442 443static inline int carm_lookup_bucket(u32 msg_size) 444{ 445 int i; 446 447 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 448 if (msg_size <= msg_sizes[i]) 449 return i; 450 451 return -ENOENT; 452} 453 454static void carm_init_buckets(void __iomem *mmio) 455{ 456 unsigned int i; 457 458 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) 459 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); 460} 461 462static inline void *carm_ref_msg(struct carm_host *host, 463 unsigned int msg_idx) 464{ 465 return host->msg_base + (msg_idx * CARM_MSG_SIZE); 466} 467 468static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, 469 unsigned int msg_idx) 470{ 471 return host->msg_dma + (msg_idx * CARM_MSG_SIZE); 472} 473 474static int carm_send_msg(struct carm_host *host, 475 struct carm_request *crq) 476{ 477 void __iomem *mmio = host->mmio; 478 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); 479 u32 cm_bucket = crq->msg_bucket; 480 u32 tmp; 481 int rc = 0; 482 483 VPRINTK("ENTER\n"); 484 485 tmp = readl(mmio + CARM_HMUC); 486 if (tmp & CARM_Q_FULL) { 487#if 0 488 tmp = readl(mmio + CARM_INT_MASK); 489 tmp |= INT_Q_AVAILABLE; 490 writel(tmp, mmio + CARM_INT_MASK); 491 readl(mmio + CARM_INT_MASK); /* flush */ 492#endif 493 DPRINTK("host msg queue full\n"); 494 rc = -EBUSY; 495 } else { 496 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); 497 readl(mmio + CARM_IHQP); /* flush */ 498 } 499 500 return rc; 501} 502 503static struct carm_request *carm_get_request(struct carm_host *host) 504{ 505 unsigned int i; 506 507 /* obey global hardware limit on S/G entries */ 508 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) 509 return NULL; 510 511 for (i = 0; i < CARM_MAX_Q; i++) 512 if ((host->msg_alloc & (1ULL << i)) == 0) { 513 struct carm_request *crq = &host->req[i]; 514 crq->port = NULL; 515 crq->n_elem = 0; 516 517 host->msg_alloc |= (1ULL << i); 518 host->n_msgs++; 519 520 assert(host->n_msgs <= CARM_MAX_REQ); 521 return crq; 522 } 523 524 DPRINTK("no request available, returning NULL\n"); 525 return NULL; 526} 527 528static int carm_put_request(struct carm_host *host, struct carm_request *crq) 529{ 530 assert(crq->tag < CARM_MAX_Q); 531 532 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) 533 return -EINVAL; /* tried to clear a tag that was not active */ 534 535 assert(host->hw_sg_used >= crq->n_elem); 536 537 host->msg_alloc &= ~(1ULL << crq->tag); 538 host->hw_sg_used -= crq->n_elem; 539 host->n_msgs--; 540 541 return 0; 542} 543 544static struct carm_request *carm_get_special(struct carm_host *host) 545{ 546 unsigned long flags; 547 struct carm_request *crq = NULL; 548 struct request *rq; 549 int tries = 5000; 550 551 while (tries-- > 0) { 552 spin_lock_irqsave(&host->lock, flags); 553 crq = carm_get_request(host); 554 spin_unlock_irqrestore(&host->lock, flags); 555 556 if (crq) 557 break; 558 msleep(10); 559 } 560 561 if (!crq) 562 return NULL; 563 564 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL); 565 if (!rq) { 566 spin_lock_irqsave(&host->lock, flags); 567 carm_put_request(host, crq); 568 spin_unlock_irqrestore(&host->lock, flags); 569 return NULL; 570 } 571 572 crq->rq = rq; 573 return crq; 574} 575 576static int carm_array_info (struct carm_host *host, unsigned int array_idx) 577{ 578 struct carm_msg_ioctl *ioc; 579 unsigned int idx; 580 u32 msg_data; 581 dma_addr_t msg_dma; 582 struct carm_request *crq; 583 int rc; 584 585 crq = carm_get_special(host); 586 if (!crq) { 587 rc = -ENOMEM; 588 goto err_out; 589 } 590 591 idx = crq->tag; 592 593 ioc = carm_ref_msg(host, idx); 594 msg_dma = carm_ref_msg_dma(host, idx); 595 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); 596 597 crq->msg_type = CARM_MSG_ARRAY; 598 crq->msg_subtype = CARM_ARRAY_INFO; 599 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + 600 sizeof(struct carm_array_info)); 601 BUG_ON(rc < 0); 602 crq->msg_bucket = (u32) rc; 603 604 memset(ioc, 0, sizeof(*ioc)); 605 ioc->type = CARM_MSG_ARRAY; 606 ioc->subtype = CARM_ARRAY_INFO; 607 ioc->array_id = (u8) array_idx; 608 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 609 ioc->data_addr = cpu_to_le32(msg_data); 610 611 spin_lock_irq(&host->lock); 612 assert(host->state == HST_DEV_SCAN_START || 613 host->state == HST_DEV_SCAN); 614 spin_unlock_irq(&host->lock); 615 616 DPRINTK("blk_insert_request, tag == %u\n", idx); 617 blk_insert_request(host->oob_q, crq->rq, 1, crq, 0); 618 619 return 0; 620 621err_out: 622 spin_lock_irq(&host->lock); 623 host->state = HST_ERROR; 624 spin_unlock_irq(&host->lock); 625 return rc; 626} 627 628typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); 629 630static int carm_send_special (struct carm_host *host, carm_sspc_t func) 631{ 632 struct carm_request *crq; 633 struct carm_msg_ioctl *ioc; 634 void *mem; 635 unsigned int idx, msg_size; 636 int rc; 637 638 crq = carm_get_special(host); 639 if (!crq) 640 return -ENOMEM; 641 642 idx = crq->tag; 643 644 mem = carm_ref_msg(host, idx); 645 646 msg_size = func(host, idx, mem); 647 648 ioc = mem; 649 crq->msg_type = ioc->type; 650 crq->msg_subtype = ioc->subtype; 651 rc = carm_lookup_bucket(msg_size); 652 BUG_ON(rc < 0); 653 crq->msg_bucket = (u32) rc; 654 655 DPRINTK("blk_insert_request, tag == %u\n", idx); 656 blk_insert_request(host->oob_q, crq->rq, 1, crq, 0); 657 658 return 0; 659} 660 661static unsigned int carm_fill_sync_time(struct carm_host *host, 662 unsigned int idx, void *mem) 663{ 664 struct timeval tv; 665 struct carm_msg_sync_time *st = mem; 666 667 do_gettimeofday(&tv); 668 669 memset(st, 0, sizeof(*st)); 670 st->type = CARM_MSG_MISC; 671 st->subtype = MISC_SET_TIME; 672 st->handle = cpu_to_le32(TAG_ENCODE(idx)); 673 st->timestamp = cpu_to_le32(tv.tv_sec); 674 675 return sizeof(struct carm_msg_sync_time); 676} 677 678static unsigned int carm_fill_alloc_buf(struct carm_host *host, 679 unsigned int idx, void *mem) 680{ 681 struct carm_msg_allocbuf *ab = mem; 682 683 memset(ab, 0, sizeof(*ab)); 684 ab->type = CARM_MSG_MISC; 685 ab->subtype = MISC_ALLOC_MEM; 686 ab->handle = cpu_to_le32(TAG_ENCODE(idx)); 687 ab->n_sg = 1; 688 ab->sg_type = SGT_32BIT; 689 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 690 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); 691 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); 692 ab->n_evt = cpu_to_le32(1024); 693 ab->rbuf_pool = cpu_to_le32(host->shm_dma); 694 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); 695 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); 696 ab->n_msg = cpu_to_le32(CARM_Q_LEN); 697 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); 698 ab->sg[0].len = cpu_to_le32(65536); 699 700 return sizeof(struct carm_msg_allocbuf); 701} 702 703static unsigned int carm_fill_scan_channels(struct carm_host *host, 704 unsigned int idx, void *mem) 705{ 706 struct carm_msg_ioctl *ioc = mem; 707 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + 708 IOC_SCAN_CHAN_OFFSET); 709 710 memset(ioc, 0, sizeof(*ioc)); 711 ioc->type = CARM_MSG_IOCTL; 712 ioc->subtype = CARM_IOC_SCAN_CHAN; 713 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 714 ioc->data_addr = cpu_to_le32(msg_data); 715 716 /* fill output data area with "no device" default values */ 717 mem += IOC_SCAN_CHAN_OFFSET; 718 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); 719 720 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; 721} 722 723static unsigned int carm_fill_get_fw_ver(struct carm_host *host, 724 unsigned int idx, void *mem) 725{ 726 struct carm_msg_get_fw_ver *ioc = mem; 727 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); 728 729 memset(ioc, 0, sizeof(*ioc)); 730 ioc->type = CARM_MSG_MISC; 731 ioc->subtype = MISC_GET_FW_VER; 732 ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); 733 ioc->data_addr = cpu_to_le32(msg_data); 734 735 return sizeof(struct carm_msg_get_fw_ver) + 736 sizeof(struct carm_fw_ver); 737} 738 739static inline void carm_end_request_queued(struct carm_host *host, 740 struct carm_request *crq, 741 int uptodate) 742{ 743 struct request *req = crq->rq; 744 int rc; 745 746 rc = end_that_request_first(req, uptodate, req->hard_nr_sectors); 747 assert(rc == 0); 748 749 end_that_request_last(req); 750 751 rc = carm_put_request(host, crq); 752 assert(rc == 0); 753} 754 755static inline void carm_push_q (struct carm_host *host, request_queue_t *q) 756{ 757 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; 758 759 blk_stop_queue(q); 760 VPRINTK("STOPPED QUEUE %p\n", q); 761 762 host->wait_q[idx] = q; 763 host->wait_q_prod++; 764 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ 765} 766 767static inline request_queue_t *carm_pop_q(struct carm_host *host) 768{ 769 unsigned int idx; 770 771 if (host->wait_q_prod == host->wait_q_cons) 772 return NULL; 773 774 idx = host->wait_q_cons % CARM_MAX_WAIT_Q; 775 host->wait_q_cons++; 776 777 return host->wait_q[idx]; 778} 779 780static inline void carm_round_robin(struct carm_host *host) 781{ 782 request_queue_t *q = carm_pop_q(host); 783 if (q) { 784 blk_start_queue(q); 785 VPRINTK("STARTED QUEUE %p\n", q); 786 } 787} 788 789static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, 790 int is_ok) 791{ 792 carm_end_request_queued(host, crq, is_ok); 793 if (CARM_MAX_Q == 1) 794 carm_round_robin(host); 795 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && 796 (host->hw_sg_used <= CARM_SG_LOW_WATER)) { 797 carm_round_robin(host); 798 } 799} 800 801static void carm_oob_rq_fn(request_queue_t *q) 802{ 803 struct carm_host *host = q->queuedata; 804 struct carm_request *crq; 805 struct request *rq; 806 int rc; 807 808 while (1) { 809 DPRINTK("get req\n"); 810 rq = elv_next_request(q); 811 if (!rq) 812 break; 813 814 blkdev_dequeue_request(rq); 815 816 crq = rq->special; 817 assert(crq != NULL); 818 assert(crq->rq == rq); 819 820 crq->n_elem = 0; 821 822 DPRINTK("send req\n"); 823 rc = carm_send_msg(host, crq); 824 if (rc) { 825 blk_requeue_request(q, rq); 826 carm_push_q(host, q); 827 return; /* call us again later, eventually */ 828 } 829 } 830} 831 832static void carm_rq_fn(request_queue_t *q) 833{ 834 struct carm_port *port = q->queuedata; 835 struct carm_host *host = port->host; 836 struct carm_msg_rw *msg; 837 struct carm_request *crq; 838 struct request *rq; 839 struct scatterlist *sg; 840 int writing = 0, pci_dir, i, n_elem, rc; 841 u32 tmp; 842 unsigned int msg_size; 843 844queue_one_request: 845 VPRINTK("get req\n"); 846 rq = elv_next_request(q); 847 if (!rq) 848 return; 849 850 crq = carm_get_request(host); 851 if (!crq) { 852 carm_push_q(host, q); 853 return; /* call us again later, eventually */ 854 } 855 crq->rq = rq; 856 857 blkdev_dequeue_request(rq); 858 859 if (rq_data_dir(rq) == WRITE) { 860 writing = 1; 861 pci_dir = PCI_DMA_TODEVICE; 862 } else { 863 pci_dir = PCI_DMA_FROMDEVICE; 864 } 865 866 /* get scatterlist from block layer */ 867 sg = &crq->sg[0]; 868 n_elem = blk_rq_map_sg(q, rq, sg); 869 if (n_elem <= 0) { 870 carm_end_rq(host, crq, 0); 871 return; /* request with no s/g entries? */ 872 } 873 874 /* map scatterlist to PCI bus addresses */ 875 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); 876 if (n_elem <= 0) { 877 carm_end_rq(host, crq, 0); 878 return; /* request with no s/g entries? */ 879 } 880 crq->n_elem = n_elem; 881 crq->port = port; 882 host->hw_sg_used += n_elem; 883 884 /* 885 * build read/write message 886 */ 887 888 VPRINTK("build msg\n"); 889 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); 890 891 if (writing) { 892 msg->type = CARM_MSG_WRITE; 893 crq->msg_type = CARM_MSG_WRITE; 894 } else { 895 msg->type = CARM_MSG_READ; 896 crq->msg_type = CARM_MSG_READ; 897 } 898 899 msg->id = port->port_no; 900 msg->sg_count = n_elem; 901 msg->sg_type = SGT_32BIT; 902 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); 903 msg->lba = cpu_to_le32(rq->sector & 0xffffffff); 904 tmp = (rq->sector >> 16) >> 16; 905 msg->lba_high = cpu_to_le16( (u16) tmp ); 906 msg->lba_count = cpu_to_le16(rq->nr_sectors); 907 908 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); 909 for (i = 0; i < n_elem; i++) { 910 struct carm_msg_sg *carm_sg = &msg->sg[i]; 911 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); 912 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); 913 msg_size += sizeof(struct carm_msg_sg); 914 } 915 916 rc = carm_lookup_bucket(msg_size); 917 BUG_ON(rc < 0); 918 crq->msg_bucket = (u32) rc; 919 920 /* 921 * queue read/write message to hardware 922 */ 923 924 VPRINTK("send msg, tag == %u\n", crq->tag); 925 rc = carm_send_msg(host, crq); 926 if (rc) { 927 carm_put_request(host, crq); 928 blk_requeue_request(q, rq); 929 carm_push_q(host, q); 930 return; /* call us again later, eventually */ 931 } 932 933 goto queue_one_request; 934} 935 936static void carm_handle_array_info(struct carm_host *host, 937 struct carm_request *crq, u8 *mem, 938 int is_ok) 939{ 940 struct carm_port *port; 941 u8 *msg_data = mem + sizeof(struct carm_array_info); 942 struct carm_array_info *desc = (struct carm_array_info *) msg_data; 943 u64 lo, hi; 944 int cur_port; 945 size_t slen; 946 947 DPRINTK("ENTER\n"); 948 949 carm_end_rq(host, crq, is_ok); 950 951 if (!is_ok) 952 goto out; 953 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) 954 goto out; 955 956 cur_port = host->cur_scan_dev; 957 958 /* should never occur */ 959 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { 960 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", 961 cur_port, (int) desc->array_id); 962 goto out; 963 } 964 965 port = &host->port[cur_port]; 966 967 lo = (u64) le32_to_cpu(desc->size); 968 hi = (u64) le16_to_cpu(desc->size_hi); 969 970 port->capacity = lo | (hi << 32); 971 port->dev_geom_head = le16_to_cpu(desc->head); 972 port->dev_geom_sect = le16_to_cpu(desc->sect); 973 port->dev_geom_cyl = le16_to_cpu(desc->cyl); 974 975 host->dev_active |= (1 << cur_port); 976 977 strncpy(port->name, desc->name, sizeof(port->name)); 978 port->name[sizeof(port->name) - 1] = 0; 979 slen = strlen(port->name); 980 while (slen && (port->name[slen - 1] == ' ')) { 981 port->name[slen - 1] = 0; 982 slen--; 983 } 984 985 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", 986 pci_name(host->pdev), port->port_no, 987 (unsigned long long) port->capacity); 988 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", 989 pci_name(host->pdev), port->port_no, port->name); 990 991out: 992 assert(host->state == HST_DEV_SCAN); 993 schedule_work(&host->fsm_task); 994} 995 996static void carm_handle_scan_chan(struct carm_host *host, 997 struct carm_request *crq, u8 *mem, 998 int is_ok) 999{ 1000 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; 1001 unsigned int i, dev_count = 0; 1002 int new_state = HST_DEV_SCAN_START; 1003 1004 DPRINTK("ENTER\n"); 1005 1006 carm_end_rq(host, crq, is_ok); 1007 1008 if (!is_ok) { 1009 new_state = HST_ERROR; 1010 goto out; 1011 } 1012 1013 /* TODO: scan and support non-disk devices */ 1014 for (i = 0; i < 8; i++) 1015 if (msg_data[i] == 0) { /* direct-access device (disk) */ 1016 host->dev_present |= (1 << i); 1017 dev_count++; 1018 } 1019 1020 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", 1021 pci_name(host->pdev), dev_count); 1022 1023out: 1024 assert(host->state == HST_PORT_SCAN); 1025 host->state = new_state; 1026 schedule_work(&host->fsm_task); 1027} 1028 1029static void carm_handle_generic(struct carm_host *host, 1030 struct carm_request *crq, int is_ok, 1031 int cur_state, int next_state) 1032{ 1033 DPRINTK("ENTER\n"); 1034 1035 carm_end_rq(host, crq, is_ok); 1036 1037 assert(host->state == cur_state); 1038 if (is_ok) 1039 host->state = next_state; 1040 else 1041 host->state = HST_ERROR; 1042 schedule_work(&host->fsm_task); 1043} 1044 1045static inline void carm_handle_rw(struct carm_host *host, 1046 struct carm_request *crq, int is_ok) 1047{ 1048 int pci_dir; 1049 1050 VPRINTK("ENTER\n"); 1051 1052 if (rq_data_dir(crq->rq) == WRITE) 1053 pci_dir = PCI_DMA_TODEVICE; 1054 else 1055 pci_dir = PCI_DMA_FROMDEVICE; 1056 1057 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); 1058 1059 carm_end_rq(host, crq, is_ok); 1060} 1061 1062static inline void carm_handle_resp(struct carm_host *host, 1063 __le32 ret_handle_le, u32 status) 1064{ 1065 u32 handle = le32_to_cpu(ret_handle_le); 1066 unsigned int msg_idx; 1067 struct carm_request *crq; 1068 int is_ok = (status == RMSG_OK); 1069 u8 *mem; 1070 1071 VPRINTK("ENTER, handle == 0x%x\n", handle); 1072 1073 if (unlikely(!TAG_VALID(handle))) { 1074 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", 1075 pci_name(host->pdev), handle); 1076 return; 1077 } 1078 1079 msg_idx = TAG_DECODE(handle); 1080 VPRINTK("tag == %u\n", msg_idx); 1081 1082 crq = &host->req[msg_idx]; 1083 1084 /* fast path */ 1085 if (likely(crq->msg_type == CARM_MSG_READ || 1086 crq->msg_type == CARM_MSG_WRITE)) { 1087 carm_handle_rw(host, crq, is_ok); 1088 return; 1089 } 1090 1091 mem = carm_ref_msg(host, msg_idx); 1092 1093 switch (crq->msg_type) { 1094 case CARM_MSG_IOCTL: { 1095 switch (crq->msg_subtype) { 1096 case CARM_IOC_SCAN_CHAN: 1097 carm_handle_scan_chan(host, crq, mem, is_ok); 1098 break; 1099 default: 1100 /* unknown / invalid response */ 1101 goto err_out; 1102 } 1103 break; 1104 } 1105 1106 case CARM_MSG_MISC: { 1107 switch (crq->msg_subtype) { 1108 case MISC_ALLOC_MEM: 1109 carm_handle_generic(host, crq, is_ok, 1110 HST_ALLOC_BUF, HST_SYNC_TIME); 1111 break; 1112 case MISC_SET_TIME: 1113 carm_handle_generic(host, crq, is_ok, 1114 HST_SYNC_TIME, HST_GET_FW_VER); 1115 break; 1116 case MISC_GET_FW_VER: { 1117 struct carm_fw_ver *ver = (struct carm_fw_ver *) 1118 mem + sizeof(struct carm_msg_get_fw_ver); 1119 if (is_ok) { 1120 host->fw_ver = le32_to_cpu(ver->version); 1121 host->flags |= (ver->features & FL_FW_VER_MASK); 1122 } 1123 carm_handle_generic(host, crq, is_ok, 1124 HST_GET_FW_VER, HST_PORT_SCAN); 1125 break; 1126 } 1127 default: 1128 /* unknown / invalid response */ 1129 goto err_out; 1130 } 1131 break; 1132 } 1133 1134 case CARM_MSG_ARRAY: { 1135 switch (crq->msg_subtype) { 1136 case CARM_ARRAY_INFO: 1137 carm_handle_array_info(host, crq, mem, is_ok); 1138 break; 1139 default: 1140 /* unknown / invalid response */ 1141 goto err_out; 1142 } 1143 break; 1144 } 1145 1146 default: 1147 /* unknown / invalid response */ 1148 goto err_out; 1149 } 1150 1151 return; 1152 1153err_out: 1154 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", 1155 pci_name(host->pdev), crq->msg_type, crq->msg_subtype); 1156 carm_end_rq(host, crq, 0); 1157} 1158 1159static inline void carm_handle_responses(struct carm_host *host) 1160{ 1161 void __iomem *mmio = host->mmio; 1162 struct carm_response *resp = (struct carm_response *) host->shm; 1163 unsigned int work = 0; 1164 unsigned int idx = host->resp_idx % RMSG_Q_LEN; 1165 1166 while (1) { 1167 u32 status = le32_to_cpu(resp[idx].status); 1168 1169 if (status == 0xffffffff) { 1170 VPRINTK("ending response on index %u\n", idx); 1171 writel(idx << 3, mmio + CARM_RESP_IDX); 1172 break; 1173 } 1174 1175 /* response to a message we sent */ 1176 else if ((status & (1 << 31)) == 0) { 1177 VPRINTK("handling msg response on index %u\n", idx); 1178 carm_handle_resp(host, resp[idx].ret_handle, status); 1179 resp[idx].status = cpu_to_le32(0xffffffff); 1180 } 1181 1182 /* asynchronous events the hardware throws our way */ 1183 else if ((status & 0xff000000) == (1 << 31)) { 1184 u8 *evt_type_ptr = (u8 *) &resp[idx]; 1185 u8 evt_type = *evt_type_ptr; 1186 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", 1187 pci_name(host->pdev), (int) evt_type); 1188 resp[idx].status = cpu_to_le32(0xffffffff); 1189 } 1190 1191 idx = NEXT_RESP(idx); 1192 work++; 1193 } 1194 1195 VPRINTK("EXIT, work==%u\n", work); 1196 host->resp_idx += work; 1197} 1198 1199static irqreturn_t carm_interrupt(int irq, void *__host, struct pt_regs *regs) 1200{ 1201 struct carm_host *host = __host; 1202 void __iomem *mmio; 1203 u32 mask; 1204 int handled = 0; 1205 unsigned long flags; 1206 1207 if (!host) { 1208 VPRINTK("no host\n"); 1209 return IRQ_NONE; 1210 } 1211 1212 spin_lock_irqsave(&host->lock, flags); 1213 1214 mmio = host->mmio; 1215 1216 /* reading should also clear interrupts */ 1217 mask = readl(mmio + CARM_INT_STAT); 1218 1219 if (mask == 0 || mask == 0xffffffff) { 1220 VPRINTK("no work, mask == 0x%x\n", mask); 1221 goto out; 1222 } 1223 1224 if (mask & INT_ACK_MASK) 1225 writel(mask, mmio + CARM_INT_STAT); 1226 1227 if (unlikely(host->state == HST_INVALID)) { 1228 VPRINTK("not initialized yet, mask = 0x%x\n", mask); 1229 goto out; 1230 } 1231 1232 if (mask & CARM_HAVE_RESP) { 1233 handled = 1; 1234 carm_handle_responses(host); 1235 } 1236 1237out: 1238 spin_unlock_irqrestore(&host->lock, flags); 1239 VPRINTK("EXIT\n"); 1240 return IRQ_RETVAL(handled); 1241} 1242 1243static void carm_fsm_task (void *_data) 1244{ 1245 struct carm_host *host = _data; 1246 unsigned long flags; 1247 unsigned int state; 1248 int rc, i, next_dev; 1249 int reschedule = 0; 1250 int new_state = HST_INVALID; 1251 1252 spin_lock_irqsave(&host->lock, flags); 1253 state = host->state; 1254 spin_unlock_irqrestore(&host->lock, flags); 1255 1256 DPRINTK("ENTER, state == %s\n", state_name[state]); 1257 1258 switch (state) { 1259 case HST_PROBE_START: 1260 new_state = HST_ALLOC_BUF; 1261 reschedule = 1; 1262 break; 1263 1264 case HST_ALLOC_BUF: 1265 rc = carm_send_special(host, carm_fill_alloc_buf); 1266 if (rc) { 1267 new_state = HST_ERROR; 1268 reschedule = 1; 1269 } 1270 break; 1271 1272 case HST_SYNC_TIME: 1273 rc = carm_send_special(host, carm_fill_sync_time); 1274 if (rc) { 1275 new_state = HST_ERROR; 1276 reschedule = 1; 1277 } 1278 break; 1279 1280 case HST_GET_FW_VER: 1281 rc = carm_send_special(host, carm_fill_get_fw_ver); 1282 if (rc) { 1283 new_state = HST_ERROR; 1284 reschedule = 1; 1285 } 1286 break; 1287 1288 case HST_PORT_SCAN: 1289 rc = carm_send_special(host, carm_fill_scan_channels); 1290 if (rc) { 1291 new_state = HST_ERROR; 1292 reschedule = 1; 1293 } 1294 break; 1295 1296 case HST_DEV_SCAN_START: 1297 host->cur_scan_dev = -1; 1298 new_state = HST_DEV_SCAN; 1299 reschedule = 1; 1300 break; 1301 1302 case HST_DEV_SCAN: 1303 next_dev = -1; 1304 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) 1305 if (host->dev_present & (1 << i)) { 1306 next_dev = i; 1307 break; 1308 } 1309 1310 if (next_dev >= 0) { 1311 host->cur_scan_dev = next_dev; 1312 rc = carm_array_info(host, next_dev); 1313 if (rc) { 1314 new_state = HST_ERROR; 1315 reschedule = 1; 1316 } 1317 } else { 1318 new_state = HST_DEV_ACTIVATE; 1319 reschedule = 1; 1320 } 1321 break; 1322 1323 case HST_DEV_ACTIVATE: { 1324 int activated = 0; 1325 for (i = 0; i < CARM_MAX_PORTS; i++) 1326 if (host->dev_active & (1 << i)) { 1327 struct carm_port *port = &host->port[i]; 1328 struct gendisk *disk = port->disk; 1329 1330 set_capacity(disk, port->capacity); 1331 add_disk(disk); 1332 activated++; 1333 } 1334 1335 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", 1336 pci_name(host->pdev), activated); 1337 1338 new_state = HST_PROBE_FINISHED; 1339 reschedule = 1; 1340 break; 1341 } 1342 1343 case HST_PROBE_FINISHED: 1344 up(&host->probe_sem); 1345 break; 1346 1347 case HST_ERROR: 1348 /* FIXME: TODO */ 1349 break; 1350 1351 default: 1352 /* should never occur */ 1353 printk(KERN_ERR PFX "BUG: unknown state %d\n", state); 1354 assert(0); 1355 break; 1356 } 1357 1358 if (new_state != HST_INVALID) { 1359 spin_lock_irqsave(&host->lock, flags); 1360 host->state = new_state; 1361 spin_unlock_irqrestore(&host->lock, flags); 1362 } 1363 if (reschedule) 1364 schedule_work(&host->fsm_task); 1365} 1366 1367static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) 1368{ 1369 unsigned int i; 1370 1371 for (i = 0; i < 50000; i++) { 1372 u32 tmp = readl(mmio + CARM_LMUC); 1373 udelay(100); 1374 1375 if (test_bit) { 1376 if ((tmp & bits) == bits) 1377 return 0; 1378 } else { 1379 if ((tmp & bits) == 0) 1380 return 0; 1381 } 1382 1383 cond_resched(); 1384 } 1385 1386 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", 1387 bits, test_bit ? "yes" : "no"); 1388 return -EBUSY; 1389} 1390 1391static void carm_init_responses(struct carm_host *host) 1392{ 1393 void __iomem *mmio = host->mmio; 1394 unsigned int i; 1395 struct carm_response *resp = (struct carm_response *) host->shm; 1396 1397 for (i = 0; i < RMSG_Q_LEN; i++) 1398 resp[i].status = cpu_to_le32(0xffffffff); 1399 1400 writel(0, mmio + CARM_RESP_IDX); 1401} 1402 1403static int carm_init_host(struct carm_host *host) 1404{ 1405 void __iomem *mmio = host->mmio; 1406 u32 tmp; 1407 u8 tmp8; 1408 int rc; 1409 1410 DPRINTK("ENTER\n"); 1411 1412 writel(0, mmio + CARM_INT_MASK); 1413 1414 tmp8 = readb(mmio + CARM_INITC); 1415 if (tmp8 & 0x01) { 1416 tmp8 &= ~0x01; 1417 writeb(tmp8, mmio + CARM_INITC); 1418 readb(mmio + CARM_INITC); /* flush */ 1419 1420 DPRINTK("snooze...\n"); 1421 msleep(5000); 1422 } 1423 1424 tmp = readl(mmio + CARM_HMUC); 1425 if (tmp & CARM_CME) { 1426 DPRINTK("CME bit present, waiting\n"); 1427 rc = carm_init_wait(mmio, CARM_CME, 1); 1428 if (rc) { 1429 DPRINTK("EXIT, carm_init_wait 1 failed\n"); 1430 return rc; 1431 } 1432 } 1433 if (tmp & CARM_RME) { 1434 DPRINTK("RME bit present, waiting\n"); 1435 rc = carm_init_wait(mmio, CARM_RME, 1); 1436 if (rc) { 1437 DPRINTK("EXIT, carm_init_wait 2 failed\n"); 1438 return rc; 1439 } 1440 } 1441 1442 tmp &= ~(CARM_RME | CARM_CME); 1443 writel(tmp, mmio + CARM_HMUC); 1444 readl(mmio + CARM_HMUC); /* flush */ 1445 1446 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); 1447 if (rc) { 1448 DPRINTK("EXIT, carm_init_wait 3 failed\n"); 1449 return rc; 1450 } 1451 1452 carm_init_buckets(mmio); 1453 1454 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); 1455 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); 1456 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); 1457 1458 tmp = readl(mmio + CARM_HMUC); 1459 tmp |= (CARM_RME | CARM_CME | CARM_WZBC); 1460 writel(tmp, mmio + CARM_HMUC); 1461 readl(mmio + CARM_HMUC); /* flush */ 1462 1463 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); 1464 if (rc) { 1465 DPRINTK("EXIT, carm_init_wait 4 failed\n"); 1466 return rc; 1467 } 1468 1469 writel(0, mmio + CARM_HMPHA); 1470 writel(INT_DEF_MASK, mmio + CARM_INT_MASK); 1471 1472 carm_init_responses(host); 1473 1474 /* start initialization, probing state machine */ 1475 spin_lock_irq(&host->lock); 1476 assert(host->state == HST_INVALID); 1477 host->state = HST_PROBE_START; 1478 spin_unlock_irq(&host->lock); 1479 schedule_work(&host->fsm_task); 1480 1481 DPRINTK("EXIT\n"); 1482 return 0; 1483} 1484 1485static int carm_init_disks(struct carm_host *host) 1486{ 1487 unsigned int i; 1488 int rc = 0; 1489 1490 for (i = 0; i < CARM_MAX_PORTS; i++) { 1491 struct gendisk *disk; 1492 request_queue_t *q; 1493 struct carm_port *port; 1494 1495 port = &host->port[i]; 1496 port->host = host; 1497 port->port_no = i; 1498 1499 disk = alloc_disk(CARM_MINORS_PER_MAJOR); 1500 if (!disk) { 1501 rc = -ENOMEM; 1502 break; 1503 } 1504 1505 port->disk = disk; 1506 sprintf(disk->disk_name, DRV_NAME "/%u", 1507 (unsigned int) (host->id * CARM_MAX_PORTS) + i); 1508 sprintf(disk->devfs_name, DRV_NAME "/%u_%u", host->id, i); 1509 disk->major = host->major; 1510 disk->first_minor = i * CARM_MINORS_PER_MAJOR; 1511 disk->fops = &carm_bd_ops; 1512 disk->private_data = port; 1513 1514 q = blk_init_queue(carm_rq_fn, &host->lock); 1515 if (!q) { 1516 rc = -ENOMEM; 1517 break; 1518 } 1519 disk->queue = q; 1520 blk_queue_max_hw_segments(q, CARM_MAX_REQ_SG); 1521 blk_queue_max_phys_segments(q, CARM_MAX_REQ_SG); 1522 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); 1523 1524 q->queuedata = port; 1525 } 1526 1527 return rc; 1528} 1529 1530static void carm_free_disks(struct carm_host *host) 1531{ 1532 unsigned int i; 1533 1534 for (i = 0; i < CARM_MAX_PORTS; i++) { 1535 struct gendisk *disk = host->port[i].disk; 1536 if (disk) { 1537 request_queue_t *q = disk->queue; 1538 1539 if (disk->flags & GENHD_FL_UP) 1540 del_gendisk(disk); 1541 if (q) 1542 blk_cleanup_queue(q); 1543 put_disk(disk); 1544 } 1545 } 1546} 1547 1548static int carm_init_shm(struct carm_host *host) 1549{ 1550 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, 1551 &host->shm_dma); 1552 if (!host->shm) 1553 return -ENOMEM; 1554 1555 host->msg_base = host->shm + RBUF_LEN; 1556 host->msg_dma = host->shm_dma + RBUF_LEN; 1557 1558 memset(host->shm, 0xff, RBUF_LEN); 1559 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); 1560 1561 return 0; 1562} 1563 1564static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) 1565{ 1566 static unsigned int printed_version; 1567 struct carm_host *host; 1568 unsigned int pci_dac; 1569 int rc; 1570 request_queue_t *q; 1571 unsigned int i; 1572 1573 if (!printed_version++) 1574 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); 1575 1576 rc = pci_enable_device(pdev); 1577 if (rc) 1578 return rc; 1579 1580 rc = pci_request_regions(pdev, DRV_NAME); 1581 if (rc) 1582 goto err_out; 1583 1584#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1585 rc = pci_set_dma_mask(pdev, 0xffffffffffffffffULL); 1586 if (!rc) { 1587 rc = pci_set_consistent_dma_mask(pdev, 0xffffffffffffffffULL); 1588 if (rc) { 1589 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", 1590 pci_name(pdev)); 1591 goto err_out_regions; 1592 } 1593 pci_dac = 1; 1594 } else { 1595#endif 1596 rc = pci_set_dma_mask(pdev, 0xffffffffULL); 1597 if (rc) { 1598 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", 1599 pci_name(pdev)); 1600 goto err_out_regions; 1601 } 1602 pci_dac = 0; 1603#if IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ 1604 } 1605#endif 1606 1607 host = kmalloc(sizeof(*host), GFP_KERNEL); 1608 if (!host) { 1609 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", 1610 pci_name(pdev)); 1611 rc = -ENOMEM; 1612 goto err_out_regions; 1613 } 1614 1615 memset(host, 0, sizeof(*host)); 1616 host->pdev = pdev; 1617 host->flags = pci_dac ? FL_DAC : 0; 1618 spin_lock_init(&host->lock); 1619 INIT_WORK(&host->fsm_task, carm_fsm_task, host); 1620 init_MUTEX_LOCKED(&host->probe_sem); 1621 1622 for (i = 0; i < ARRAY_SIZE(host->req); i++) 1623 host->req[i].tag = i; 1624 1625 host->mmio = ioremap(pci_resource_start(pdev, 0), 1626 pci_resource_len(pdev, 0)); 1627 if (!host->mmio) { 1628 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", 1629 pci_name(pdev)); 1630 rc = -ENOMEM; 1631 goto err_out_kfree; 1632 } 1633 1634 rc = carm_init_shm(host); 1635 if (rc) { 1636 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", 1637 pci_name(pdev)); 1638 goto err_out_iounmap; 1639 } 1640 1641 q = blk_init_queue(carm_oob_rq_fn, &host->lock); 1642 if (!q) { 1643 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", 1644 pci_name(pdev)); 1645 rc = -ENOMEM; 1646 goto err_out_pci_free; 1647 } 1648 host->oob_q = q; 1649 q->queuedata = host; 1650 1651 /* 1652 * Figure out which major to use: 160, 161, or dynamic 1653 */ 1654 if (!test_and_set_bit(0, &carm_major_alloc)) 1655 host->major = 160; 1656 else if (!test_and_set_bit(1, &carm_major_alloc)) 1657 host->major = 161; 1658 else 1659 host->flags |= FL_DYN_MAJOR; 1660 1661 host->id = carm_host_id; 1662 sprintf(host->name, DRV_NAME "%d", carm_host_id); 1663 1664 rc = register_blkdev(host->major, host->name); 1665 if (rc < 0) 1666 goto err_out_free_majors; 1667 if (host->flags & FL_DYN_MAJOR) 1668 host->major = rc; 1669 1670 devfs_mk_dir(DRV_NAME); 1671 1672 rc = carm_init_disks(host); 1673 if (rc) 1674 goto err_out_blkdev_disks; 1675 1676 pci_set_master(pdev); 1677 1678 rc = request_irq(pdev->irq, carm_interrupt, SA_SHIRQ, DRV_NAME, host); 1679 if (rc) { 1680 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", 1681 pci_name(pdev)); 1682 goto err_out_blkdev_disks; 1683 } 1684 1685 rc = carm_init_host(host); 1686 if (rc) 1687 goto err_out_free_irq; 1688 1689 DPRINTK("waiting for probe_sem\n"); 1690 down(&host->probe_sem); 1691 1692 printk(KERN_INFO "%s: pci %s, ports %d, io %lx, irq %u, major %d\n", 1693 host->name, pci_name(pdev), (int) CARM_MAX_PORTS, 1694 pci_resource_start(pdev, 0), pdev->irq, host->major); 1695 1696 carm_host_id++; 1697 pci_set_drvdata(pdev, host); 1698 return 0; 1699 1700err_out_free_irq: 1701 free_irq(pdev->irq, host); 1702err_out_blkdev_disks: 1703 carm_free_disks(host); 1704 unregister_blkdev(host->major, host->name); 1705err_out_free_majors: 1706 if (host->major == 160) 1707 clear_bit(0, &carm_major_alloc); 1708 else if (host->major == 161) 1709 clear_bit(1, &carm_major_alloc); 1710 blk_cleanup_queue(host->oob_q); 1711err_out_pci_free: 1712 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1713err_out_iounmap: 1714 iounmap(host->mmio); 1715err_out_kfree: 1716 kfree(host); 1717err_out_regions: 1718 pci_release_regions(pdev); 1719err_out: 1720 pci_disable_device(pdev); 1721 return rc; 1722} 1723 1724static void carm_remove_one (struct pci_dev *pdev) 1725{ 1726 struct carm_host *host = pci_get_drvdata(pdev); 1727 1728 if (!host) { 1729 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", 1730 pci_name(pdev)); 1731 return; 1732 } 1733 1734 free_irq(pdev->irq, host); 1735 carm_free_disks(host); 1736 devfs_remove(DRV_NAME); 1737 unregister_blkdev(host->major, host->name); 1738 if (host->major == 160) 1739 clear_bit(0, &carm_major_alloc); 1740 else if (host->major == 161) 1741 clear_bit(1, &carm_major_alloc); 1742 blk_cleanup_queue(host->oob_q); 1743 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); 1744 iounmap(host->mmio); 1745 kfree(host); 1746 pci_release_regions(pdev); 1747 pci_disable_device(pdev); 1748 pci_set_drvdata(pdev, NULL); 1749} 1750 1751static int __init carm_init(void) 1752{ 1753 return pci_module_init(&carm_driver); 1754} 1755 1756static void __exit carm_exit(void) 1757{ 1758 pci_unregister_driver(&carm_driver); 1759} 1760 1761module_init(carm_init); 1762module_exit(carm_exit); 1763 1764