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1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_LPPACA_H
20#define _ASM_LPPACA_H
21
22//=============================================================================
23//
24// This control block contains the data that is shared between the
25// hypervisor (PLIC) and the OS.
26//
27//
28//----------------------------------------------------------------------------
29#include <asm/types.h>
30
31struct lppaca
32{
33//=============================================================================
34// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
35// NOTE: The xDynXyz fields are fields that will be dynamically changed by
36// PLIC when preparing to bring a processor online or when dispatching a
37// virtual processor!
38//=============================================================================
39 u32 desc; // Eye catcher 0xD397D781 x00-x03
40 u16 size; // Size of this struct x04-x05
41 u16 reserved1; // Reserved x06-x07
42 u16 reserved2:14; // Reserved x08-x09
43 u8 shared_proc:1; // Shared processor indicator ...
44 u8 secondary_thread:1; // Secondary thread indicator ...
45 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
46 u8 secondary_thread_count; // Secondary thread count x0B-x0B
47 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
48 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
49 u32 decr_val; // Value for Decr programming x10-x13
50 u32 pmc_val; // Value for PMC regs x14-x17
51 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
52 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
53 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
54 u32 dsei_data; // DSEI data x24-x27
55 u64 sprg3; // SPRG3 value x28-x2F
56 u8 reserved3[80]; // Reserved x30-x7F
57
58//=============================================================================
59// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
60//=============================================================================
61 // This Dword contains a byte for each type of interrupt that can occur.
62 // The IPI is a count while the others are just a binary 1 or 0.
63 union {
64 u64 any_int;
65 struct {
66 u16 reserved; // Reserved - cleared by #mpasmbl
67 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
68 u8 ipi_cnt; // IPI Count
69 u8 decr_int; // DECR interrupt occurred
70 u8 pdc_int; // PDC interrupt occurred
71 u8 quantum_int; // Interrupt quantum reached
72 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
73 } fields;
74 } int_dword;
75
76 // Whenever any fields in this Dword are set then PLIC will defer the
77 // processing of external interrupts. Note that PLIC will store the
78 // XIRR directly into the xXirrValue field so that another XIRR will
79 // not be presented until this one clears. The layout of the low
80 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
81 // entire Dword is zero or not. A non-zero value in the low order
82 // 2-bytes will result in SLIC being granted the highest thread
83 // priority upon return. A 0 will return to SLIC as medium priority.
84 u64 plic_defer_ints_area; // Entire Dword
85
86 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
87 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
88 u64 saved_srr0; // Saved SRR0 x10-x17
89 u64 saved_srr1; // Saved SRR1 x18-x1F
90
91 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
92 u64 saved_gpr3; // Saved GPR3 x20-x27
93 u64 saved_gpr4; // Saved GPR4 x28-x2F
94 u64 saved_gpr5; // Saved GPR5 x30-x37
95
96 u8 reserved4; // Reserved x38-x38
97 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39
98 u8 fpregs_in_use; // FP regs in use x3A-x3A
99 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
100 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
101 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
102 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
103 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
104 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
105 u64 end_of_quantum; // TB at end of quantum x60-x67
106 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
107 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
108 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
109 u16 slb_count; // # of SLBs to maintain x7C-x7D
110 u8 idle; // Indicate OS is idle x7E
111 u8 reserved5; // Reserved x7F
112
113
114//=============================================================================
115// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
116//=============================================================================
117 // This is the yield_count. An "odd" value (low bit on) means that
118 // the processor is yielded (either because of an OS yield or a PLIC
119 // preempt). An even value implies that the processor is currently
120 // executing.
121 // NOTE: This value will ALWAYS be zero for dedicated processors and
122 // will NEVER be zero for shared processors (ie, initialized to a 1).
123 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
124 u8 reserved6[124]; // Reserved x04-x7F
125
126//=============================================================================
127// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
128//=============================================================================
129 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
130};
131
132#endif /* _ASM_LPPACA_H */