tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * include/asm-ppc/ibm44x.h
3 *
4 * PPC44x definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_IBM44x_H__
18#define __ASM_IBM44x_H__
19
20#include <linux/config.h>
21
22#ifndef NR_BOARD_IRQS
23#define NR_BOARD_IRQS 0
24#endif
25
26#define _IO_BASE isa_io_base
27#define _ISA_MEM_BASE isa_mem_base
28#define PCI_DRAM_OFFSET pci_dram_offset
29
30/* TLB entry offset/size used for pinning kernel lowmem */
31#define PPC44x_PIN_SHIFT 28
32#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
33
34/* Lowest TLB slot consumed by the default pinned TLBs */
35#define PPC44x_LOW_SLOT 63
36
37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#ifdef CONFIG_440SP
39#define UART0_PHYS_IO_BASE 0xf0000200
40#else
41#define UART0_PHYS_IO_BASE 0x40000200
42#endif
43
44/*
45 * XXX This 36-bit trap stuff will move somewhere in syslib/
46 * when we rework/abstract the PPC44x PCI-X handling -mdp
47 */
48
49/*
50 * Standard 4GB "page" definitions
51 */
52#ifdef CONFIG_440SP
53#define PPC44x_IO_PAGE 0x0000000100000000ULL
54#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
57#else
58#define PPC44x_IO_PAGE 0x0000000100000000ULL
59#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
60#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
61#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
62#endif
63
64/*
65 * 36-bit trap ranges
66 */
67#ifdef CONFIG_440SP
68#define PPC44x_IO_LO 0xf0000000UL
69#define PPC44x_IO_HI 0xf0000fffUL
70#define PPC44x_PCI0CFG_LO 0x0ec00000UL
71#define PPC44x_PCI0CFG_HI 0x0ec00007UL
72#define PPC44x_PCI1CFG_LO 0x1ec00000UL
73#define PPC44x_PCI1CFG_HI 0x1ec00007UL
74#define PPC44x_PCI2CFG_LO 0x2ec00000UL
75#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76#define PPC44x_PCIMEM_LO 0x80000000UL
77#define PPC44x_PCIMEM_HI 0xdfffffffUL
78#else
79#define PPC44x_IO_LO 0x40000000UL
80#define PPC44x_IO_HI 0x40000fffUL
81#define PPC44x_PCI0CFG_LO 0x0ec00000UL
82#define PPC44x_PCI0CFG_HI 0x0ec00007UL
83#define PPC44x_PCIMEM_LO 0x80002000UL
84#define PPC44x_PCIMEM_HI 0xffffffffUL
85#endif
86
87/*
88 * The "residual" board information structure the boot loader passes
89 * into the kernel.
90 */
91#ifndef __ASSEMBLY__
92
93/*
94 * DCRN definitions
95 */
96
97
98/* CPRs (440GX and 440SP) */
99#define DCRN_CPR_CONFIG_ADDR 0xc
100#define DCRN_CPR_CONFIG_DATA 0xd
101
102#define DCRN_CPR_CLKUPD 0x0020
103#define DCRN_CPR_PLLC 0x0040
104#define DCRN_CPR_PLLD 0x0060
105#define DCRN_CPR_PRIMAD 0x0080
106#define DCRN_CPR_PRIMBD 0x00a0
107#define DCRN_CPR_OPBD 0x00c0
108#define DCRN_CPR_PERD 0x00e0
109#define DCRN_CPR_MALD 0x0100
110
111/* CPRs read/write helper macros */
112#define CPR_READ(offset) ({\
113 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
114 mfdcr(DCRN_CPR_CONFIG_DATA);})
115#define CPR_WRITE(offset, data) ({\
116 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
117 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
118
119/* SDRs (440GX and 440SP) */
120#define DCRN_SDR_CONFIG_ADDR 0xe
121#define DCRN_SDR_CONFIG_DATA 0xf
122#define DCRN_SDR_PFC0 0x4100
123#define DCRN_SDR_PFC1 0x4101
124#define DCRN_SDR_PFC1_EPS 0x1c00000
125#define DCRN_SDR_PFC1_EPS_SHIFT 22
126#define DCRN_SDR_PFC1_RMII 0x02000000
127#define DCRN_SDR_MFR 0x4300
128#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
129#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
130#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
131#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
132#define DCRN_SDR_MFR_T0TXFL 0x00080000
133#define DCRN_SDR_MFR_T0TXFH 0x00040000
134#define DCRN_SDR_MFR_T1TXFL 0x00020000
135#define DCRN_SDR_MFR_T1TXFH 0x00010000
136#define DCRN_SDR_MFR_E0TXFL 0x00008000
137#define DCRN_SDR_MFR_E0TXFH 0x00004000
138#define DCRN_SDR_MFR_E0RXFL 0x00002000
139#define DCRN_SDR_MFR_E0RXFH 0x00001000
140#define DCRN_SDR_MFR_E1TXFL 0x00000800
141#define DCRN_SDR_MFR_E1TXFH 0x00000400
142#define DCRN_SDR_MFR_E1RXFL 0x00000200
143#define DCRN_SDR_MFR_E1RXFH 0x00000100
144#define DCRN_SDR_MFR_E2TXFL 0x00000080
145#define DCRN_SDR_MFR_E2TXFH 0x00000040
146#define DCRN_SDR_MFR_E2RXFL 0x00000020
147#define DCRN_SDR_MFR_E2RXFH 0x00000010
148#define DCRN_SDR_MFR_E3TXFL 0x00000008
149#define DCRN_SDR_MFR_E3TXFH 0x00000004
150#define DCRN_SDR_MFR_E3RXFL 0x00000002
151#define DCRN_SDR_MFR_E3RXFH 0x00000001
152#define DCRN_SDR_UART0 0x0120
153#define DCRN_SDR_UART1 0x0121
154
155/* SDR read/write helper macros */
156#define SDR_READ(offset) ({\
157 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
158 mfdcr(DCRN_SDR_CONFIG_DATA);})
159#define SDR_WRITE(offset, data) ({\
160 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
161 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
162
163/* DMA (excluding 440SP) */
164#define DCRN_DMA0_BASE 0x100
165#define DCRN_DMA1_BASE 0x108
166#define DCRN_DMA2_BASE 0x110
167#define DCRN_DMA3_BASE 0x118
168#define DCRN_DMASR_BASE 0x120
169#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170#define DCRN_MAL_BASE 0x180
171
172/* UIC */
173#define DCRN_UIC0_BASE 0xc0
174#define DCRN_UIC1_BASE 0xd0
175#define DCRN_UIC2_BASE 0x210
176#define DCRN_UICB_BASE 0x200
177#define UIC0 DCRN_UIC0_BASE
178#define UIC1 DCRN_UIC1_BASE
179#define UIC2 DCRN_UIC2_BASE
180#define UICB DCRN_UICB_BASE
181
182#define DCRN_UIC_SR(base) (base + 0x0)
183#define DCRN_UIC_ER(base) (base + 0x2)
184#define DCRN_UIC_CR(base) (base + 0x3)
185#define DCRN_UIC_PR(base) (base + 0x4)
186#define DCRN_UIC_TR(base) (base + 0x5)
187#define DCRN_UIC_MSR(base) (base + 0x6)
188#define DCRN_UIC_VR(base) (base + 0x7)
189#define DCRN_UIC_VCR(base) (base + 0x8)
190
191#define UIC0_UIC1NC 0x00000002
192
193#define UICB_UIC0NC 0x40000000
194#define UICB_UIC1NC 0x10000000
195#define UICB_UIC2NC 0x04000000
196
197/* 440 MAL DCRs */
198#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
199#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
200#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
201#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
202#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
203#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
204#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
205#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
206#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
207#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
208#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
209#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
210#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
211#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
212#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
213#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
214#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
215#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
216#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
217
218/* Compatibility DCRN's */
219#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
220#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
221#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
222#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
223#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
224#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
225#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
226#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
227
228#define MALCR_MMSR 0x80000000 /* MAL Software reset */
229#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
230#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
231#define MALCR_PLBP_3 0x00C00000 /* highest */
232#define MALCR_GA 0x00200000 /* Guarded Active Bit */
233#define MALCR_OA 0x00100000 /* Ordered Active Bit */
234#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
235#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
236#define MALCR_PLBLT_2 0x00020000
237#define MALCR_PLBLT_3 0x00010000
238#define MALCR_PLBLT_4 0x00008000
239#ifdef CONFIG_440GP
240#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
241#else
242#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
243#endif
244#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
245#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
246#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
247#define MALCR_LEA 0x00000002 /* Locked Error Active */
248#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
249/* DCRN_MALESR */
250#define MALESR_EVB 0x80000000 /* Error Valid Bit */
251#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
252#define MALESR_DE 0x00100000 /* Descriptor Error */
253#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
254#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
255#define MALESR_OSE 0x00020000 /* OPB Slave Error */
256#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
257#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
258#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
259#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
260#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
261#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
262/* DCRN_MALIER */
263#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
264#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
265#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
266#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
267#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
268/* DCRN_MALTXEOBISR */
269#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
270#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
271
272/* 440GP/GX PLB Arbiter DCRs */
273#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
274#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
275#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
276#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
277#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
278#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
279
280/* 440GP/GX PLB to OPB bridge DCRs */
281#define DCRN_POB0_BESR0 0x090
282#define DCRN_POB0_BESR1 0x094
283#define DCRN_POB0_BEARL 0x092
284#define DCRN_POB0_BEARH 0x093
285
286/* 440GP/GX OPB to PLB bridge DCRs */
287#define DCRN_OPB0_BSTAT 0x0a9
288#define DCRN_OPB0_BEARL 0x0aa
289#define DCRN_OPB0_BEARH 0x0ab
290
291/* 440GP Clock, PM, chip control */
292#define DCRN_CPC0_SR 0x0b0
293#define DCRN_CPC0_ER 0x0b1
294#define DCRN_CPC0_FR 0x0b2
295#define DCRN_CPC0_SYS0 0x0e0
296#define DCRN_CPC0_SYS1 0x0e1
297#define DCRN_CPC0_CUST0 0x0e2
298#define DCRN_CPC0_CUST1 0x0e3
299#define DCRN_CPC0_STRP0 0x0e4
300#define DCRN_CPC0_STRP1 0x0e5
301#define DCRN_CPC0_STRP2 0x0e6
302#define DCRN_CPC0_STRP3 0x0e7
303#define DCRN_CPC0_GPIO 0x0e8
304#define DCRN_CPC0_PLB 0x0e9
305#define DCRN_CPC0_CR1 0x0ea
306#define DCRN_CPC0_CR0 0x0eb
307#define DCRN_CPC0_MIRQ0 0x0ec
308#define DCRN_CPC0_MIRQ1 0x0ed
309#define DCRN_CPC0_JTAGID 0x0ef
310
311/* 440GP DMA controller DCRs */
312#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
313#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
314#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
315#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
316#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
317#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
318#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
319#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
320
321#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
322#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
323#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
324#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
325#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
326#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
327#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
328#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
329
330#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
331#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
332#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
333#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
334#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
335#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
336#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
337#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
338
339#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
340#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
341#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
342#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
343#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
344#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
345#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
346#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
347
348#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
349#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
350#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
351#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
352
353/* 440GP/440GX SDRAM controller DCRs */
354#define DCRN_SDRAM0_CFGADDR 0x010
355#define DCRN_SDRAM0_CFGDATA 0x011
356
357#define SDRAM0_B0CR 0x40
358#define SDRAM0_B1CR 0x44
359#define SDRAM0_B2CR 0x48
360#define SDRAM0_B3CR 0x4c
361
362#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
363#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
364#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
365#define SDRAM_CONFIG_SIZE_8M 0x00000001
366#define SDRAM_CONFIG_SIZE_16M 0x00000002
367#define SDRAM_CONFIG_SIZE_32M 0x00000003
368#define SDRAM_CONFIG_SIZE_64M 0x00000004
369#define SDRAM_CONFIG_SIZE_128M 0x00000005
370#define SDRAM_CONFIG_SIZE_256M 0x00000006
371#define SDRAM_CONFIG_SIZE_512M 0x00000007
372#define PPC44x_MEM_SIZE_8M 0x00800000
373#define PPC44x_MEM_SIZE_16M 0x01000000
374#define PPC44x_MEM_SIZE_32M 0x02000000
375#define PPC44x_MEM_SIZE_64M 0x04000000
376#define PPC44x_MEM_SIZE_128M 0x08000000
377#define PPC44x_MEM_SIZE_256M 0x10000000
378#define PPC44x_MEM_SIZE_512M 0x20000000
379#define PPC44x_MEM_SIZE_1G 0x40000000
380#define PPC44x_MEM_SIZE_2G 0x80000000
381
382/* 440SP memory controller DCRs */
383#define DCRN_MQ0_BS0BAS 0x40
384#define DCRN_MQ0_BS1BAS 0x41
385
386#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
387#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
388#define MQ0_CONFIG_SIZE_16M 0x0000ff80
389#define MQ0_CONFIG_SIZE_32M 0x0000ff00
390#define MQ0_CONFIG_SIZE_64M 0x0000fe00
391#define MQ0_CONFIG_SIZE_128M 0x0000fc00
392#define MQ0_CONFIG_SIZE_256M 0x0000f800
393#define MQ0_CONFIG_SIZE_512M 0x0000f000
394#define MQ0_CONFIG_SIZE_1G 0x0000e000
395#define MQ0_CONFIG_SIZE_2G 0x0000c000
396
397/* Internal SRAM Controller 440GX/440SP */
398#ifdef CONFIG_440SP
399#define DCRN_SRAM0_BASE 0x100
400#else /* 440GX */
401#define DCRN_SRAM0_BASE 0x000
402#endif
403
404#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
405#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
406#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022)
407#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023)
408#define SRAM_SBCR_BAS0 0x80000000
409#define SRAM_SBCR_BAS1 0x80010000
410#define SRAM_SBCR_BAS2 0x80020000
411#define SRAM_SBCR_BAS3 0x80030000
412#define SRAM_SBCR_BU_MASK 0x00000180
413#define SRAM_SBCR_BS_64KB 0x00000800
414#define SRAM_SBCR_BU_RO 0x00000080
415#define SRAM_SBCR_BU_RW 0x00000180
416#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024)
417#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025)
418#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026)
419#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027)
420#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028)
421#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029)
422#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
423#define SRAM_DPC_ENABLE 0x80000000
424
425/* L2 Cache Controller 440GX/440SP */
426#define DCRN_L2C0_CFG 0x030
427#define L2C_CFG_L2M 0x80000000
428#define L2C_CFG_ICU 0x40000000
429#define L2C_CFG_DCU 0x20000000
430#define L2C_CFG_DCW_MASK 0x1e000000
431#define L2C_CFG_TPC 0x01000000
432#define L2C_CFG_CPC 0x00800000
433#define L2C_CFG_FRAN 0x00200000
434#define L2C_CFG_SS_MASK 0x00180000
435#define L2C_CFG_SS_256 0x00000000
436#define L2C_CFG_CPIM 0x00040000
437#define L2C_CFG_TPIM 0x00020000
438#define L2C_CFG_LIM 0x00010000
439#define L2C_CFG_PMUX_MASK 0x00007000
440#define L2C_CFG_PMUX_SNP 0x00000000
441#define L2C_CFG_PMUX_IF 0x00001000
442#define L2C_CFG_PMUX_DF 0x00002000
443#define L2C_CFG_PMUX_DS 0x00003000
444#define L2C_CFG_PMIM 0x00000800
445#define L2C_CFG_TPEI 0x00000400
446#define L2C_CFG_CPEI 0x00000200
447#define L2C_CFG_NAM 0x00000100
448#define L2C_CFG_SMCM 0x00000080
449#define L2C_CFG_NBRM 0x00000040
450#define DCRN_L2C0_CMD 0x031
451#define L2C_CMD_CLR 0x80000000
452#define L2C_CMD_DIAG 0x40000000
453#define L2C_CMD_INV 0x20000000
454#define L2C_CMD_CCP 0x10000000
455#define L2C_CMD_CTE 0x08000000
456#define L2C_CMD_STRC 0x04000000
457#define L2C_CMD_STPC 0x02000000
458#define L2C_CMD_RPMC 0x01000000
459#define L2C_CMD_HCC 0x00800000
460#define DCRN_L2C0_ADDR 0x032
461#define DCRN_L2C0_DATA 0x033
462#define DCRN_L2C0_SR 0x034
463#define L2C_SR_CC 0x80000000
464#define L2C_SR_CPE 0x40000000
465#define L2C_SR_TPE 0x20000000
466#define L2C_SR_LRU 0x10000000
467#define L2C_SR_PCS 0x08000000
468#define DCRN_L2C0_REVID 0x035
469#define DCRN_L2C0_SNP0 0x036
470#define DCRN_L2C0_SNP1 0x037
471#define L2C_SNP_BA_MASK 0xffff0000
472#define L2C_SNP_SSR_MASK 0x0000f000
473#define L2C_SNP_SSR_32G 0x0000f000
474#define L2C_SNP_ESR 0x00000800
475
476/*
477 * PCI-X definitions
478 */
479#define PCIX0_CFGA 0x0ec00000UL
480#define PCIX1_CFGA 0x1ec00000UL
481#define PCIX2_CFGA 0x2ec00000UL
482#define PCIX0_CFGD 0x0ec00004UL
483#define PCIX1_CFGD 0x1ec00004UL
484#define PCIX2_CFGD 0x2ec00004UL
485
486#define PCIX0_IO_BASE 0x0000000908000000ULL
487#define PCIX1_IO_BASE 0x0000000908000000ULL
488#define PCIX2_IO_BASE 0x0000000908000000ULL
489#define PCIX_IO_SIZE 0x00010000
490
491#ifdef CONFIG_440SP
492#define PCIX0_REG_BASE 0x000000090ec80000ULL
493#else
494#define PCIX0_REG_BASE 0x000000020ec80000ULL
495#endif
496#define PCIX_REG_OFFSET 0x10000000
497#define PCIX_REG_SIZE 0x200
498
499#define PCIX0_VENDID 0x000
500#define PCIX0_DEVID 0x002
501#define PCIX0_COMMAND 0x004
502#define PCIX0_STATUS 0x006
503#define PCIX0_REVID 0x008
504#define PCIX0_CLS 0x009
505#define PCIX0_CACHELS 0x00c
506#define PCIX0_LATTIM 0x00d
507#define PCIX0_HDTYPE 0x00e
508#define PCIX0_BIST 0x00f
509#define PCIX0_BAR0L 0x010
510#define PCIX0_BAR0H 0x014
511#define PCIX0_BAR1 0x018
512#define PCIX0_BAR2L 0x01c
513#define PCIX0_BAR2H 0x020
514#define PCIX0_BAR3 0x024
515#define PCIX0_CISPTR 0x028
516#define PCIX0_SBSYSVID 0x02c
517#define PCIX0_SBSYSID 0x02e
518#define PCIX0_EROMBA 0x030
519#define PCIX0_CAP 0x034
520#define PCIX0_RES0 0x035
521#define PCIX0_RES1 0x036
522#define PCIX0_RES2 0x038
523#define PCIX0_INTLN 0x03c
524#define PCIX0_INTPN 0x03d
525#define PCIX0_MINGNT 0x03e
526#define PCIX0_MAXLTNCY 0x03f
527#define PCIX0_BRDGOPT1 0x040
528#define PCIX0_BRDGOPT2 0x044
529#define PCIX0_ERREN 0x050
530#define PCIX0_ERRSTS 0x054
531#define PCIX0_PLBBESR 0x058
532#define PCIX0_PLBBEARL 0x05c
533#define PCIX0_PLBBEARH 0x060
534#define PCIX0_POM0LAL 0x068
535#define PCIX0_POM0LAH 0x06c
536#define PCIX0_POM0SA 0x070
537#define PCIX0_POM0PCIAL 0x074
538#define PCIX0_POM0PCIAH 0x078
539#define PCIX0_POM1LAL 0x07c
540#define PCIX0_POM1LAH 0x080
541#define PCIX0_POM1SA 0x084
542#define PCIX0_POM1PCIAL 0x088
543#define PCIX0_POM1PCIAH 0x08c
544#define PCIX0_POM2SA 0x090
545#define PCIX0_PIM0SAL 0x098
546#define PCIX0_PIM0SA PCIX0_PIM0SAL
547#define PCIX0_PIM0LAL 0x09c
548#define PCIX0_PIM0LAH 0x0a0
549#define PCIX0_PIM1SA 0x0a4
550#define PCIX0_PIM1LAL 0x0a8
551#define PCIX0_PIM1LAH 0x0ac
552#define PCIX0_PIM2SAL 0x0b0
553#define PCIX0_PIM2SA PCIX0_PIM2SAL
554#define PCIX0_PIM2LAL 0x0b4
555#define PCIX0_PIM2LAH 0x0b8
556#define PCIX0_OMCAPID 0x0c0
557#define PCIX0_OMNIPTR 0x0c1
558#define PCIX0_OMMC 0x0c2
559#define PCIX0_OMMA 0x0c4
560#define PCIX0_OMMUA 0x0c8
561#define PCIX0_OMMDATA 0x0cc
562#define PCIX0_OMMEOI 0x0ce
563#define PCIX0_PMCAPID 0x0d0
564#define PCIX0_PMNIPTR 0x0d1
565#define PCIX0_PMC 0x0d2
566#define PCIX0_PMCSR 0x0d4
567#define PCIX0_PMCSRBSE 0x0d6
568#define PCIX0_PMDATA 0x0d7
569#define PCIX0_PMSCRR 0x0d8
570#define PCIX0_CAPID 0x0dc
571#define PCIX0_NIPTR 0x0dd
572#define PCIX0_CMD 0x0de
573#define PCIX0_STS 0x0e0
574#define PCIX0_IDR 0x0e4
575#define PCIX0_CID 0x0e8
576#define PCIX0_RID 0x0ec
577#define PCIX0_PIM0SAH 0x0f8
578#define PCIX0_PIM2SAH 0x0fc
579#define PCIX0_MSGIL 0x100
580#define PCIX0_MSGIH 0x104
581#define PCIX0_MSGOL 0x108
582#define PCIX0_MSGOH 0x10c
583#define PCIX0_IM 0x1f8
584
585#define IIC_OWN 0x55
586#define IIC_CLOCK 50
587
588#undef NR_UICS
589#ifdef CONFIG_440GX
590#define NR_UICS 3
591#else
592#define NR_UICS 2
593#endif
594
595#include <asm/ibm4xx.h>
596
597#endif /* __ASSEMBLY__ */
598#endif /* __ASM_IBM44x_H__ */
599#endif /* __KERNEL__ */