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Linux kernel mirror (for testing)
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linux
1/*
2 * include/asm-v850/rte_me2_cb.h -- Midas labs RTE-V850E/ME2-CB board
3 *
4 * Copyright (C) 2001,02,03 NEC Corporation
5 * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
6 *
7 * This file is subject to the terms and conditions of the GNU General
8 * Public License. See the file COPYING in the main directory of this
9 * archive for more details.
10 *
11 * Written by Miles Bader <miles@gnu.org>
12 */
13
14#ifndef __V850_RTE_ME2_CB_H__
15#define __V850_RTE_ME2_CB_H__
16
17#include <asm/rte_cb.h> /* Common defs for Midas RTE-CB boards. */
18
19
20#define PLATFORM "rte-v850e/me2-cb"
21#define PLATFORM_LONG "Midas lab RTE-V850E/ME2-CB"
22
23#define CPU_CLOCK_FREQ 150000000 /* 150MHz */
24#define FIXED_BOGOMIPS 50
25
26/* 32MB of onbard SDRAM. */
27#define SDRAM_ADDR 0x00800000
28#define SDRAM_SIZE 0x02000000 /* 32MB */
29
30
31/* CPU addresses of GBUS memory spaces. */
32#define GCS0_ADDR 0x04000000 /* GCS0 - Common SRAM (2MB) */
33#define GCS0_SIZE 0x00800000 /* 8MB */
34#define GCS1_ADDR 0x04800000 /* GCS1 - Flash ROM (8MB) */
35#define GCS1_SIZE 0x00800000 /* 8MB */
36#define GCS2_ADDR 0x07000000 /* GCS2 - I/O registers */
37#define GCS2_SIZE 0x00800000 /* 8MB */
38#define GCS5_ADDR 0x08000000 /* GCS5 - PCI bus space */
39#define GCS5_SIZE 0x02000000 /* 32MB */
40#define GCS6_ADDR 0x07800000 /* GCS6 - PCI control registers */
41#define GCS6_SIZE 0x00800000 /* 8MB */
42
43
44/* For <asm/page.h> */
45#define PAGE_OFFSET SDRAM_ADDR
46
47
48#ifdef CONFIG_ROM_KERNEL
49/* Kernel is in ROM, starting at address 0. */
50
51#define INTV_BASE 0
52#define ROOT_FS_IMAGE_RW 0
53
54#else /* !CONFIG_ROM_KERNEL */
55/* Using RAM-kernel. Assume some sort of boot-loader got us loaded at
56 address 0. */
57
58#define INTV_BASE 0
59#define ROOT_FS_IMAGE_RW 1
60
61#endif /* CONFIG_ROM_KERNEL */
62
63
64/* Some misc. on-board devices. */
65
66/* Seven-segment LED display (four digits). */
67#define LED_ADDR(n) (0x0FE02000 + (n))
68#define LED(n) (*(volatile unsigned char *)LED_ADDR(n))
69#define LED_NUM_DIGITS 4
70
71
72/* On-board PIC. */
73
74#define CB_PIC_BASE_ADDR 0x0FE04000
75
76#define CB_PIC_INT0M_ADDR (CB_PIC_BASE_ADDR + 0x00)
77#define CB_PIC_INT0M (*(volatile u16 *)CB_PIC_INT0M_ADDR)
78#define CB_PIC_INT1M_ADDR (CB_PIC_BASE_ADDR + 0x10)
79#define CB_PIC_INT1M (*(volatile u16 *)CB_PIC_INT1M_ADDR)
80#define CB_PIC_INTR_ADDR (CB_PIC_BASE_ADDR + 0x20)
81#define CB_PIC_INTR (*(volatile u16 *)CB_PIC_INTR_ADDR)
82#define CB_PIC_INTEN_ADDR (CB_PIC_BASE_ADDR + 0x30)
83#define CB_PIC_INTEN (*(volatile u16 *)CB_PIC_INTEN_ADDR)
84
85#define CB_PIC_INT0EN 0x0001
86#define CB_PIC_INT1EN 0x0002
87#define CB_PIC_INT0SEL 0x0080
88
89/* The PIC interrupts themselves. */
90#define CB_PIC_BASE_IRQ NUM_CPU_IRQS
91#define IRQ_CB_PIC_NUM 10
92
93/* Some specific CB_PIC interrupts. */
94#define IRQ_CB_EXTTM0 (CB_PIC_BASE_IRQ + 0)
95#define IRQ_CB_EXTSIO (CB_PIC_BASE_IRQ + 1)
96#define IRQ_CB_TOVER (CB_PIC_BASE_IRQ + 2)
97#define IRQ_CB_GINT0 (CB_PIC_BASE_IRQ + 3)
98#define IRQ_CB_USB (CB_PIC_BASE_IRQ + 4)
99#define IRQ_CB_LANC (CB_PIC_BASE_IRQ + 5)
100#define IRQ_CB_USB_VBUS_ON (CB_PIC_BASE_IRQ + 6)
101#define IRQ_CB_USB_VBUS_OFF (CB_PIC_BASE_IRQ + 7)
102#define IRQ_CB_EXTTM1 (CB_PIC_BASE_IRQ + 8)
103#define IRQ_CB_EXTTM2 (CB_PIC_BASE_IRQ + 9)
104
105/* The GBUS GINT1 - GINT3 (note, not GINT0!) interrupts are connected to
106 the INTP65 - INTP67 pins on the CPU. These are shared among the GBUS
107 interrupts. */
108#define IRQ_GINT(n) IRQ_INTP((n) + 9) /* 0 is unused! */
109#define IRQ_GINT_NUM 4 /* 0 is unused! */
110
111/* The shared interrupt line from the PIC is connected to CPU pin INTP23. */
112#define IRQ_CB_PIC IRQ_INTP(4) /* P23 */
113
114/* Used by <asm/rte_cb.h> to derive NUM_MACH_IRQS. */
115#define NUM_RTE_CB_IRQS (NUM_CPU_IRQS + IRQ_CB_PIC_NUM)
116
117
118#ifndef __ASSEMBLY__
119struct cb_pic_irq_init {
120 const char *name; /* name of interrupt type */
121
122 /* Range of kernel irq numbers for this type:
123 BASE, BASE+INTERVAL, ..., BASE+INTERVAL*NUM */
124 unsigned base, num, interval;
125
126 unsigned priority; /* interrupt priority to assign */
127};
128struct hw_interrupt_type; /* fwd decl */
129
130/* Enable interrupt handling for interrupt IRQ. */
131extern void cb_pic_enable_irq (unsigned irq);
132/* Disable interrupt handling for interrupt IRQ. Note that any interrupts
133 received while disabled will be delivered once the interrupt is enabled
134 again, unless they are explicitly cleared using `cb_pic_clear_pending_irq'. */
135extern void cb_pic_disable_irq (unsigned irq);
136/* Initialize HW_IRQ_TYPES for PIC irqs described in array INITS (which is
137 terminated by an entry with the name field == 0). */
138extern void cb_pic_init_irq_types (struct cb_pic_irq_init *inits,
139 struct hw_interrupt_type *hw_irq_types);
140/* Initialize PIC interrupts. */
141extern void cb_pic_init_irqs (void);
142#endif /* __ASSEMBLY__ */
143
144
145/* TL16C550C on board UART see also asm/serial.h */
146#define CB_UART_BASE 0x0FE08000
147#define CB_UART_REG_GAP 0x10
148#define CB_UART_CLOCK 0x16000000
149
150/* CompactFlash setting */
151#define CB_CF_BASE 0x0FE0C000
152#define CB_CF_CCR_ADDR (CB_CF_BASE+0x200)
153#define CB_CF_CCR (*(volatile u8 *)CB_CF_CCR_ADDR)
154#define CB_CF_REG0_ADDR (CB_CF_BASE+0x1000)
155#define CB_CF_REG0 (*(volatile u16 *)CB_CF_REG0_ADDR)
156#define CB_CF_STS0_ADDR (CB_CF_BASE+0x1004)
157#define CB_CF_STS0 (*(volatile u16 *)CB_CF_STS0_ADDR)
158#define CB_PCATA_BASE (CB_CF_BASE+0x800)
159#define CB_IDE_BASE (CB_CF_BASE+0x9F0)
160#define CB_IDE_CTRL (CB_CF_BASE+0xBF6)
161#define CB_IDE_REG_OFFS 0x1
162
163
164/* SMSC LAN91C111 setting */
165#if defined(CONFIG_SMC91111)
166#define CB_LANC_BASE 0x0FE10300
167#define CONFIG_SMC16BITONLY
168#define ETH0_ADDR CB_LANC_BASE
169#define ETH0_IRQ IRQ_CB_LANC
170#endif /* CONFIG_SMC16BITONLY */
171
172
173#undef V850E_UART_PRE_CONFIGURE
174#define V850E_UART_PRE_CONFIGURE rte_me2_cb_uart_pre_configure
175#ifndef __ASSEMBLY__
176extern void rte_me2_cb_uart_pre_configure (unsigned chan,
177 unsigned cflags, unsigned baud);
178#endif /* __ASSEMBLY__ */
179
180/* This board supports RTS/CTS for the on-chip UART, but only for channel 0. */
181
182/* CTS for UART channel 0 is pin P22 (bit 2 of port 2). */
183#define V850E_UART_CTS(chan) ((chan) == 0 ? !(ME2_PORT2_IO & 0x4) : 1)
184/* RTS for UART channel 0 is pin P21 (bit 1 of port 2). */
185#define V850E_UART_SET_RTS(chan, val) \
186 do { \
187 if (chan == 0) { \
188 unsigned old = ME2_PORT2_IO; \
189 if (val) \
190 ME2_PORT2_IO = old & ~0x2; \
191 else \
192 ME2_PORT2_IO = old | 0x2; \
193 } \
194 } while (0)
195
196
197#ifndef __ASSEMBLY__
198extern void rte_me2_cb_init_irqs (void);
199#endif /* !__ASSEMBLY__ */
200
201
202#endif /* __V850_RTE_ME2_CB_H__ */