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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*
2 * PowerPC memory management structures
3 */
4
5#ifdef __KERNEL__
6#ifndef _PPC_MMU_H_
7#define _PPC_MMU_H_
8
9#include <linux/config.h>
10
11#ifndef __ASSEMBLY__
12
13/*
14 * Define physical address type. Machines using split size
15 * virtual/physical addressing like 32-bit virtual / 36-bit
16 * physical need a larger than native word size type. -Matt
17 */
18#ifndef CONFIG_PTE_64BIT
19typedef unsigned long phys_addr_t;
20#else
21typedef unsigned long long phys_addr_t;
22extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
23#endif
24
25/* Default "unsigned long" context */
26typedef unsigned long mm_context_t;
27
28/* Hardware Page Table Entry */
29typedef struct _PTE {
30#ifdef CONFIG_PPC64BRIDGE
31 unsigned long long vsid:52;
32 unsigned long api:5;
33 unsigned long :5;
34 unsigned long h:1;
35 unsigned long v:1;
36 unsigned long long rpn:52;
37#else /* CONFIG_PPC64BRIDGE */
38 unsigned long v:1; /* Entry is valid */
39 unsigned long vsid:24; /* Virtual segment identifier */
40 unsigned long h:1; /* Hash algorithm indicator */
41 unsigned long api:6; /* Abbreviated page index */
42 unsigned long rpn:20; /* Real (physical) page number */
43#endif /* CONFIG_PPC64BRIDGE */
44 unsigned long :3; /* Unused */
45 unsigned long r:1; /* Referenced */
46 unsigned long c:1; /* Changed */
47 unsigned long w:1; /* Write-thru cache mode */
48 unsigned long i:1; /* Cache inhibited */
49 unsigned long m:1; /* Memory coherence */
50 unsigned long g:1; /* Guarded */
51 unsigned long :1; /* Unused */
52 unsigned long pp:2; /* Page protection */
53} PTE;
54
55/* Values for PP (assumes Ks=0, Kp=1) */
56#define PP_RWXX 0 /* Supervisor read/write, User none */
57#define PP_RWRX 1 /* Supervisor read/write, User read */
58#define PP_RWRW 2 /* Supervisor read/write, User read/write */
59#define PP_RXRX 3 /* Supervisor read, User read */
60
61/* Segment Register */
62typedef struct _SEGREG {
63 unsigned long t:1; /* Normal or I/O type */
64 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
65 unsigned long kp:1; /* User 'key' (normally 1) */
66 unsigned long n:1; /* No-execute */
67 unsigned long :4; /* Unused */
68 unsigned long vsid:24; /* Virtual Segment Identifier */
69} SEGREG;
70
71/* Block Address Translation (BAT) Registers */
72typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
73 unsigned long bepi:15; /* Effective page index (virtual address) */
74 unsigned long :8; /* unused */
75 unsigned long w:1;
76 unsigned long i:1; /* Cache inhibit */
77 unsigned long m:1; /* Memory coherence */
78 unsigned long ks:1; /* Supervisor key (normally 0) */
79 unsigned long kp:1; /* User key (normally 1) */
80 unsigned long pp:2; /* Page access protections */
81} P601_BATU;
82
83typedef struct _BATU { /* Upper part of BAT (all except 601) */
84#ifdef CONFIG_PPC64BRIDGE
85 unsigned long long bepi:47;
86#else /* CONFIG_PPC64BRIDGE */
87 unsigned long bepi:15; /* Effective page index (virtual address) */
88#endif /* CONFIG_PPC64BRIDGE */
89 unsigned long :4; /* Unused */
90 unsigned long bl:11; /* Block size mask */
91 unsigned long vs:1; /* Supervisor valid */
92 unsigned long vp:1; /* User valid */
93} BATU;
94
95typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
96 unsigned long brpn:15; /* Real page index (physical address) */
97 unsigned long :10; /* Unused */
98 unsigned long v:1; /* Valid bit */
99 unsigned long bl:6; /* Block size mask */
100} P601_BATL;
101
102typedef struct _BATL { /* Lower part of BAT (all except 601) */
103#ifdef CONFIG_PPC64BRIDGE
104 unsigned long long brpn:47;
105#else /* CONFIG_PPC64BRIDGE */
106 unsigned long brpn:15; /* Real page index (physical address) */
107#endif /* CONFIG_PPC64BRIDGE */
108 unsigned long :10; /* Unused */
109 unsigned long w:1; /* Write-thru cache */
110 unsigned long i:1; /* Cache inhibit */
111 unsigned long m:1; /* Memory coherence */
112 unsigned long g:1; /* Guarded (MBZ in IBAT) */
113 unsigned long :1; /* Unused */
114 unsigned long pp:2; /* Page access protections */
115} BATL;
116
117typedef struct _BAT {
118 BATU batu; /* Upper register */
119 BATL batl; /* Lower register */
120} BAT;
121
122typedef struct _P601_BAT {
123 P601_BATU batu; /* Upper register */
124 P601_BATL batl; /* Lower register */
125} P601_BAT;
126
127#endif /* __ASSEMBLY__ */
128
129/* Block size masks */
130#define BL_128K 0x000
131#define BL_256K 0x001
132#define BL_512K 0x003
133#define BL_1M 0x007
134#define BL_2M 0x00F
135#define BL_4M 0x01F
136#define BL_8M 0x03F
137#define BL_16M 0x07F
138#define BL_32M 0x0FF
139#define BL_64M 0x1FF
140#define BL_128M 0x3FF
141#define BL_256M 0x7FF
142
143/* BAT Access Protection */
144#define BPP_XX 0x00 /* No access */
145#define BPP_RX 0x01 /* Read only */
146#define BPP_RW 0x02 /* Read/write */
147
148/* Control/status registers for the MPC8xx.
149 * A write operation to these registers causes serialized access.
150 * During software tablewalk, the registers used perform mask/shift-add
151 * operations when written/read. A TLB entry is created when the Mx_RPN
152 * is written, and the contents of several registers are used to
153 * create the entry.
154 */
155#define SPRN_MI_CTR 784 /* Instruction TLB control register */
156#define MI_GPM 0x80000000 /* Set domain manager mode */
157#define MI_PPM 0x40000000 /* Set subpage protection */
158#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
159#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
160#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
161#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
162#define MI_RESETVAL 0x00000000 /* Value of register at reset */
163
164/* These are the Ks and Kp from the PowerPC books. For proper operation,
165 * Ks = 0, Kp = 1.
166 */
167#define SPRN_MI_AP 786
168#define MI_Ks 0x80000000 /* Should not be set */
169#define MI_Kp 0x40000000 /* Should always be set */
170
171/* The effective page number register. When read, contains the information
172 * about the last instruction TLB miss. When MI_RPN is written, bits in
173 * this register are used to create the TLB entry.
174 */
175#define SPRN_MI_EPN 787
176#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
177#define MI_EVALID 0x00000200 /* Entry is valid */
178#define MI_ASIDMASK 0x0000000f /* ASID match value */
179 /* Reset value is undefined */
180
181/* A "level 1" or "segment" or whatever you want to call it register.
182 * For the instruction TLB, it contains bits that get loaded into the
183 * TLB entry when the MI_RPN is written.
184 */
185#define SPRN_MI_TWC 789
186#define MI_APG 0x000001e0 /* Access protection group (0) */
187#define MI_GUARDED 0x00000010 /* Guarded storage */
188#define MI_PSMASK 0x0000000c /* Mask of page size bits */
189#define MI_PS8MEG 0x0000000c /* 8M page size */
190#define MI_PS512K 0x00000004 /* 512K page size */
191#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
192#define MI_SVALID 0x00000001 /* Segment entry is valid */
193 /* Reset value is undefined */
194
195/* Real page number. Defined by the pte. Writing this register
196 * causes a TLB entry to be created for the instruction TLB, using
197 * additional information from the MI_EPN, and MI_TWC registers.
198 */
199#define SPRN_MI_RPN 790
200
201/* Define an RPN value for mapping kernel memory to large virtual
202 * pages for boot initialization. This has real page number of 0,
203 * large page size, shared page, cache enabled, and valid.
204 * Also mark all subpages valid and write access.
205 */
206#define MI_BOOTINIT 0x000001fd
207
208#define SPRN_MD_CTR 792 /* Data TLB control register */
209#define MD_GPM 0x80000000 /* Set domain manager mode */
210#define MD_PPM 0x40000000 /* Set subpage protection */
211#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
212#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
213#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
214#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
215#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
216#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
217#define MD_RESETVAL 0x04000000 /* Value of register at reset */
218
219#define SPRN_M_CASID 793 /* Address space ID (context) to match */
220#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
221
222
223/* These are the Ks and Kp from the PowerPC books. For proper operation,
224 * Ks = 0, Kp = 1.
225 */
226#define SPRN_MD_AP 794
227#define MD_Ks 0x80000000 /* Should not be set */
228#define MD_Kp 0x40000000 /* Should always be set */
229
230/* The effective page number register. When read, contains the information
231 * about the last instruction TLB miss. When MD_RPN is written, bits in
232 * this register are used to create the TLB entry.
233 */
234#define SPRN_MD_EPN 795
235#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
236#define MD_EVALID 0x00000200 /* Entry is valid */
237#define MD_ASIDMASK 0x0000000f /* ASID match value */
238 /* Reset value is undefined */
239
240/* The pointer to the base address of the first level page table.
241 * During a software tablewalk, reading this register provides the address
242 * of the entry associated with MD_EPN.
243 */
244#define SPRN_M_TWB 796
245#define M_L1TB 0xfffff000 /* Level 1 table base address */
246#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
247 /* Reset value is undefined */
248
249/* A "level 1" or "segment" or whatever you want to call it register.
250 * For the data TLB, it contains bits that get loaded into the TLB entry
251 * when the MD_RPN is written. It is also provides the hardware assist
252 * for finding the PTE address during software tablewalk.
253 */
254#define SPRN_MD_TWC 797
255#define MD_L2TB 0xfffff000 /* Level 2 table base address */
256#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
257#define MD_APG 0x000001e0 /* Access protection group (0) */
258#define MD_GUARDED 0x00000010 /* Guarded storage */
259#define MD_PSMASK 0x0000000c /* Mask of page size bits */
260#define MD_PS8MEG 0x0000000c /* 8M page size */
261#define MD_PS512K 0x00000004 /* 512K page size */
262#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
263#define MD_WT 0x00000002 /* Use writethrough page attribute */
264#define MD_SVALID 0x00000001 /* Segment entry is valid */
265 /* Reset value is undefined */
266
267
268/* Real page number. Defined by the pte. Writing this register
269 * causes a TLB entry to be created for the data TLB, using
270 * additional information from the MD_EPN, and MD_TWC registers.
271 */
272#define SPRN_MD_RPN 798
273
274/* This is a temporary storage register that could be used to save
275 * a processor working register during a tablewalk.
276 */
277#define SPRN_M_TW 799
278
279/*
280 * At present, all PowerPC 400-class processors share a similar TLB
281 * architecture. The instruction and data sides share a unified,
282 * 64-entry, fully-associative TLB which is maintained totally under
283 * software control. In addition, the instruction side has a
284 * hardware-managed, 4-entry, fully- associative TLB which serves as a
285 * first level to the shared TLB. These two TLBs are known as the UTLB
286 * and ITLB, respectively.
287 */
288
289#define PPC4XX_TLB_SIZE 64
290
291/*
292 * TLB entries are defined by a "high" tag portion and a "low" data
293 * portion. On all architectures, the data portion is 32-bits.
294 *
295 * TLB entries are managed entirely under software control by reading,
296 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
297 * instructions.
298 */
299
300#define TLB_LO 1
301#define TLB_HI 0
302
303#define TLB_DATA TLB_LO
304#define TLB_TAG TLB_HI
305
306/* Tag portion */
307
308#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
309#define TLB_PAGESZ_MASK 0x00000380
310#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
311#define PAGESZ_1K 0
312#define PAGESZ_4K 1
313#define PAGESZ_16K 2
314#define PAGESZ_64K 3
315#define PAGESZ_256K 4
316#define PAGESZ_1M 5
317#define PAGESZ_4M 6
318#define PAGESZ_16M 7
319#define TLB_VALID 0x00000040 /* Entry is valid */
320
321/* Data portion */
322
323#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
324#define TLB_PERM_MASK 0x00000300
325#define TLB_EX 0x00000200 /* Instruction execution allowed */
326#define TLB_WR 0x00000100 /* Writes permitted */
327#define TLB_ZSEL_MASK 0x000000F0
328#define TLB_ZSEL(x) (((x) & 0xF) << 4)
329#define TLB_ATTR_MASK 0x0000000F
330#define TLB_W 0x00000008 /* Caching is write-through */
331#define TLB_I 0x00000004 /* Caching is inhibited */
332#define TLB_M 0x00000002 /* Memory is coherent */
333#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
334
335/*
336 * PPC440 support
337 */
338#define PPC44x_MMUCR_TID 0x000000ff
339#define PPC44x_MMUCR_STS 0x00010000
340
341#define PPC44x_TLB_PAGEID 0
342#define PPC44x_TLB_XLAT 1
343#define PPC44x_TLB_ATTRIB 2
344
345/* Page identification fields */
346#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
347#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
348#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
349#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
350#define PPC44x_TLB_4K 0x00000010
351#define PPC44x_TLB_16K 0x00000020
352#define PPC44x_TLB_64K 0x00000030
353#define PPC44x_TLB_256K 0x00000040
354#define PPC44x_TLB_1M 0x00000050
355#define PPC44x_TLB_16M 0x00000070
356#define PPC44x_TLB_256M 0x00000090
357
358/* Translation fields */
359#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
360#define PPC44x_TLB_ERPN_MASK 0x0000000f
361
362/* Storage attribute and access control fields */
363#define PPC44x_TLB_ATTR_MASK 0x0000ff80
364#define PPC44x_TLB_U0 0x00008000 /* User 0 */
365#define PPC44x_TLB_U1 0x00004000 /* User 1 */
366#define PPC44x_TLB_U2 0x00002000 /* User 2 */
367#define PPC44x_TLB_U3 0x00001000 /* User 3 */
368#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
369#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
370#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
371#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
372#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
373
374#define PPC44x_TLB_PERM_MASK 0x0000003f
375#define PPC44x_TLB_UX 0x00000020 /* User execution */
376#define PPC44x_TLB_UW 0x00000010 /* User write */
377#define PPC44x_TLB_UR 0x00000008 /* User read */
378#define PPC44x_TLB_SX 0x00000004 /* Super execution */
379#define PPC44x_TLB_SW 0x00000002 /* Super write */
380#define PPC44x_TLB_SR 0x00000001 /* Super read */
381
382/* Book-E defined page sizes */
383#define BOOKE_PAGESZ_1K 0
384#define BOOKE_PAGESZ_4K 1
385#define BOOKE_PAGESZ_16K 2
386#define BOOKE_PAGESZ_64K 3
387#define BOOKE_PAGESZ_256K 4
388#define BOOKE_PAGESZ_1M 5
389#define BOOKE_PAGESZ_4M 6
390#define BOOKE_PAGESZ_16M 7
391#define BOOKE_PAGESZ_64M 8
392#define BOOKE_PAGESZ_256M 9
393#define BOOKE_PAGESZ_1GB 10
394#define BOOKE_PAGESZ_4GB 11
395#define BOOKE_PAGESZ_16GB 12
396#define BOOKE_PAGESZ_64GB 13
397#define BOOKE_PAGESZ_256GB 14
398#define BOOKE_PAGESZ_1TB 15
399
400/*
401 * Freescale Book-E MMU support
402 */
403
404#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
405#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
406#define MAS0_NV 0x00000FFF
407
408#define MAS1_VALID 0x80000000
409#define MAS1_IPROT 0x40000000
410#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
411#define MAS1_TS 0x00001000
412#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
413
414#define MAS2_EPN 0xFFFFF000
415#define MAS2_X0 0x00000040
416#define MAS2_X1 0x00000020
417#define MAS2_W 0x00000010
418#define MAS2_I 0x00000008
419#define MAS2_M 0x00000004
420#define MAS2_G 0x00000002
421#define MAS2_E 0x00000001
422
423#define MAS3_RPN 0xFFFFF000
424#define MAS3_U0 0x00000200
425#define MAS3_U1 0x00000100
426#define MAS3_U2 0x00000080
427#define MAS3_U3 0x00000040
428#define MAS3_UX 0x00000020
429#define MAS3_SX 0x00000010
430#define MAS3_UW 0x00000008
431#define MAS3_SW 0x00000004
432#define MAS3_UR 0x00000002
433#define MAS3_SR 0x00000001
434
435#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
436#define MAS4_TIDDSEL 0x000F0000
437#define MAS4_TSIZED(x) MAS1_TSIZE(x)
438#define MAS4_X0D 0x00000040
439#define MAS4_X1D 0x00000020
440#define MAS4_WD 0x00000010
441#define MAS4_ID 0x00000008
442#define MAS4_MD 0x00000004
443#define MAS4_GD 0x00000002
444#define MAS4_ED 0x00000001
445
446#define MAS6_SPID0 0x3FFF0000
447#define MAS6_SPID1 0x00007FFE
448#define MAS6_SAS 0x00000001
449#define MAS6_SPID MAS6_SPID0
450
451#define MAS7_RPN 0xFFFFFFFF
452
453#endif /* _PPC_MMU_H_ */
454#endif /* __KERNEL__ */