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Linux kernel mirror (for testing)
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kernel
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linux
1#ifndef _I915_DRM_H_
2#define _I915_DRM_H_
3
4/* Please note that modifications to all structs defined here are
5 * subject to backwards-compatibility constraints.
6 */
7
8#include "drm.h"
9
10/* Each region is a minimum of 16k, and there are at most 255 of them.
11 */
12#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
13 * of chars for next/prev indices */
14#define I915_LOG_MIN_TEX_REGION_SIZE 14
15
16typedef struct _drm_i915_init {
17 enum {
18 I915_INIT_DMA = 0x01,
19 I915_CLEANUP_DMA = 0x02,
20 I915_RESUME_DMA = 0x03
21 } func;
22 unsigned int mmio_offset;
23 int sarea_priv_offset;
24 unsigned int ring_start;
25 unsigned int ring_end;
26 unsigned int ring_size;
27 unsigned int front_offset;
28 unsigned int back_offset;
29 unsigned int depth_offset;
30 unsigned int w;
31 unsigned int h;
32 unsigned int pitch;
33 unsigned int pitch_bits;
34 unsigned int back_pitch;
35 unsigned int depth_pitch;
36 unsigned int cpp;
37 unsigned int chipset;
38} drm_i915_init_t;
39
40typedef struct _drm_i915_sarea {
41 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
42 int last_upload; /* last time texture was uploaded */
43 int last_enqueue; /* last time a buffer was enqueued */
44 int last_dispatch; /* age of the most recently dispatched buffer */
45 int ctxOwner; /* last context to upload state */
46 int texAge;
47 int pf_enabled; /* is pageflipping allowed? */
48 int pf_active;
49 int pf_current_page; /* which buffer is being displayed? */
50 int perf_boxes; /* performance boxes to be displayed */
51} drm_i915_sarea_t;
52
53/* Flags for perf_boxes
54 */
55#define I915_BOX_RING_EMPTY 0x1
56#define I915_BOX_FLIP 0x2
57#define I915_BOX_WAIT 0x4
58#define I915_BOX_TEXTURE_LOAD 0x8
59#define I915_BOX_LOST_CONTEXT 0x10
60
61/* I915 specific ioctls
62 * The device specific ioctl range is 0x40 to 0x79.
63 */
64#define DRM_I915_INIT 0x00
65#define DRM_I915_FLUSH 0x01
66#define DRM_I915_FLIP 0x02
67#define DRM_I915_BATCHBUFFER 0x03
68#define DRM_I915_IRQ_EMIT 0x04
69#define DRM_I915_IRQ_WAIT 0x05
70#define DRM_I915_GETPARAM 0x06
71#define DRM_I915_SETPARAM 0x07
72#define DRM_I915_ALLOC 0x08
73#define DRM_I915_FREE 0x09
74#define DRM_I915_INIT_HEAP 0x0a
75#define DRM_I915_CMDBUFFER 0x0b
76
77#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
78#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
79#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
80#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
81#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
82#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
83#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
84#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
85#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
86#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
87#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
88#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
89
90/* Allow drivers to submit batchbuffers directly to hardware, relying
91 * on the security mechanisms provided by hardware.
92 */
93typedef struct _drm_i915_batchbuffer {
94 int start; /* agp offset */
95 int used; /* nr bytes in use */
96 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
97 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
98 int num_cliprects; /* mulitpass with multiple cliprects? */
99 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
100} drm_i915_batchbuffer_t;
101
102/* As above, but pass a pointer to userspace buffer which can be
103 * validated by the kernel prior to sending to hardware.
104 */
105typedef struct _drm_i915_cmdbuffer {
106 char __user *buf; /* pointer to userspace command buffer */
107 int sz; /* nr bytes in buf */
108 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
109 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
110 int num_cliprects; /* mulitpass with multiple cliprects? */
111 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
112} drm_i915_cmdbuffer_t;
113
114/* Userspace can request & wait on irq's:
115 */
116typedef struct drm_i915_irq_emit {
117 int __user *irq_seq;
118} drm_i915_irq_emit_t;
119
120typedef struct drm_i915_irq_wait {
121 int irq_seq;
122} drm_i915_irq_wait_t;
123
124/* Ioctl to query kernel params:
125 */
126#define I915_PARAM_IRQ_ACTIVE 1
127#define I915_PARAM_ALLOW_BATCHBUFFER 2
128
129typedef struct drm_i915_getparam {
130 int param;
131 int __user *value;
132} drm_i915_getparam_t;
133
134/* Ioctl to set kernel params:
135 */
136#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
137#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
138#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
139
140typedef struct drm_i915_setparam {
141 int param;
142 int value;
143} drm_i915_setparam_t;
144
145/* A memory manager for regions of shared memory:
146 */
147#define I915_MEM_REGION_AGP 1
148
149typedef struct drm_i915_mem_alloc {
150 int region;
151 int alignment;
152 int size;
153 int __user *region_offset; /* offset from start of fb or agp */
154} drm_i915_mem_alloc_t;
155
156typedef struct drm_i915_mem_free {
157 int region;
158 int region_offset;
159} drm_i915_mem_free_t;
160
161typedef struct drm_i915_mem_init_heap {
162 int region;
163 int size;
164 int start;
165} drm_i915_mem_init_heap_t;
166
167#endif /* _I915_DRM_H_ */