tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
4#define __SOC_MEDIATEK_MT8192_MMSYS_H
5
6#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
7#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
8#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
9#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
10#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
11#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
12#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
13#define MT8192_DISP_AAL0_SEL_IN 0xf38
14#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
15#define MT8192_DISP_DSI0_SEL_IN 0xf40
16#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
17
18#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
19#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
20#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
21#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
22#define MT8192_DISP_OVL0_GO_BG BIT(1)
23#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
24#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
25#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
26#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
27#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
28#define MT8192_RDMA0_SOUT_COLOR0 0x1
29#define MT8192_CCORR0_SOUT_AAL0 0x1
30#define MT8192_AAL0_SEL_IN_CCORR0 0x1
31#define MT8192_DSI0_SEL_IN_DITHER0 0x1
32
33static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
34 MMSYS_ROUTE(OVL_2L0, RDMA0,
35 MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
36 MT8192_OVL0_MOUT_EN_DISP_RDMA0),
37 MMSYS_ROUTE(OVL_2L2, RDMA4,
38 MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
39 MT8192_OVL2_2L_MOUT_EN_RDMA4),
40 MMSYS_ROUTE(DITHER0, DSI0,
41 MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
42 MT8192_DITHER0_MOUT_IN_DSI0),
43 MMSYS_ROUTE(OVL_2L0, RDMA0,
44 MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
45 MT8192_RDMA0_SEL_IN_OVL0_2L),
46 MMSYS_ROUTE(CCORR, AAL0,
47 MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
48 MT8192_AAL0_SEL_IN_CCORR0),
49 MMSYS_ROUTE(DITHER0, DSI0,
50 MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
51 MT8192_DSI0_SEL_IN_DITHER0),
52 MMSYS_ROUTE(RDMA0, COLOR0,
53 MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
54 MT8192_RDMA0_SOUT_COLOR0),
55 MMSYS_ROUTE(CCORR, AAL0,
56 MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
57 MT8192_CCORR0_SOUT_AAL0),
58 MMSYS_ROUTE(OVL0, OVL_2L0,
59 MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
60 MT8192_DISP_OVL0_GO_BG),
61 MMSYS_ROUTE(OVL_2L0, RDMA0,
62 MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
63 MT8192_DISP_OVL0_2L_GO_BLEND),
64};
65
66#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */