tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * omap iommu: main structures
4 *
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 */
9
10#ifndef _OMAP_IOMMU_H
11#define _OMAP_IOMMU_H
12
13#include <linux/bitops.h>
14#include <linux/iommu.h>
15
16#define for_each_iotlb_cr(obj, n, __i, cr) \
17 for (__i = 0; \
18 (__i < (n)) && (cr = __iotlb_read_cr((obj), __i), true); \
19 __i++)
20
21struct iotlb_entry {
22 u32 da;
23 u32 pa;
24 u32 pgsz, prsvd, valid;
25 u32 endian, elsz, mixed;
26};
27
28/**
29 * struct omap_iommu_device - omap iommu device data
30 * @pgtable: page table used by an omap iommu attached to a domain
31 * @iommu_dev: pointer to store an omap iommu instance attached to a domain
32 */
33struct omap_iommu_device {
34 u32 *pgtable;
35 struct omap_iommu *iommu_dev;
36};
37
38/**
39 * struct omap_iommu_domain - omap iommu domain
40 * @num_iommus: number of iommus in this domain
41 * @iommus: omap iommu device data for all iommus in this domain
42 * @dev: Device using this domain.
43 * @lock: domain lock, should be taken when attaching/detaching
44 * @domain: generic domain handle used by iommu core code
45 */
46struct omap_iommu_domain {
47 u32 num_iommus;
48 struct omap_iommu_device *iommus;
49 struct device *dev;
50 spinlock_t lock;
51 struct iommu_domain domain;
52};
53
54struct omap_iommu {
55 const char *name;
56 void __iomem *regbase;
57 struct regmap *syscfg;
58 struct device *dev;
59 struct iommu_domain *domain;
60 struct dentry *debug_dir;
61
62 spinlock_t iommu_lock; /* global for this whole object */
63
64 /*
65 * We don't change iopgd for a situation like pgd for a task,
66 * but share it globally for each iommu.
67 */
68 u32 *iopgd;
69 spinlock_t page_table_lock; /* protect iopgd */
70 dma_addr_t pd_dma;
71
72 int nr_tlb_entries;
73
74 void *ctx; /* iommu context: registres saved area */
75
76 struct cr_regs *cr_ctx;
77 u32 num_cr_ctx;
78
79 int has_bus_err_back;
80 u32 id;
81
82 struct iommu_device iommu;
83 bool has_iommu_driver;
84
85 u8 pwrst;
86};
87
88/**
89 * struct omap_iommu_arch_data - omap iommu private data
90 * @iommu_dev: handle of the OMAP iommu device
91 *
92 * This is an omap iommu private data object, which binds an iommu user
93 * to its iommu device. This object should be placed at the iommu user's
94 * dev_archdata so generic IOMMU API can be used without having to
95 * utilize omap-specific plumbing anymore.
96 */
97struct omap_iommu_arch_data {
98 struct omap_iommu *iommu_dev;
99};
100
101struct cr_regs {
102 u32 cam;
103 u32 ram;
104};
105
106struct iotlb_lock {
107 short base;
108 short vict;
109};
110
111/*
112 * MMU Register offsets
113 */
114#define MMU_REVISION 0x00
115#define MMU_IRQSTATUS 0x18
116#define MMU_IRQENABLE 0x1c
117#define MMU_WALKING_ST 0x40
118#define MMU_CNTL 0x44
119#define MMU_FAULT_AD 0x48
120#define MMU_TTB 0x4c
121#define MMU_LOCK 0x50
122#define MMU_LD_TLB 0x54
123#define MMU_CAM 0x58
124#define MMU_RAM 0x5c
125#define MMU_GFLUSH 0x60
126#define MMU_FLUSH_ENTRY 0x64
127#define MMU_READ_CAM 0x68
128#define MMU_READ_RAM 0x6c
129#define MMU_EMU_FAULT_AD 0x70
130#define MMU_GP_REG 0x88
131
132#define MMU_REG_SIZE 256
133
134/*
135 * MMU Register bit definitions
136 */
137/* IRQSTATUS & IRQENABLE */
138#define MMU_IRQ_MULTIHITFAULT BIT(4)
139#define MMU_IRQ_TABLEWALKFAULT BIT(3)
140#define MMU_IRQ_EMUMISS BIT(2)
141#define MMU_IRQ_TRANSLATIONFAULT BIT(1)
142#define MMU_IRQ_TLBMISS BIT(0)
143
144#define __MMU_IRQ_FAULT \
145 (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
146#define MMU_IRQ_MASK \
147 (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
148#define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
149#define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
150
151/* MMU_CNTL */
152#define MMU_CNTL_SHIFT 1
153#define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
154#define MMU_CNTL_EML_TLB BIT(3)
155#define MMU_CNTL_TWL_EN BIT(2)
156#define MMU_CNTL_MMU_EN BIT(1)
157
158/* CAM */
159#define MMU_CAM_VATAG_SHIFT 12
160#define MMU_CAM_VATAG_MASK \
161 ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
162#define MMU_CAM_P BIT(3)
163#define MMU_CAM_V BIT(2)
164#define MMU_CAM_PGSZ_MASK 3
165#define MMU_CAM_PGSZ_1M (0 << 0)
166#define MMU_CAM_PGSZ_64K (1 << 0)
167#define MMU_CAM_PGSZ_4K (2 << 0)
168#define MMU_CAM_PGSZ_16M (3 << 0)
169
170/* RAM */
171#define MMU_RAM_PADDR_SHIFT 12
172#define MMU_RAM_PADDR_MASK \
173 ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
174
175#define MMU_RAM_ENDIAN_SHIFT 9
176#define MMU_RAM_ENDIAN_MASK BIT(MMU_RAM_ENDIAN_SHIFT)
177#define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
178#define MMU_RAM_ENDIAN_BIG BIT(MMU_RAM_ENDIAN_SHIFT)
179
180#define MMU_RAM_ELSZ_SHIFT 7
181#define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
182#define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
183#define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
184#define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
185#define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
186#define MMU_RAM_MIXED_SHIFT 6
187#define MMU_RAM_MIXED_MASK BIT(MMU_RAM_MIXED_SHIFT)
188#define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
189
190#define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
191
192#define get_cam_va_mask(pgsz) \
193 (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
194 ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
195 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
196 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
197
198/*
199 * DSP_SYSTEM registers and bit definitions (applicable only for DRA7xx DSP)
200 */
201#define DSP_SYS_REVISION 0x00
202#define DSP_SYS_MMU_CONFIG 0x18
203#define DSP_SYS_MMU_CONFIG_EN_SHIFT 4
204
205/*
206 * utilities for super page(16MB, 1MB, 64KB and 4KB)
207 */
208
209#define iopgsz_max(bytes) \
210 (((bytes) >= SZ_16M) ? SZ_16M : \
211 ((bytes) >= SZ_1M) ? SZ_1M : \
212 ((bytes) >= SZ_64K) ? SZ_64K : \
213 ((bytes) >= SZ_4K) ? SZ_4K : 0)
214
215#define bytes_to_iopgsz(bytes) \
216 (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
217 ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
218 ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
219 ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
220
221#define iopgsz_to_bytes(iopgsz) \
222 (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
223 ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
224 ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
225 ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
226
227#define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
228
229/*
230 * global functions
231 */
232
233struct cr_regs __iotlb_read_cr(struct omap_iommu *obj, int n);
234void iotlb_lock_get(struct omap_iommu *obj, struct iotlb_lock *l);
235void iotlb_lock_set(struct omap_iommu *obj, struct iotlb_lock *l);
236
237#ifdef CONFIG_OMAP_IOMMU_DEBUG
238void omap_iommu_debugfs_init(void);
239void omap_iommu_debugfs_exit(void);
240
241void omap_iommu_debugfs_add(struct omap_iommu *obj);
242void omap_iommu_debugfs_remove(struct omap_iommu *obj);
243#else
244static inline void omap_iommu_debugfs_init(void) { }
245static inline void omap_iommu_debugfs_exit(void) { }
246
247static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
248static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
249#endif
250
251/*
252 * register accessors
253 */
254static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
255{
256 return __raw_readl(obj->regbase + offs);
257}
258
259static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
260{
261 __raw_writel(val, obj->regbase + offs);
262}
263
264static inline int iotlb_cr_valid(struct cr_regs *cr)
265{
266 if (!cr)
267 return -EINVAL;
268
269 return cr->cam & MMU_CAM_V;
270}
271
272#endif /* _OMAP_IOMMU_H */