tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Garmin Chang <garmin.chang@mediatek.com>
5 */
6
7#include <dt-bindings/clock/mediatek,mt8188-clk.h>
8#include <linux/clk-provider.h>
9#include <linux/platform_device.h>
10
11#include "clk-gate.h"
12#include "clk-mtk.h"
13
14static const struct mtk_gate_regs imgsys_cg_regs = {
15 .set_ofs = 0x4,
16 .clr_ofs = 0x8,
17 .sta_ofs = 0x0,
18};
19
20#define GATE_IMGSYS(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &imgsys_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
22
23#define IMG_SYS_SMI_LARB_RST_OFF (0xC)
24
25static const struct mtk_gate imgsys_main_clks[] = {
26 GATE_IMGSYS(CLK_IMGSYS_MAIN_LARB9, "imgsys_main_larb9", "top_img", 0),
27 GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW0, "imgsys_main_traw0", "top_img", 1),
28 GATE_IMGSYS(CLK_IMGSYS_MAIN_TRAW1, "imgsys_main_traw1", "top_img", 2),
29 GATE_IMGSYS(CLK_IMGSYS_MAIN_VCORE_GALS, "imgsys_main_vcore_gals", "top_img", 3),
30 GATE_IMGSYS(CLK_IMGSYS_MAIN_DIP0, "imgsys_main_dip0", "top_img", 8),
31 GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE0, "imgsys_main_wpe0", "top_img", 9),
32 GATE_IMGSYS(CLK_IMGSYS_MAIN_IPE, "imgsys_main_ipe", "top_img", 10),
33 GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE1, "imgsys_main_wpe1", "top_img", 12),
34 GATE_IMGSYS(CLK_IMGSYS_MAIN_WPE2, "imgsys_main_wpe2", "top_img", 13),
35 GATE_IMGSYS(CLK_IMGSYS_MAIN_GALS, "imgsys_main_gals", "top_img", 31),
36};
37
38static const struct mtk_gate imgsys_wpe1_clks[] = {
39 GATE_IMGSYS(CLK_IMGSYS_WPE1_LARB11, "imgsys_wpe1_larb11", "top_img", 0),
40 GATE_IMGSYS(CLK_IMGSYS_WPE1, "imgsys_wpe1", "top_img", 1),
41};
42
43static const struct mtk_gate imgsys_wpe2_clks[] = {
44 GATE_IMGSYS(CLK_IMGSYS_WPE2_LARB11, "imgsys_wpe2_larb11", "top_img", 0),
45 GATE_IMGSYS(CLK_IMGSYS_WPE2, "imgsys_wpe2", "top_img", 1),
46};
47
48static const struct mtk_gate imgsys_wpe3_clks[] = {
49 GATE_IMGSYS(CLK_IMGSYS_WPE3_LARB11, "imgsys_wpe3_larb11", "top_img", 0),
50 GATE_IMGSYS(CLK_IMGSYS_WPE3, "imgsys_wpe3", "top_img", 1),
51};
52
53static const struct mtk_gate imgsys1_dip_top_clks[] = {
54 GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_LARB10, "imgsys1_dip_larb10", "top_img", 0),
55 GATE_IMGSYS(CLK_IMGSYS1_DIP_TOP_DIP_TOP, "imgsys1_dip_dip_top", "top_img", 1),
56};
57
58static const struct mtk_gate imgsys1_dip_nr_clks[] = {
59 GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_LARB15, "imgsys1_dip_nr_larb15", "top_img", 0),
60 GATE_IMGSYS(CLK_IMGSYS1_DIP_NR_DIP_NR, "imgsys1_dip_nr_dip_nr", "top_img", 1),
61};
62
63/* Reset for SMI larb 10/11a/11b/11c/15 */
64static u16 img_sys_rst_ofs[] = {
65 IMG_SYS_SMI_LARB_RST_OFF,
66};
67
68static const struct mtk_clk_rst_desc img_sys_rst_desc = {
69 .version = MTK_RST_SIMPLE,
70 .rst_bank_ofs = img_sys_rst_ofs,
71 .rst_bank_nr = ARRAY_SIZE(img_sys_rst_ofs),
72};
73
74static const struct mtk_clk_desc imgsys_main_desc = {
75 .clks = imgsys_main_clks,
76 .num_clks = ARRAY_SIZE(imgsys_main_clks),
77};
78
79static const struct mtk_clk_desc imgsys_wpe1_desc = {
80 .clks = imgsys_wpe1_clks,
81 .num_clks = ARRAY_SIZE(imgsys_wpe1_clks),
82 .rst_desc = &img_sys_rst_desc,
83};
84
85static const struct mtk_clk_desc imgsys_wpe2_desc = {
86 .clks = imgsys_wpe2_clks,
87 .num_clks = ARRAY_SIZE(imgsys_wpe2_clks),
88 .rst_desc = &img_sys_rst_desc,
89};
90
91static const struct mtk_clk_desc imgsys_wpe3_desc = {
92 .clks = imgsys_wpe3_clks,
93 .num_clks = ARRAY_SIZE(imgsys_wpe3_clks),
94 .rst_desc = &img_sys_rst_desc,
95};
96
97static const struct mtk_clk_desc imgsys1_dip_top_desc = {
98 .clks = imgsys1_dip_top_clks,
99 .num_clks = ARRAY_SIZE(imgsys1_dip_top_clks),
100 .rst_desc = &img_sys_rst_desc,
101};
102
103static const struct mtk_clk_desc imgsys1_dip_nr_desc = {
104 .clks = imgsys1_dip_nr_clks,
105 .num_clks = ARRAY_SIZE(imgsys1_dip_nr_clks),
106 .rst_desc = &img_sys_rst_desc,
107};
108
109static const struct of_device_id of_match_clk_mt8188_imgsys_main[] = {
110 { .compatible = "mediatek,mt8188-imgsys", .data = &imgsys_main_desc },
111 { .compatible = "mediatek,mt8188-imgsys-wpe1", .data = &imgsys_wpe1_desc },
112 { .compatible = "mediatek,mt8188-imgsys-wpe2", .data = &imgsys_wpe2_desc },
113 { .compatible = "mediatek,mt8188-imgsys-wpe3", .data = &imgsys_wpe3_desc },
114 { .compatible = "mediatek,mt8188-imgsys1-dip-top", .data = &imgsys1_dip_top_desc },
115 { .compatible = "mediatek,mt8188-imgsys1-dip-nr", .data = &imgsys1_dip_nr_desc },
116 { /* sentinel */ }
117};
118MODULE_DEVICE_TABLE(of, of_match_clk_mt8188_imgsys_main);
119
120static struct platform_driver clk_mt8188_imgsys_main_drv = {
121 .probe = mtk_clk_simple_probe,
122 .remove = mtk_clk_simple_remove,
123 .driver = {
124 .name = "clk-mt8188-imgsys_main",
125 .of_match_table = of_match_clk_mt8188_imgsys_main,
126 },
127};
128module_platform_driver(clk_mt8188_imgsys_main_drv);
129
130MODULE_DESCRIPTION("MediaTek MT8188 imgsys clocks driver");
131MODULE_LICENSE("GPL");