tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: StarFive JH7100 Pin Controller
8
9description: |
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
11
12 Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63]
13 and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have
14 configurable bias, drive strength, schmitt trigger etc. The SoC has an
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
16 below.
17
18 Signal group 0, 1, ... or 6
19 ___|___
20 | |
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
24 ... | | ...
25 | |--- PAD_GPIO[63]
26 -------- GPIO0 ------------| |
27 | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0]
28 | | | | | |--- PAD_FUNC_SHARE[1]
29 | | | | ... | | ...
30 | | | | | |--- PAD_FUNC_SHARE[141]
31 | | -----|---|-- GPIO63 ---| |
32 | | | | | | -------
33 UART0 UART1 --
34
35 The big MUX in the diagram only has 7 different ways of mapping peripherals
36 on the left to pins on the right. StarFive calls the 7 configurations "signal
37 groups".
38 However some peripherals have their I/O go through the 64 "GPIOs". The
39 diagram only shows UART0 and UART1, but this also includes a number of other
40 UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
41 GPIOs such that any GPIO can be set up to be controlled by any of the
42 peripherals.
43 Note that signal group 0 doesn't map any of the GPIOs to pins, and only
44 signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63].
45
46maintainers:
47 - Emil Renner Berthing <kernel@esmil.dk>
48 - Drew Fustini <drew@beagleboard.org>
49
50properties:
51 compatible:
52 const: starfive,jh7100-pinctrl
53
54 reg:
55 minItems: 2
56 maxItems: 2
57
58 reg-names:
59 items:
60 - const: gpio
61 - const: padctl
62
63 clocks:
64 maxItems: 1
65
66 resets:
67 maxItems: 1
68
69 gpio-controller: true
70
71 "#gpio-cells":
72 const: 2
73
74 interrupts:
75 maxItems: 1
76 description: The GPIO parent interrupt.
77
78 interrupt-controller: true
79
80 "#interrupt-cells":
81 const: 2
82
83 starfive,signal-group:
84 description: |
85 Select one of the 7 signal groups. If this property is not set it
86 defaults to the configuration already chosen by the earlier boot stages.
87 $ref: /schemas/types.yaml#/definitions/uint32
88 enum: [0, 1, 2, 3, 4, 5, 6]
89
90required:
91 - compatible
92 - reg
93 - reg-names
94 - clocks
95 - gpio-controller
96 - "#gpio-cells"
97 - interrupts
98 - interrupt-controller
99 - "#interrupt-cells"
100
101patternProperties:
102 '-[0-9]+$':
103 type: object
104 patternProperties:
105 '-pins$':
106 type: object
107 description: |
108 A pinctrl node should contain at least one subnode representing the
109 pinctrl groups available on the machine. Each subnode will list the
110 pins it needs, and how they should be configured, with regard to
111 muxer configuration, bias, input enable/disable, input schmitt
112 trigger enable/disable, slew-rate and drive strength.
113 $ref: /schemas/pinctrl/pincfg-node.yaml
114
115 properties:
116 pins:
117 description: |
118 The list of pin identifiers that properties in the node apply to.
119 This should be set using either the PAD_GPIO or PAD_FUNC_SHARE
120 macros.
121 Either this or "pinmux" has to be specified, but not both.
122 $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins
123
124 pinmux:
125 description: |
126 The list of GPIOs and their mux settings that properties in the
127 node apply to. This should be set using the GPIOMUX macro.
128 Either this or "pins" has to be specified, but not both.
129 $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux
130
131 bias-disable: true
132
133 bias-pull-up:
134 type: boolean
135
136 bias-pull-down:
137 type: boolean
138
139 drive-strength:
140 enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ]
141
142 input-enable: true
143
144 input-disable: true
145
146 input-schmitt-enable: true
147
148 input-schmitt-disable: true
149
150 slew-rate:
151 maximum: 7
152
153 starfive,strong-pull-up:
154 description: enable strong pull-up.
155 type: boolean
156
157 additionalProperties: false
158
159 additionalProperties: false
160
161additionalProperties: false
162
163examples:
164 - |
165 #include <dt-bindings/clock/starfive-jh7100.h>
166 #include <dt-bindings/reset/starfive-jh7100.h>
167 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
168
169 soc {
170 #address-cells = <2>;
171 #size-cells = <2>;
172
173 pinctrl@11910000 {
174 compatible = "starfive,jh7100-pinctrl";
175 reg = <0x0 0x11910000 0x0 0x10000>,
176 <0x0 0x11858000 0x0 0x1000>;
177 reg-names = "gpio", "padctl";
178 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
179 resets = <&clkgen JH7100_RSTN_GPIO_APB>;
180 interrupts = <32>;
181 gpio-controller;
182 #gpio-cells = <2>;
183 interrupt-controller;
184 #interrupt-cells = <2>;
185 starfive,signal-group = <6>;
186
187 gmac_pins_default: gmac-0 {
188 gtxclk-pins {
189 pins = <PAD_FUNC_SHARE(115)>;
190 bias-pull-up;
191 drive-strength = <35>;
192 input-enable;
193 input-schmitt-enable;
194 slew-rate = <0>;
195 };
196 miitxclk-pins {
197 pins = <PAD_FUNC_SHARE(116)>;
198 bias-pull-up;
199 drive-strength = <14>;
200 input-enable;
201 input-schmitt-disable;
202 slew-rate = <0>;
203 };
204 tx-pins {
205 pins = <PAD_FUNC_SHARE(117)>,
206 <PAD_FUNC_SHARE(119)>,
207 <PAD_FUNC_SHARE(120)>,
208 <PAD_FUNC_SHARE(121)>,
209 <PAD_FUNC_SHARE(122)>,
210 <PAD_FUNC_SHARE(123)>,
211 <PAD_FUNC_SHARE(124)>,
212 <PAD_FUNC_SHARE(125)>,
213 <PAD_FUNC_SHARE(126)>;
214 bias-disable;
215 drive-strength = <35>;
216 input-disable;
217 input-schmitt-disable;
218 slew-rate = <0>;
219 };
220 rxclk-pins {
221 pins = <PAD_FUNC_SHARE(127)>;
222 bias-pull-up;
223 drive-strength = <14>;
224 input-enable;
225 input-schmitt-disable;
226 slew-rate = <6>;
227 };
228 rxer-pins {
229 pins = <PAD_FUNC_SHARE(129)>;
230 bias-pull-up;
231 drive-strength = <14>;
232 input-enable;
233 input-schmitt-disable;
234 slew-rate = <0>;
235 };
236 rx-pins {
237 pins = <PAD_FUNC_SHARE(128)>,
238 <PAD_FUNC_SHARE(130)>,
239 <PAD_FUNC_SHARE(131)>,
240 <PAD_FUNC_SHARE(132)>,
241 <PAD_FUNC_SHARE(133)>,
242 <PAD_FUNC_SHARE(134)>,
243 <PAD_FUNC_SHARE(135)>,
244 <PAD_FUNC_SHARE(136)>,
245 <PAD_FUNC_SHARE(137)>,
246 <PAD_FUNC_SHARE(138)>,
247 <PAD_FUNC_SHARE(139)>,
248 <PAD_FUNC_SHARE(140)>,
249 <PAD_FUNC_SHARE(141)>;
250 bias-pull-up;
251 drive-strength = <14>;
252 input-enable;
253 input-schmitt-enable;
254 slew-rate = <0>;
255 };
256 };
257
258 i2c0_pins_default: i2c0-0 {
259 i2c-pins {
260 pinmux = <GPIOMUX(62, GPO_LOW,
261 GPO_I2C0_PAD_SCK_OEN,
262 GPI_I2C0_PAD_SCK_IN)>,
263 <GPIOMUX(61, GPO_LOW,
264 GPO_I2C0_PAD_SDA_OEN,
265 GPI_I2C0_PAD_SDA_IN)>;
266 bias-disable; /* external pull-up */
267 input-enable;
268 input-schmitt-enable;
269 };
270 };
271
272 uart3_pins_default: uart3-0 {
273 rx-pins {
274 pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
275 GPI_UART3_PAD_SIN)>;
276 bias-pull-up;
277 input-enable;
278 input-schmitt-enable;
279 };
280 tx-pins {
281 pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT,
282 GPO_ENABLE, GPI_NONE)>;
283 bias-disable;
284 input-disable;
285 input-schmitt-disable;
286 };
287 };
288 };
289
290 gmac {
291 pinctrl-0 = <&gmac_pins_default>;
292 pinctrl-names = "default";
293 };
294
295 i2c {
296 pinctrl-0 = <&i2c0_pins_default>;
297 pinctrl-names = "default";
298 };
299
300 uart3 {
301 pinctrl-0 = <&uart3_pins_default>;
302 pinctrl-names = "default";
303 };
304 };
305
306...