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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Marvell Xenon SDHCI Controller
8
9description: |
10 This file documents differences between the core MMC properties described by
11 mmc-controller.yaml and the properties used by the Xenon implementation.
12
13 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
14 Each SDHC is independent and owns independent resources, such as register
15 sets, clock and PHY.
16
17 Each SDHC should have an independent device tree node.
18
19maintainers:
20 - Ulf Hansson <ulf.hansson@linaro.org>
21
22properties:
23 compatible:
24 oneOf:
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
28
29 - items:
30 - enum:
31 - marvell,armada-ap807-sdhci
32 - marvell,ac5-sdhci
33 - const: marvell,armada-ap806-sdhci
34
35 - items:
36 - const: marvell,armada-3700-sdhci
37 - const: marvell,sdhci-xenon
38
39 reg:
40 minItems: 1
41 items:
42 - description: Xenon IP registers
43 - description: Armada 3700 SoC PHY PAD Voltage Control register
44
45 clocks:
46 minItems: 1
47 maxItems: 2
48
49 clock-names:
50 minItems: 1
51 items:
52 - const: core
53 - const: axi
54
55 dma-coherent: true
56
57 interrupts:
58 maxItems: 1
59
60 iommus:
61 maxItems: 1
62
63 marvell,pad-type:
64 $ref: /schemas/types.yaml#/definitions/string
65 enum:
66 - sd
67 - fixed-1-8v
68 description:
69 Type of Armada 3700 SoC PHY PAD Voltage Controller register. If "sd" is
70 selected, SoC PHY PAD is set as 3.3V at the beginning and is switched to
71 1.8V when later in higher speed mode. If "fixed-1-8v" is selected, SoC PHY
72 PAD is fixed 1.8V, such as for eMMC.
73
74 marvell,xenon-sdhc-id:
75 $ref: /schemas/types.yaml#/definitions/uint32
76 minimum: 0
77 maximum: 7
78 description: |
79 Indicate the corresponding bit index of current SDHC in SDHC System
80 Operation Control Register Bit[7:0]. Set/clear the corresponding bit to
81 enable/disable current SDHC.
82
83 marvell,xenon-phy-type:
84 $ref: /schemas/types.yaml#/definitions/string
85 enum:
86 - emmc 5.1 phy
87 - emmc 5.0 phy
88 description: |
89 Xenon support multiple types of PHYs. To select eMMC 5.1 PHY, set:
90 marvell,xenon-phy-type = "emmc 5.1 phy" eMMC 5.1 PHY is the default
91 choice if this property is not provided. To select eMMC 5.0 PHY, set:
92 marvell,xenon-phy-type = "emmc 5.0 phy"
93
94 All those types of PHYs can support eMMC, SD and SDIO. Please note that
95 this property only presents the type of PHY. It doesn't stand for the
96 entire SDHC type or property. For example, "emmc 5.1 phy" doesn't mean
97 that this Xenon SDHC only supports eMMC 5.1.
98
99 marvell,xenon-phy-znr:
100 $ref: /schemas/types.yaml#/definitions/uint32
101 minimum: 0
102 maximum: 0x1f
103 default: 0xf
104 description: |
105 Set PHY ZNR value.
106 Only available for eMMC PHY.
107
108 marvell,xenon-phy-zpr:
109 $ref: /schemas/types.yaml#/definitions/uint32
110 minimum: 0
111 maximum: 0x1f
112 default: 0xf
113 description: |
114 Set PHY ZPR value.
115 Only available for eMMC PHY.
116
117 marvell,xenon-phy-nr-success-tun:
118 $ref: /schemas/types.yaml#/definitions/uint32
119 minimum: 1
120 maximum: 7
121 default: 0x4
122 description: |
123 Set the number of required consecutive successful sampling points
124 used to identify a valid sampling window, in tuning process.
125
126 marvell,xenon-phy-tun-step-divider:
127 $ref: /schemas/types.yaml#/definitions/uint32
128 default: 64
129 description: |
130 Set the divider for calculating TUN_STEP.
131
132 marvell,xenon-phy-slow-mode:
133 type: boolean
134 description: |
135 If this property is selected, transfers will bypass PHY.
136 Only available when bus frequency lower than 55MHz in SDR mode.
137 Disabled by default. Please only try this property if timing issues
138 always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
139 SD Default Speed and HS mode and eMMC legacy speed mode.
140
141 marvell,xenon-tun-count:
142 $ref: /schemas/types.yaml#/definitions/uint32
143 default: 0x9
144 description: |
145 Xenon SDHC SoC usually doesn't provide re-tuning counter in
146 Capabilities Register 3 Bit[11:8].
147 This property provides the re-tuning counter.
148
149allOf:
150 - $ref: sdhci-common.yaml#
151 - if:
152 properties:
153 compatible:
154 contains:
155 const: marvell,armada-3700-sdhci
156
157 then:
158 properties:
159 reg:
160 minItems: 2
161
162 required:
163 - marvell,pad-type
164
165 else:
166 properties:
167 reg:
168 maxItems: 1
169
170 marvell,pad-type: false
171
172required:
173 - compatible
174 - reg
175 - clocks
176 - clock-names
177
178unevaluatedProperties: false
179
180examples:
181 - |
182 // For eMMC
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 #include <dt-bindings/interrupt-controller/irq.h>
185
186 mmc@aa0000 {
187 compatible = "marvell,armada-ap807-sdhci", "marvell,armada-ap806-sdhci";
188 reg = <0xaa0000 0x1000>;
189 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&emmc_clk 0>, <&axi_clk 0>;
191 clock-names = "core", "axi";
192 bus-width = <4>;
193 marvell,xenon-phy-slow-mode;
194 marvell,xenon-tun-count = <11>;
195 non-removable;
196 no-sd;
197 no-sdio;
198
199 /* Vmmc and Vqmmc are both fixed */
200 };
201
202 - |
203 // For SD/SDIO
204 #include <dt-bindings/interrupt-controller/arm-gic.h>
205 #include <dt-bindings/interrupt-controller/irq.h>
206
207 mmc@ab0000 {
208 compatible = "marvell,armada-cp110-sdhci";
209 reg = <0xab0000 0x1000>;
210 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
211 vqmmc-supply = <&sd_vqmmc_regulator>;
212 vmmc-supply = <&sd_vmmc_regulator>;
213 clocks = <&sdclk 0>, <&axi_clk 0>;
214 clock-names = "core", "axi";
215 bus-width = <4>;
216 marvell,xenon-tun-count = <9>;
217 };
218
219 - |
220 // For eMMC with compatible "marvell,armada-3700-sdhci":
221 #include <dt-bindings/interrupt-controller/arm-gic.h>
222 #include <dt-bindings/interrupt-controller/irq.h>
223
224 mmc@aa0000 {
225 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
226 reg = <0xaa0000 0x1000>,
227 <0x17808 0x4>;
228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&emmcclk 0>;
230 clock-names = "core";
231 bus-width = <8>;
232 mmc-ddr-1_8v;
233 mmc-hs400-1_8v;
234 non-removable;
235 no-sd;
236 no-sdio;
237
238 /* Vmmc and Vqmmc are both fixed */
239
240 marvell,pad-type = "fixed-1-8v";
241 };
242
243 - |
244 // For SD/SDIO with compatible "marvell,armada-3700-sdhci":
245 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 #include <dt-bindings/interrupt-controller/irq.h>
247
248 mmc@ab0000 {
249 compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon";
250 reg = <0xab0000 0x1000>,
251 <0x17808 0x4>;
252 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
253 vqmmc-supply = <&sd_regulator>;
254 /* Vmmc is fixed */
255 clocks = <&sdclk 0>;
256 clock-names = "core";
257 bus-width = <4>;
258
259 marvell,pad-type = "sd";
260 };