tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-vi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Video Input controller
8
9maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13properties:
14 $nodename:
15 pattern: "^vi@[0-9a-f]+$"
16
17 compatible:
18 oneOf:
19 - const: nvidia,tegra20-vi
20 - const: nvidia,tegra30-vi
21 - const: nvidia,tegra114-vi
22 - const: nvidia,tegra124-vi
23 - items:
24 - const: nvidia,tegra132-vi
25 - const: nvidia,tegra124-vi
26 - const: nvidia,tegra210-vi
27 - const: nvidia,tegra186-vi
28 - const: nvidia,tegra194-vi
29
30 reg:
31 maxItems: 1
32
33 interrupts:
34 maxItems: 1
35
36 clocks:
37 maxItems: 1
38
39 resets:
40 items:
41 - description: module reset
42
43 reset-names:
44 items:
45 - const: vi
46
47 iommus:
48 maxItems: 1
49
50 interconnects:
51 minItems: 4
52 maxItems: 5
53
54 interconnect-names:
55 minItems: 4
56 maxItems: 5
57
58 operating-points-v2: true
59
60 power-domains:
61 items:
62 - description: phandle to the VENC power domain
63
64 "#address-cells":
65 const: 1
66
67 "#size-cells":
68 const: 1
69
70 ranges:
71 maxItems: 1
72
73 vip:
74 $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml
75
76 ports:
77 $ref: /schemas/graph.yaml#/properties/ports
78
79 properties:
80 port@0:
81 $ref: /schemas/graph.yaml#/properties/port
82 description:
83 Input from the VIP (parallel input capture) module
84
85patternProperties:
86 "^csi@[0-9a-f]+$":
87 type: object
88
89additionalProperties: false
90
91required:
92 - compatible
93 - reg
94 - interrupts
95 - clocks
96
97allOf:
98 - if:
99 properties:
100 compatible:
101 contains:
102 enum:
103 - nvidia,tegra20-vi
104 - nvidia,tegra30-vi
105 - nvidia,tegra114-vi
106 - nvidia,tegra124-vi
107 then:
108 required:
109 - resets
110 - reset-names
111 else:
112 required:
113 - power-domains
114
115examples:
116 - |
117 #include <dt-bindings/clock/tegra20-car.h>
118 #include <dt-bindings/interrupt-controller/arm-gic.h>
119
120 i2c {
121 #address-cells = <1>;
122 #size-cells = <0>;
123 camera@48 {
124 compatible = "aptina,mt9v111";
125 reg = <0x48>;
126 clocks = <&camera_clk>;
127
128 port {
129 mt9v111_out: endpoint {
130 remote-endpoint = <&vi_vip_in>;
131 };
132 };
133 };
134 };
135
136 vi@54080000 {
137 compatible = "nvidia,tegra20-vi";
138 reg = <0x54080000 0x00040000>;
139 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&tegra_car TEGRA20_CLK_VI>;
141 resets = <&tegra_car 100>;
142 reset-names = "vi";
143
144 vip {
145 compatible = "nvidia,tegra20-vip";
146 ports {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 port@0 {
150 reg = <0>;
151 vi_vip_in: endpoint {
152 remote-endpoint = <&mt9v111_out>;
153 };
154 };
155 port@1 {
156 reg = <1>;
157 vi_vip_out: endpoint {
158 remote-endpoint = <&vi_in>;
159 };
160 };
161 };
162 };
163
164 ports {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 port@0 {
168 reg = <0>;
169 vi_in: endpoint {
170 remote-endpoint = <&vi_vip_out>;
171 };
172 };
173 };
174 };
175
176 - |
177 #include <dt-bindings/clock/tegra210-car.h>
178 #include <dt-bindings/interrupt-controller/arm-gic.h>
179
180 vi@54080000 {
181 compatible = "nvidia,tegra210-vi";
182 reg = <0x54080000 0x00000700>;
183 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
184 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
185 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
186
187 clocks = <&tegra_car TEGRA210_CLK_VI>;
188 power-domains = <&pd_venc>;
189
190 #address-cells = <1>;
191 #size-cells = <1>;
192
193 ranges = <0x0 0x54080000 0x2000>;
194
195 csi@838 {
196 compatible = "nvidia,tegra210-csi";
197 reg = <0x838 0x1300>;
198 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
199 <&tegra_car TEGRA210_CLK_CILCD>,
200 <&tegra_car TEGRA210_CLK_CILE>,
201 <&tegra_car TEGRA210_CLK_CSI_TPG>;
202 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
203 <&tegra_car TEGRA210_CLK_PLL_P>,
204 <&tegra_car TEGRA210_CLK_PLL_P>;
205 assigned-clock-rates = <102000000>,
206 <102000000>,
207 <102000000>,
208 <972000000>;
209
210 clocks = <&tegra_car TEGRA210_CLK_CSI>,
211 <&tegra_car TEGRA210_CLK_CILAB>,
212 <&tegra_car TEGRA210_CLK_CILCD>,
213 <&tegra_car TEGRA210_CLK_CILE>,
214 <&tegra_car TEGRA210_CLK_CSI_TPG>;
215 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
216 power-domains = <&pd_sor>;
217 };
218 };