tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: mediatek display DSC controller
8
9maintainers:
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
12
13description: |
14 The DSC standard is a specification of the algorithms used for
15 compressing and decompressing image display streams, including
16 the specification of the syntax and semantics of the compressed
17 video bit stream. DSC is designed for real-time systems with
18 real-time compression, transmission, decompression and Display.
19
20properties:
21 compatible:
22 oneOf:
23 - enum:
24 - mediatek,mt8195-disp-dsc
25 - items:
26 - const: mediatek,mt8188-disp-dsc
27 - const: mediatek,mt8195-disp-dsc
28
29 reg:
30 maxItems: 1
31
32 interrupts:
33 maxItems: 1
34
35 clocks:
36 items:
37 - description: DSC Wrapper Clock
38
39 power-domains:
40 description: A phandle and PM domain specifier as defined by bindings of
41 the power controller specified by phandle. See
42 Documentation/devicetree/bindings/power/power-domain.yaml for details.
43
44 mediatek,gce-client-reg:
45 description:
46 The register of client driver can be configured by gce with 4 arguments
47 defined in this property, such as phandle of gce, subsys id,
48 register offset and size.
49 Each subsys id is mapping to a base address of display function blocks
50 register which is defined in the gce header
51 include/dt-bindings/gce/<chip>-gce.h.
52 $ref: /schemas/types.yaml#/definitions/phandle-array
53 maxItems: 1
54
55 ports:
56 $ref: /schemas/graph.yaml#/properties/ports
57 description:
58 Input and output ports can have multiple endpoints, each of those
59 connects to either the primary, secondary, etc, display pipeline.
60
61 properties:
62 port@0:
63 $ref: /schemas/graph.yaml#/properties/port
64 description:
65 Display Stream Compression input, usually from one of the DITHER
66 or MERGE blocks.
67
68 port@1:
69 $ref: /schemas/graph.yaml#/properties/port
70 description:
71 Display Stream Compression output to the input of the next desired
72 component in the display pipeline, for example to MERGE, DP_INTF,
73 DPI or DSI.
74
75 required:
76 - port@0
77 - port@1
78
79required:
80 - compatible
81 - reg
82 - interrupts
83 - power-domains
84 - clocks
85
86additionalProperties: false
87
88examples:
89 - |
90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/clock/mt8195-clk.h>
92 #include <dt-bindings/power/mt8195-power.h>
93 #include <dt-bindings/gce/mt8195-gce.h>
94
95 soc {
96 #address-cells = <2>;
97 #size-cells = <2>;
98
99 dsc0: disp_dsc_wrap@1c009000 {
100 compatible = "mediatek,mt8195-disp-dsc";
101 reg = <0 0x1c009000 0 0x1000>;
102 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
103 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
104 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
105 mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
106 };
107 };