tjh.dev
Linux kernel mirror (for testing)
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1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display Clock & Reset Controller on GLYMUR
8
9maintainers:
10 - Taniya Das <taniya.das@oss.qualcomm.com>
11
12description: |
13 Qualcomm display clock control module which supports the clocks, resets and
14 power domains for the MDSS instances on GLYMUR SoC.
15
16 See also:
17 include/dt-bindings/clock/qcom,dispcc-glymur.h
18
19properties:
20 compatible:
21 enum:
22 - qcom,glymur-dispcc
23
24 clocks:
25 items:
26 - description: Board CXO clock
27 - description: Board sleep clock
28 - description: DisplayPort 0 link clock
29 - description: DisplayPort 0 VCO div clock
30 - description: DisplayPort 1 link clock
31 - description: DisplayPort 1 VCO div clock
32 - description: DisplayPort 2 link clock
33 - description: DisplayPort 2 VCO div clock
34 - description: DisplayPort 3 link clock
35 - description: DisplayPort 3 VCO div clock
36 - description: DSI 0 PLL byte clock
37 - description: DSI 0 PLL DSI clock
38 - description: DSI 1 PLL byte clock
39 - description: DSI 1 PLL DSI clock
40 - description: Standalone PHY 0 PLL link clock
41 - description: Standalone PHY 0 VCO div clock
42 - description: Standalone PHY 1 PLL link clock
43 - description: Standalone PHY 1 VCO div clock
44
45 power-domains:
46 description:
47 A phandle and PM domain specifier for the MMCX power domain.
48 maxItems: 1
49
50 required-opps:
51 description:
52 A phandle to an OPP node describing required MMCX performance point.
53 maxItems: 1
54
55required:
56 - compatible
57 - clocks
58 - power-domains
59 - '#power-domain-cells'
60
61allOf:
62 - $ref: qcom,gcc.yaml#
63
64unevaluatedProperties: false
65
66examples:
67 - |
68 #include <dt-bindings/clock/qcom,rpmh.h>
69 #include <dt-bindings/power/qcom,rpmhpd.h>
70
71 clock-controller@af00000 {
72 compatible = "qcom,glymur-dispcc";
73 reg = <0x0af00000 0x20000>;
74 clocks = <&rpmhcc RPMH_CXO_CLK>,
75 <&sleep_clk>,
76 <&mdss_dp_phy0 0>,
77 <&mdss_dp_phy0 1>,
78 <&mdss_dp_phy1 0>,
79 <&mdss_dp_phy1 1>,
80 <&mdss_dp_phy2 0>,
81 <&mdss_dp_phy2 1>,
82 <&mdss_dp_phy3 0>,
83 <&mdss_dp_phy3 1>,
84 <&mdss_dsi0_phy 0>,
85 <&mdss_dsi0_phy 1>,
86 <&mdss_dsi1_phy 0>,
87 <&mdss_dsi1_phy 1>,
88 <&mdss_phy0_link 0>,
89 <&mdss_phy0_vco_div 0>,
90 <&mdss_phy1_link 1>,
91 <&mdss_phy1_vco_div 1>;
92 power-domains = <&rpmhpd RPMHPD_MMCX>;
93 required-opps = <&rpmhpd_opp_low_svs>;
94 #clock-cells = <1>;
95 #reset-cells = <1>;
96 #power-domain-cells = <1>;
97 };
98...