tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * wm8993.c -- WM8993 ALSA SoC audio driver
4 *
5 * Copyright 2009-12 Wolfson Microelectronics plc
6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 */
9
10#include <linux/module.h>
11#include <linux/moduleparam.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/pm.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/regulator/consumer.h>
18#include <linux/spi/spi.h>
19#include <linux/slab.h>
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/tlv.h>
24#include <sound/soc.h>
25#include <sound/initval.h>
26#include <sound/wm8993.h>
27
28#include "wm8993.h"
29#include "wm_hubs.h"
30
31#define WM8993_NUM_SUPPLIES 6
32static const char *wm8993_supply_names[WM8993_NUM_SUPPLIES] = {
33 "DCVDD",
34 "DBVDD",
35 "AVDD1",
36 "AVDD2",
37 "CPVDD",
38 "SPKVDD",
39};
40
41static const struct reg_default wm8993_reg_defaults[] = {
42 { 1, 0x0000 }, /* R1 - Power Management (1) */
43 { 2, 0x6000 }, /* R2 - Power Management (2) */
44 { 3, 0x0000 }, /* R3 - Power Management (3) */
45 { 4, 0x4050 }, /* R4 - Audio Interface (1) */
46 { 5, 0x4000 }, /* R5 - Audio Interface (2) */
47 { 6, 0x01C8 }, /* R6 - Clocking 1 */
48 { 7, 0x0000 }, /* R7 - Clocking 2 */
49 { 8, 0x0000 }, /* R8 - Audio Interface (3) */
50 { 9, 0x0040 }, /* R9 - Audio Interface (4) */
51 { 10, 0x0004 }, /* R10 - DAC CTRL */
52 { 11, 0x00C0 }, /* R11 - Left DAC Digital Volume */
53 { 12, 0x00C0 }, /* R12 - Right DAC Digital Volume */
54 { 13, 0x0000 }, /* R13 - Digital Side Tone */
55 { 14, 0x0300 }, /* R14 - ADC CTRL */
56 { 15, 0x00C0 }, /* R15 - Left ADC Digital Volume */
57 { 16, 0x00C0 }, /* R16 - Right ADC Digital Volume */
58 { 18, 0x0000 }, /* R18 - GPIO CTRL 1 */
59 { 19, 0x0010 }, /* R19 - GPIO1 */
60 { 20, 0x0000 }, /* R20 - IRQ_DEBOUNCE */
61 { 21, 0x0000 }, /* R21 - Inputs Clamp */
62 { 22, 0x8000 }, /* R22 - GPIOCTRL 2 */
63 { 23, 0x0800 }, /* R23 - GPIO_POL */
64 { 24, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
65 { 25, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
66 { 26, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
67 { 27, 0x008B }, /* R27 - Right Line Input 3&4 Volume */
68 { 28, 0x006D }, /* R28 - Left Output Volume */
69 { 29, 0x006D }, /* R29 - Right Output Volume */
70 { 30, 0x0066 }, /* R30 - Line Outputs Volume */
71 { 31, 0x0020 }, /* R31 - HPOUT2 Volume */
72 { 32, 0x0079 }, /* R32 - Left OPGA Volume */
73 { 33, 0x0079 }, /* R33 - Right OPGA Volume */
74 { 34, 0x0003 }, /* R34 - SPKMIXL Attenuation */
75 { 35, 0x0003 }, /* R35 - SPKMIXR Attenuation */
76 { 36, 0x0011 }, /* R36 - SPKOUT Mixers */
77 { 37, 0x0100 }, /* R37 - SPKOUT Boost */
78 { 38, 0x0079 }, /* R38 - Speaker Volume Left */
79 { 39, 0x0079 }, /* R39 - Speaker Volume Right */
80 { 40, 0x0000 }, /* R40 - Input Mixer2 */
81 { 41, 0x0000 }, /* R41 - Input Mixer3 */
82 { 42, 0x0000 }, /* R42 - Input Mixer4 */
83 { 43, 0x0000 }, /* R43 - Input Mixer5 */
84 { 44, 0x0000 }, /* R44 - Input Mixer6 */
85 { 45, 0x0000 }, /* R45 - Output Mixer1 */
86 { 46, 0x0000 }, /* R46 - Output Mixer2 */
87 { 47, 0x0000 }, /* R47 - Output Mixer3 */
88 { 48, 0x0000 }, /* R48 - Output Mixer4 */
89 { 49, 0x0000 }, /* R49 - Output Mixer5 */
90 { 50, 0x0000 }, /* R50 - Output Mixer6 */
91 { 51, 0x0000 }, /* R51 - HPOUT2 Mixer */
92 { 52, 0x0000 }, /* R52 - Line Mixer1 */
93 { 53, 0x0000 }, /* R53 - Line Mixer2 */
94 { 54, 0x0000 }, /* R54 - Speaker Mixer */
95 { 55, 0x0000 }, /* R55 - Additional Control */
96 { 56, 0x0000 }, /* R56 - AntiPOP1 */
97 { 57, 0x0000 }, /* R57 - AntiPOP2 */
98 { 58, 0x0000 }, /* R58 - MICBIAS */
99 { 60, 0x0000 }, /* R60 - FLL Control 1 */
100 { 61, 0x0000 }, /* R61 - FLL Control 2 */
101 { 62, 0x0000 }, /* R62 - FLL Control 3 */
102 { 63, 0x2EE0 }, /* R63 - FLL Control 4 */
103 { 64, 0x0002 }, /* R64 - FLL Control 5 */
104 { 65, 0x2287 }, /* R65 - Clocking 3 */
105 { 66, 0x025F }, /* R66 - Clocking 4 */
106 { 67, 0x0000 }, /* R67 - MW Slave Control */
107 { 69, 0x0002 }, /* R69 - Bus Control 1 */
108 { 70, 0x0000 }, /* R70 - Write Sequencer 0 */
109 { 71, 0x0000 }, /* R71 - Write Sequencer 1 */
110 { 72, 0x0000 }, /* R72 - Write Sequencer 2 */
111 { 73, 0x0000 }, /* R73 - Write Sequencer 3 */
112 { 74, 0x0000 }, /* R74 - Write Sequencer 4 */
113 { 75, 0x0000 }, /* R75 - Write Sequencer 5 */
114 { 76, 0x1F25 }, /* R76 - Charge Pump 1 */
115 { 81, 0x0000 }, /* R81 - Class W 0 */
116 { 85, 0x054A }, /* R85 - DC Servo 1 */
117 { 87, 0x0000 }, /* R87 - DC Servo 3 */
118 { 96, 0x0100 }, /* R96 - Analogue HP 0 */
119 { 98, 0x0000 }, /* R98 - EQ1 */
120 { 99, 0x000C }, /* R99 - EQ2 */
121 { 100, 0x000C }, /* R100 - EQ3 */
122 { 101, 0x000C }, /* R101 - EQ4 */
123 { 102, 0x000C }, /* R102 - EQ5 */
124 { 103, 0x000C }, /* R103 - EQ6 */
125 { 104, 0x0FCA }, /* R104 - EQ7 */
126 { 105, 0x0400 }, /* R105 - EQ8 */
127 { 106, 0x00D8 }, /* R106 - EQ9 */
128 { 107, 0x1EB5 }, /* R107 - EQ10 */
129 { 108, 0xF145 }, /* R108 - EQ11 */
130 { 109, 0x0B75 }, /* R109 - EQ12 */
131 { 110, 0x01C5 }, /* R110 - EQ13 */
132 { 111, 0x1C58 }, /* R111 - EQ14 */
133 { 112, 0xF373 }, /* R112 - EQ15 */
134 { 113, 0x0A54 }, /* R113 - EQ16 */
135 { 114, 0x0558 }, /* R114 - EQ17 */
136 { 115, 0x168E }, /* R115 - EQ18 */
137 { 116, 0xF829 }, /* R116 - EQ19 */
138 { 117, 0x07AD }, /* R117 - EQ20 */
139 { 118, 0x1103 }, /* R118 - EQ21 */
140 { 119, 0x0564 }, /* R119 - EQ22 */
141 { 120, 0x0559 }, /* R120 - EQ23 */
142 { 121, 0x4000 }, /* R121 - EQ24 */
143 { 122, 0x0000 }, /* R122 - Digital Pulls */
144 { 123, 0x0F08 }, /* R123 - DRC Control 1 */
145 { 124, 0x0000 }, /* R124 - DRC Control 2 */
146 { 125, 0x0080 }, /* R125 - DRC Control 3 */
147 { 126, 0x0000 }, /* R126 - DRC Control 4 */
148};
149
150static struct {
151 int ratio;
152 int clk_sys_rate;
153} clk_sys_rates[] = {
154 { 64, 0 },
155 { 128, 1 },
156 { 192, 2 },
157 { 256, 3 },
158 { 384, 4 },
159 { 512, 5 },
160 { 768, 6 },
161 { 1024, 7 },
162 { 1408, 8 },
163 { 1536, 9 },
164};
165
166static struct {
167 int rate;
168 int sample_rate;
169} sample_rates[] = {
170 { 8000, 0 },
171 { 11025, 1 },
172 { 12000, 1 },
173 { 16000, 2 },
174 { 22050, 3 },
175 { 24000, 3 },
176 { 32000, 4 },
177 { 44100, 5 },
178 { 48000, 5 },
179};
180
181static struct {
182 int div; /* *10 due to .5s */
183 int bclk_div;
184} bclk_divs[] = {
185 { 10, 0 },
186 { 15, 1 },
187 { 20, 2 },
188 { 30, 3 },
189 { 40, 4 },
190 { 55, 5 },
191 { 60, 6 },
192 { 80, 7 },
193 { 110, 8 },
194 { 120, 9 },
195 { 160, 10 },
196 { 220, 11 },
197 { 240, 12 },
198 { 320, 13 },
199 { 440, 14 },
200 { 480, 15 },
201};
202
203struct wm8993_priv {
204 struct wm_hubs_data hubs_data;
205 struct device *dev;
206 struct regmap *regmap;
207 struct regulator_bulk_data supplies[WM8993_NUM_SUPPLIES];
208 struct wm8993_platform_data pdata;
209 struct completion fll_lock;
210 int master;
211 int sysclk_source;
212 int tdm_slots;
213 int tdm_width;
214 unsigned int mclk_rate;
215 unsigned int sysclk_rate;
216 unsigned int fs;
217 unsigned int bclk;
218 unsigned int fll_fref;
219 unsigned int fll_fout;
220 int fll_src;
221};
222
223static bool wm8993_volatile(struct device *dev, unsigned int reg)
224{
225 switch (reg) {
226 case WM8993_SOFTWARE_RESET:
227 case WM8993_GPIO_CTRL_1:
228 case WM8993_DC_SERVO_0:
229 case WM8993_DC_SERVO_READBACK_0:
230 case WM8993_DC_SERVO_READBACK_1:
231 case WM8993_DC_SERVO_READBACK_2:
232 return true;
233 default:
234 return false;
235 }
236}
237
238static bool wm8993_readable(struct device *dev, unsigned int reg)
239{
240 switch (reg) {
241 case WM8993_SOFTWARE_RESET:
242 case WM8993_POWER_MANAGEMENT_1:
243 case WM8993_POWER_MANAGEMENT_2:
244 case WM8993_POWER_MANAGEMENT_3:
245 case WM8993_AUDIO_INTERFACE_1:
246 case WM8993_AUDIO_INTERFACE_2:
247 case WM8993_CLOCKING_1:
248 case WM8993_CLOCKING_2:
249 case WM8993_AUDIO_INTERFACE_3:
250 case WM8993_AUDIO_INTERFACE_4:
251 case WM8993_DAC_CTRL:
252 case WM8993_LEFT_DAC_DIGITAL_VOLUME:
253 case WM8993_RIGHT_DAC_DIGITAL_VOLUME:
254 case WM8993_DIGITAL_SIDE_TONE:
255 case WM8993_ADC_CTRL:
256 case WM8993_LEFT_ADC_DIGITAL_VOLUME:
257 case WM8993_RIGHT_ADC_DIGITAL_VOLUME:
258 case WM8993_GPIO_CTRL_1:
259 case WM8993_GPIO1:
260 case WM8993_IRQ_DEBOUNCE:
261 case WM8993_GPIOCTRL_2:
262 case WM8993_GPIO_POL:
263 case WM8993_LEFT_LINE_INPUT_1_2_VOLUME:
264 case WM8993_LEFT_LINE_INPUT_3_4_VOLUME:
265 case WM8993_RIGHT_LINE_INPUT_1_2_VOLUME:
266 case WM8993_RIGHT_LINE_INPUT_3_4_VOLUME:
267 case WM8993_LEFT_OUTPUT_VOLUME:
268 case WM8993_RIGHT_OUTPUT_VOLUME:
269 case WM8993_LINE_OUTPUTS_VOLUME:
270 case WM8993_HPOUT2_VOLUME:
271 case WM8993_LEFT_OPGA_VOLUME:
272 case WM8993_RIGHT_OPGA_VOLUME:
273 case WM8993_SPKMIXL_ATTENUATION:
274 case WM8993_SPKMIXR_ATTENUATION:
275 case WM8993_SPKOUT_MIXERS:
276 case WM8993_SPKOUT_BOOST:
277 case WM8993_SPEAKER_VOLUME_LEFT:
278 case WM8993_SPEAKER_VOLUME_RIGHT:
279 case WM8993_INPUT_MIXER2:
280 case WM8993_INPUT_MIXER3:
281 case WM8993_INPUT_MIXER4:
282 case WM8993_INPUT_MIXER5:
283 case WM8993_INPUT_MIXER6:
284 case WM8993_OUTPUT_MIXER1:
285 case WM8993_OUTPUT_MIXER2:
286 case WM8993_OUTPUT_MIXER3:
287 case WM8993_OUTPUT_MIXER4:
288 case WM8993_OUTPUT_MIXER5:
289 case WM8993_OUTPUT_MIXER6:
290 case WM8993_HPOUT2_MIXER:
291 case WM8993_LINE_MIXER1:
292 case WM8993_LINE_MIXER2:
293 case WM8993_SPEAKER_MIXER:
294 case WM8993_ADDITIONAL_CONTROL:
295 case WM8993_ANTIPOP1:
296 case WM8993_ANTIPOP2:
297 case WM8993_MICBIAS:
298 case WM8993_FLL_CONTROL_1:
299 case WM8993_FLL_CONTROL_2:
300 case WM8993_FLL_CONTROL_3:
301 case WM8993_FLL_CONTROL_4:
302 case WM8993_FLL_CONTROL_5:
303 case WM8993_CLOCKING_3:
304 case WM8993_CLOCKING_4:
305 case WM8993_MW_SLAVE_CONTROL:
306 case WM8993_BUS_CONTROL_1:
307 case WM8993_WRITE_SEQUENCER_0:
308 case WM8993_WRITE_SEQUENCER_1:
309 case WM8993_WRITE_SEQUENCER_2:
310 case WM8993_WRITE_SEQUENCER_3:
311 case WM8993_WRITE_SEQUENCER_4:
312 case WM8993_WRITE_SEQUENCER_5:
313 case WM8993_CHARGE_PUMP_1:
314 case WM8993_CLASS_W_0:
315 case WM8993_DC_SERVO_0:
316 case WM8993_DC_SERVO_1:
317 case WM8993_DC_SERVO_3:
318 case WM8993_DC_SERVO_READBACK_0:
319 case WM8993_DC_SERVO_READBACK_1:
320 case WM8993_DC_SERVO_READBACK_2:
321 case WM8993_ANALOGUE_HP_0:
322 case WM8993_EQ1:
323 case WM8993_EQ2:
324 case WM8993_EQ3:
325 case WM8993_EQ4:
326 case WM8993_EQ5:
327 case WM8993_EQ6:
328 case WM8993_EQ7:
329 case WM8993_EQ8:
330 case WM8993_EQ9:
331 case WM8993_EQ10:
332 case WM8993_EQ11:
333 case WM8993_EQ12:
334 case WM8993_EQ13:
335 case WM8993_EQ14:
336 case WM8993_EQ15:
337 case WM8993_EQ16:
338 case WM8993_EQ17:
339 case WM8993_EQ18:
340 case WM8993_EQ19:
341 case WM8993_EQ20:
342 case WM8993_EQ21:
343 case WM8993_EQ22:
344 case WM8993_EQ23:
345 case WM8993_EQ24:
346 case WM8993_DIGITAL_PULLS:
347 case WM8993_DRC_CONTROL_1:
348 case WM8993_DRC_CONTROL_2:
349 case WM8993_DRC_CONTROL_3:
350 case WM8993_DRC_CONTROL_4:
351 return true;
352 default:
353 return false;
354 }
355}
356
357struct _fll_div {
358 u16 fll_fratio;
359 u16 fll_outdiv;
360 u16 fll_clk_ref_div;
361 u16 n;
362 u16 k;
363};
364
365/* The size in bits of the FLL divide multiplied by 10
366 * to allow rounding later */
367#define FIXED_FLL_SIZE ((1 << 16) * 10)
368
369static struct {
370 unsigned int min;
371 unsigned int max;
372 u16 fll_fratio;
373 int ratio;
374} fll_fratios[] = {
375 { 0, 64000, 4, 16 },
376 { 64000, 128000, 3, 8 },
377 { 128000, 256000, 2, 4 },
378 { 256000, 1000000, 1, 2 },
379 { 1000000, 13500000, 0, 1 },
380};
381
382static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
383 unsigned int Fout)
384{
385 u64 Kpart;
386 unsigned int K, Ndiv, Nmod, target;
387 unsigned int div;
388 int i;
389
390 /* Fref must be <=13.5MHz */
391 div = 1;
392 fll_div->fll_clk_ref_div = 0;
393 while ((Fref / div) > 13500000) {
394 div *= 2;
395 fll_div->fll_clk_ref_div++;
396
397 if (div > 8) {
398 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
399 Fref);
400 return -EINVAL;
401 }
402 }
403
404 pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
405
406 /* Apply the division for our remaining calculations */
407 Fref /= div;
408
409 /* Fvco should be 90-100MHz; don't check the upper bound */
410 div = 0;
411 target = Fout * 2;
412 while (target < 90000000) {
413 div++;
414 target *= 2;
415 if (div > 7) {
416 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
417 Fout);
418 return -EINVAL;
419 }
420 }
421 fll_div->fll_outdiv = div;
422
423 pr_debug("Fvco=%dHz\n", target);
424
425 /* Find an appropriate FLL_FRATIO and factor it out of the target */
426 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
427 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
428 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
429 target /= fll_fratios[i].ratio;
430 break;
431 }
432 }
433 if (i == ARRAY_SIZE(fll_fratios)) {
434 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
435 return -EINVAL;
436 }
437
438 /* Now, calculate N.K */
439 Ndiv = target / Fref;
440
441 fll_div->n = Ndiv;
442 Nmod = target % Fref;
443 pr_debug("Nmod=%d\n", Nmod);
444
445 /* Calculate fractional part - scale up so we can round. */
446 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
447
448 do_div(Kpart, Fref);
449
450 K = Kpart & 0xFFFFFFFF;
451
452 if ((K % 10) >= 5)
453 K += 5;
454
455 /* Move down to proper range now rounding is done */
456 fll_div->k = K / 10;
457
458 pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
459 fll_div->n, fll_div->k,
460 fll_div->fll_fratio, fll_div->fll_outdiv,
461 fll_div->fll_clk_ref_div);
462
463 return 0;
464}
465
466static int _wm8993_set_fll(struct snd_soc_component *component, int fll_id, int source,
467 unsigned int Fref, unsigned int Fout)
468{
469 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
470 struct i2c_client *i2c = to_i2c_client(component->dev);
471 u16 reg1, reg4, reg5;
472 struct _fll_div fll_div;
473 unsigned long time_left;
474 int ret;
475
476 /* Any change? */
477 if (Fref == wm8993->fll_fref && Fout == wm8993->fll_fout)
478 return 0;
479
480 /* Disable the FLL */
481 if (Fout == 0) {
482 dev_dbg(component->dev, "FLL disabled\n");
483 wm8993->fll_fref = 0;
484 wm8993->fll_fout = 0;
485
486 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
487 reg1 &= ~WM8993_FLL_ENA;
488 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
489
490 return 0;
491 }
492
493 ret = fll_factors(&fll_div, Fref, Fout);
494 if (ret != 0)
495 return ret;
496
497 reg5 = snd_soc_component_read(component, WM8993_FLL_CONTROL_5);
498 reg5 &= ~WM8993_FLL_CLK_SRC_MASK;
499
500 switch (fll_id) {
501 case WM8993_FLL_MCLK:
502 break;
503
504 case WM8993_FLL_LRCLK:
505 reg5 |= 1;
506 break;
507
508 case WM8993_FLL_BCLK:
509 reg5 |= 2;
510 break;
511
512 default:
513 dev_err(component->dev, "Unknown FLL ID %d\n", fll_id);
514 return -EINVAL;
515 }
516
517 /* Any FLL configuration change requires that the FLL be
518 * disabled first. */
519 reg1 = snd_soc_component_read(component, WM8993_FLL_CONTROL_1);
520 reg1 &= ~WM8993_FLL_ENA;
521 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
522
523 /* Apply the configuration */
524 if (fll_div.k)
525 reg1 |= WM8993_FLL_FRAC_MASK;
526 else
527 reg1 &= ~WM8993_FLL_FRAC_MASK;
528 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1);
529
530 snd_soc_component_write(component, WM8993_FLL_CONTROL_2,
531 (fll_div.fll_outdiv << WM8993_FLL_OUTDIV_SHIFT) |
532 (fll_div.fll_fratio << WM8993_FLL_FRATIO_SHIFT));
533 snd_soc_component_write(component, WM8993_FLL_CONTROL_3, fll_div.k);
534
535 reg4 = snd_soc_component_read(component, WM8993_FLL_CONTROL_4);
536 reg4 &= ~WM8993_FLL_N_MASK;
537 reg4 |= fll_div.n << WM8993_FLL_N_SHIFT;
538 snd_soc_component_write(component, WM8993_FLL_CONTROL_4, reg4);
539
540 reg5 &= ~WM8993_FLL_CLK_REF_DIV_MASK;
541 reg5 |= fll_div.fll_clk_ref_div << WM8993_FLL_CLK_REF_DIV_SHIFT;
542 snd_soc_component_write(component, WM8993_FLL_CONTROL_5, reg5);
543
544 /* If we've got an interrupt wired up make sure we get it */
545 if (i2c->irq)
546 time_left = msecs_to_jiffies(20);
547 else if (Fref < 1000000)
548 time_left = msecs_to_jiffies(3);
549 else
550 time_left = msecs_to_jiffies(1);
551
552 try_wait_for_completion(&wm8993->fll_lock);
553
554 /* Enable the FLL */
555 snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA);
556
557 time_left = wait_for_completion_timeout(&wm8993->fll_lock, time_left);
558 if (i2c->irq && !time_left)
559 dev_warn(component->dev, "Timed out waiting for FLL\n");
560
561 dev_dbg(component->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
562
563 wm8993->fll_fref = Fref;
564 wm8993->fll_fout = Fout;
565 wm8993->fll_src = source;
566
567 return 0;
568}
569
570static int wm8993_set_fll(struct snd_soc_dai *dai, int fll_id, int source,
571 unsigned int Fref, unsigned int Fout)
572{
573 return _wm8993_set_fll(dai->component, fll_id, source, Fref, Fout);
574}
575
576static int configure_clock(struct snd_soc_component *component)
577{
578 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
579 unsigned int reg;
580
581 /* This should be done on init() for bypass paths */
582 switch (wm8993->sysclk_source) {
583 case WM8993_SYSCLK_MCLK:
584 dev_dbg(component->dev, "Using %dHz MCLK\n", wm8993->mclk_rate);
585
586 reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
587 reg &= ~(WM8993_MCLK_DIV | WM8993_SYSCLK_SRC);
588 if (wm8993->mclk_rate > 13500000) {
589 reg |= WM8993_MCLK_DIV;
590 wm8993->sysclk_rate = wm8993->mclk_rate / 2;
591 } else {
592 reg &= ~WM8993_MCLK_DIV;
593 wm8993->sysclk_rate = wm8993->mclk_rate;
594 }
595 snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
596 break;
597
598 case WM8993_SYSCLK_FLL:
599 dev_dbg(component->dev, "Using %dHz FLL clock\n",
600 wm8993->fll_fout);
601
602 reg = snd_soc_component_read(component, WM8993_CLOCKING_2);
603 reg |= WM8993_SYSCLK_SRC;
604 if (wm8993->fll_fout > 13500000) {
605 reg |= WM8993_MCLK_DIV;
606 wm8993->sysclk_rate = wm8993->fll_fout / 2;
607 } else {
608 reg &= ~WM8993_MCLK_DIV;
609 wm8993->sysclk_rate = wm8993->fll_fout;
610 }
611 snd_soc_component_write(component, WM8993_CLOCKING_2, reg);
612 break;
613
614 default:
615 dev_err(component->dev, "System clock not configured\n");
616 return -EINVAL;
617 }
618
619 dev_dbg(component->dev, "CLK_SYS is %dHz\n", wm8993->sysclk_rate);
620
621 return 0;
622}
623
624static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 300, 0);
625static const DECLARE_TLV_DB_SCALE(drc_comp_threash, -4500, 75, 0);
626static const DECLARE_TLV_DB_SCALE(drc_comp_amp, -2250, 75, 0);
627static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
628static const DECLARE_TLV_DB_RANGE(drc_max_tlv,
629 0, 2, TLV_DB_SCALE_ITEM(1200, 600, 0),
630 3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0)
631);
632static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
633static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -1800, 300, 0);
634static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
635static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
636static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
637
638static const char *dac_deemph_text[] = {
639 "None",
640 "32kHz",
641 "44.1kHz",
642 "48kHz",
643};
644
645static SOC_ENUM_SINGLE_DECL(dac_deemph,
646 WM8993_DAC_CTRL, 4, dac_deemph_text);
647
648static const char *adc_hpf_text[] = {
649 "Hi-Fi",
650 "Voice 1",
651 "Voice 2",
652 "Voice 3",
653};
654
655static SOC_ENUM_SINGLE_DECL(adc_hpf,
656 WM8993_ADC_CTRL, 5, adc_hpf_text);
657
658static const char *drc_path_text[] = {
659 "ADC",
660 "DAC"
661};
662
663static SOC_ENUM_SINGLE_DECL(drc_path,
664 WM8993_DRC_CONTROL_1, 14, drc_path_text);
665
666static const char *drc_r0_text[] = {
667 "1",
668 "1/2",
669 "1/4",
670 "1/8",
671 "1/16",
672 "0",
673};
674
675static SOC_ENUM_SINGLE_DECL(drc_r0,
676 WM8993_DRC_CONTROL_3, 8, drc_r0_text);
677
678static const char *drc_r1_text[] = {
679 "1",
680 "1/2",
681 "1/4",
682 "1/8",
683 "0",
684};
685
686static SOC_ENUM_SINGLE_DECL(drc_r1,
687 WM8993_DRC_CONTROL_4, 13, drc_r1_text);
688
689static const char *drc_attack_text[] = {
690 "Reserved",
691 "181us",
692 "363us",
693 "726us",
694 "1.45ms",
695 "2.9ms",
696 "5.8ms",
697 "11.6ms",
698 "23.2ms",
699 "46.4ms",
700 "92.8ms",
701 "185.6ms",
702};
703
704static SOC_ENUM_SINGLE_DECL(drc_attack,
705 WM8993_DRC_CONTROL_2, 12, drc_attack_text);
706
707static const char *drc_decay_text[] = {
708 "186ms",
709 "372ms",
710 "743ms",
711 "1.49s",
712 "2.97ms",
713 "5.94ms",
714 "11.89ms",
715 "23.78ms",
716 "47.56ms",
717};
718
719static SOC_ENUM_SINGLE_DECL(drc_decay,
720 WM8993_DRC_CONTROL_2, 8, drc_decay_text);
721
722static const char *drc_ff_text[] = {
723 "5 samples",
724 "9 samples",
725};
726
727static SOC_ENUM_SINGLE_DECL(drc_ff,
728 WM8993_DRC_CONTROL_3, 7, drc_ff_text);
729
730static const char *drc_qr_rate_text[] = {
731 "0.725ms",
732 "1.45ms",
733 "5.8ms",
734};
735
736static SOC_ENUM_SINGLE_DECL(drc_qr_rate,
737 WM8993_DRC_CONTROL_3, 0, drc_qr_rate_text);
738
739static const char *drc_smooth_text[] = {
740 "Low",
741 "Medium",
742 "High",
743};
744
745static SOC_ENUM_SINGLE_DECL(drc_smooth,
746 WM8993_DRC_CONTROL_1, 4, drc_smooth_text);
747
748static const struct snd_kcontrol_new wm8993_snd_controls[] = {
749SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8993_DIGITAL_SIDE_TONE,
750 5, 9, 12, 0, sidetone_tlv),
751
752SOC_SINGLE("DRC Switch", WM8993_DRC_CONTROL_1, 15, 1, 0),
753SOC_ENUM("DRC Path", drc_path),
754SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8993_DRC_CONTROL_2,
755 2, 60, 1, drc_comp_threash),
756SOC_SINGLE_TLV("DRC Compressor Amplitude Volume", WM8993_DRC_CONTROL_3,
757 11, 30, 1, drc_comp_amp),
758SOC_ENUM("DRC R0", drc_r0),
759SOC_ENUM("DRC R1", drc_r1),
760SOC_SINGLE_TLV("DRC Minimum Volume", WM8993_DRC_CONTROL_1, 2, 3, 1,
761 drc_min_tlv),
762SOC_SINGLE_TLV("DRC Maximum Volume", WM8993_DRC_CONTROL_1, 0, 3, 0,
763 drc_max_tlv),
764SOC_ENUM("DRC Attack Rate", drc_attack),
765SOC_ENUM("DRC Decay Rate", drc_decay),
766SOC_ENUM("DRC FF Delay", drc_ff),
767SOC_SINGLE("DRC Anti-clip Switch", WM8993_DRC_CONTROL_1, 9, 1, 0),
768SOC_SINGLE("DRC Quick Release Switch", WM8993_DRC_CONTROL_1, 10, 1, 0),
769SOC_SINGLE_TLV("DRC Quick Release Volume", WM8993_DRC_CONTROL_3, 2, 3, 0,
770 drc_qr_tlv),
771SOC_ENUM("DRC Quick Release Rate", drc_qr_rate),
772SOC_SINGLE("DRC Smoothing Switch", WM8993_DRC_CONTROL_1, 11, 1, 0),
773SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8993_DRC_CONTROL_1, 8, 1, 0),
774SOC_ENUM("DRC Smoothing Hysteresis Threshold", drc_smooth),
775SOC_SINGLE_TLV("DRC Startup Volume", WM8993_DRC_CONTROL_4, 8, 18, 0,
776 drc_startup_tlv),
777
778SOC_SINGLE("EQ Switch", WM8993_EQ1, 0, 1, 0),
779
780SOC_DOUBLE_R_TLV("Capture Volume", WM8993_LEFT_ADC_DIGITAL_VOLUME,
781 WM8993_RIGHT_ADC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
782SOC_SINGLE("ADC High Pass Filter Switch", WM8993_ADC_CTRL, 8, 1, 0),
783SOC_ENUM("ADC High Pass Filter Mode", adc_hpf),
784
785SOC_DOUBLE_R_TLV("Playback Volume", WM8993_LEFT_DAC_DIGITAL_VOLUME,
786 WM8993_RIGHT_DAC_DIGITAL_VOLUME, 1, 96, 0, digital_tlv),
787SOC_SINGLE_TLV("Playback Boost Volume", WM8993_AUDIO_INTERFACE_2, 10, 3, 0,
788 dac_boost_tlv),
789SOC_ENUM("DAC Deemphasis", dac_deemph),
790
791SOC_SINGLE_TLV("SPKL DAC Volume", WM8993_SPKMIXL_ATTENUATION,
792 2, 1, 1, wm_hubs_spkmix_tlv),
793
794SOC_SINGLE_TLV("SPKR DAC Volume", WM8993_SPKMIXR_ATTENUATION,
795 2, 1, 1, wm_hubs_spkmix_tlv),
796};
797
798static const struct snd_kcontrol_new wm8993_eq_controls[] = {
799SOC_SINGLE_TLV("EQ1 Volume", WM8993_EQ2, 0, 24, 0, eq_tlv),
800SOC_SINGLE_TLV("EQ2 Volume", WM8993_EQ3, 0, 24, 0, eq_tlv),
801SOC_SINGLE_TLV("EQ3 Volume", WM8993_EQ4, 0, 24, 0, eq_tlv),
802SOC_SINGLE_TLV("EQ4 Volume", WM8993_EQ5, 0, 24, 0, eq_tlv),
803SOC_SINGLE_TLV("EQ5 Volume", WM8993_EQ6, 0, 24, 0, eq_tlv),
804};
805
806static int clk_sys_event(struct snd_soc_dapm_widget *w,
807 struct snd_kcontrol *kcontrol, int event)
808{
809 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
810
811 switch (event) {
812 case SND_SOC_DAPM_PRE_PMU:
813 return configure_clock(component);
814
815 case SND_SOC_DAPM_POST_PMD:
816 break;
817 }
818
819 return 0;
820}
821
822static const struct snd_kcontrol_new left_speaker_mixer[] = {
823SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 7, 1, 0),
824SOC_DAPM_SINGLE("IN1LP Switch", WM8993_SPEAKER_MIXER, 5, 1, 0),
825SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 3, 1, 0),
826SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
827};
828
829static const struct snd_kcontrol_new right_speaker_mixer[] = {
830SOC_DAPM_SINGLE("Input Switch", WM8993_SPEAKER_MIXER, 6, 1, 0),
831SOC_DAPM_SINGLE("IN1RP Switch", WM8993_SPEAKER_MIXER, 4, 1, 0),
832SOC_DAPM_SINGLE("Output Switch", WM8993_SPEAKER_MIXER, 2, 1, 0),
833SOC_DAPM_SINGLE("DAC Switch", WM8993_SPEAKER_MIXER, 0, 1, 0),
834};
835
836static const char *aif_text[] = {
837 "Left", "Right"
838};
839
840static SOC_ENUM_SINGLE_DECL(aifoutl_enum,
841 WM8993_AUDIO_INTERFACE_1, 15, aif_text);
842
843static const struct snd_kcontrol_new aifoutl_mux =
844 SOC_DAPM_ENUM("AIFOUTL Mux", aifoutl_enum);
845
846static SOC_ENUM_SINGLE_DECL(aifoutr_enum,
847 WM8993_AUDIO_INTERFACE_1, 14, aif_text);
848
849static const struct snd_kcontrol_new aifoutr_mux =
850 SOC_DAPM_ENUM("AIFOUTR Mux", aifoutr_enum);
851
852static SOC_ENUM_SINGLE_DECL(aifinl_enum,
853 WM8993_AUDIO_INTERFACE_2, 15, aif_text);
854
855static const struct snd_kcontrol_new aifinl_mux =
856 SOC_DAPM_ENUM("AIFINL Mux", aifinl_enum);
857
858static SOC_ENUM_SINGLE_DECL(aifinr_enum,
859 WM8993_AUDIO_INTERFACE_2, 14, aif_text);
860
861static const struct snd_kcontrol_new aifinr_mux =
862 SOC_DAPM_ENUM("AIFINR Mux", aifinr_enum);
863
864static const char *sidetone_text[] = {
865 "None", "Left", "Right"
866};
867
868static SOC_ENUM_SINGLE_DECL(sidetonel_enum,
869 WM8993_DIGITAL_SIDE_TONE, 2, sidetone_text);
870
871static const struct snd_kcontrol_new sidetonel_mux =
872 SOC_DAPM_ENUM("Left Sidetone", sidetonel_enum);
873
874static SOC_ENUM_SINGLE_DECL(sidetoner_enum,
875 WM8993_DIGITAL_SIDE_TONE, 0, sidetone_text);
876
877static const struct snd_kcontrol_new sidetoner_mux =
878 SOC_DAPM_ENUM("Right Sidetone", sidetoner_enum);
879
880static const struct snd_soc_dapm_widget wm8993_dapm_widgets[] = {
881SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8993_BUS_CONTROL_1, 1, 0, clk_sys_event,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
883SND_SOC_DAPM_SUPPLY("TOCLK", WM8993_CLOCKING_1, 14, 0, NULL, 0),
884SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8993_CLOCKING_3, 0, 0, NULL, 0),
885SND_SOC_DAPM_SUPPLY("VMID", SND_SOC_NOPM, 0, 0, NULL, 0),
886
887SND_SOC_DAPM_ADC("ADCL", NULL, WM8993_POWER_MANAGEMENT_2, 1, 0),
888SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
889
890SND_SOC_DAPM_MUX("AIFOUTL Mux", SND_SOC_NOPM, 0, 0, &aifoutl_mux),
891SND_SOC_DAPM_MUX("AIFOUTR Mux", SND_SOC_NOPM, 0, 0, &aifoutr_mux),
892
893SND_SOC_DAPM_AIF_OUT("AIFOUTL", "Capture", 0, SND_SOC_NOPM, 0, 0),
894SND_SOC_DAPM_AIF_OUT("AIFOUTR", "Capture", 1, SND_SOC_NOPM, 0, 0),
895
896SND_SOC_DAPM_AIF_IN("AIFINL", "Playback", 0, SND_SOC_NOPM, 0, 0),
897SND_SOC_DAPM_AIF_IN("AIFINR", "Playback", 1, SND_SOC_NOPM, 0, 0),
898
899SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &aifinl_mux),
900SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &aifinr_mux),
901
902SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &sidetonel_mux),
903SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &sidetoner_mux),
904
905SND_SOC_DAPM_DAC("DACL", NULL, WM8993_POWER_MANAGEMENT_3, 1, 0),
906SND_SOC_DAPM_DAC("DACR", NULL, WM8993_POWER_MANAGEMENT_3, 0, 0),
907
908SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpl_mux),
909SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &wm_hubs_hpr_mux),
910
911SND_SOC_DAPM_MIXER("SPKL", WM8993_POWER_MANAGEMENT_3, 8, 0,
912 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
913SND_SOC_DAPM_MIXER("SPKR", WM8993_POWER_MANAGEMENT_3, 9, 0,
914 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
915SND_SOC_DAPM_PGA("Direct Voice", SND_SOC_NOPM, 0, 0, NULL, 0),
916};
917
918static const struct snd_soc_dapm_route routes[] = {
919 { "MICBIAS1", NULL, "VMID" },
920 { "MICBIAS2", NULL, "VMID" },
921
922 { "ADCL", NULL, "CLK_SYS" },
923 { "ADCL", NULL, "CLK_DSP" },
924 { "ADCR", NULL, "CLK_SYS" },
925 { "ADCR", NULL, "CLK_DSP" },
926
927 { "AIFOUTL Mux", "Left", "ADCL" },
928 { "AIFOUTL Mux", "Right", "ADCR" },
929 { "AIFOUTR Mux", "Left", "ADCL" },
930 { "AIFOUTR Mux", "Right", "ADCR" },
931
932 { "AIFOUTL", NULL, "AIFOUTL Mux" },
933 { "AIFOUTR", NULL, "AIFOUTR Mux" },
934
935 { "DACL Mux", "Left", "AIFINL" },
936 { "DACL Mux", "Right", "AIFINR" },
937 { "DACR Mux", "Left", "AIFINL" },
938 { "DACR Mux", "Right", "AIFINR" },
939
940 { "DACL Sidetone", "Left", "ADCL" },
941 { "DACL Sidetone", "Right", "ADCR" },
942 { "DACR Sidetone", "Left", "ADCL" },
943 { "DACR Sidetone", "Right", "ADCR" },
944
945 { "DACL", NULL, "CLK_SYS" },
946 { "DACL", NULL, "CLK_DSP" },
947 { "DACL", NULL, "DACL Mux" },
948 { "DACL", NULL, "DACL Sidetone" },
949 { "DACR", NULL, "CLK_SYS" },
950 { "DACR", NULL, "CLK_DSP" },
951 { "DACR", NULL, "DACR Mux" },
952 { "DACR", NULL, "DACR Sidetone" },
953
954 { "Left Output Mixer", "DAC Switch", "DACL" },
955
956 { "Right Output Mixer", "DAC Switch", "DACR" },
957
958 { "Left Output PGA", NULL, "CLK_SYS" },
959
960 { "Right Output PGA", NULL, "CLK_SYS" },
961
962 { "SPKL", "DAC Switch", "DACL" },
963 { "SPKL", NULL, "CLK_SYS" },
964
965 { "SPKR", "DAC Switch", "DACR" },
966 { "SPKR", NULL, "CLK_SYS" },
967
968 { "Left Headphone Mux", "DAC", "DACL" },
969 { "Right Headphone Mux", "DAC", "DACR" },
970};
971
972static int wm8993_set_bias_level(struct snd_soc_component *component,
973 enum snd_soc_bias_level level)
974{
975 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
976 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
977 int ret;
978
979 wm_hubs_set_bias_level(component, level);
980
981 switch (level) {
982 case SND_SOC_BIAS_ON:
983 case SND_SOC_BIAS_PREPARE:
984 /* VMID=2*40k */
985 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
986 WM8993_VMID_SEL_MASK, 0x2);
987 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
988 WM8993_TSHUT_ENA, WM8993_TSHUT_ENA);
989 break;
990
991 case SND_SOC_BIAS_STANDBY:
992 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) {
993 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
994 wm8993->supplies);
995 if (ret != 0)
996 return ret;
997
998 regcache_cache_only(wm8993->regmap, false);
999 regcache_sync(wm8993->regmap);
1000
1001 wm_hubs_vmid_ena(component);
1002
1003 /* Bring up VMID with fast soft start */
1004 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1005 WM8993_STARTUP_BIAS_ENA |
1006 WM8993_VMID_BUF_ENA |
1007 WM8993_VMID_RAMP_MASK |
1008 WM8993_BIAS_SRC,
1009 WM8993_STARTUP_BIAS_ENA |
1010 WM8993_VMID_BUF_ENA |
1011 WM8993_VMID_RAMP_MASK |
1012 WM8993_BIAS_SRC);
1013
1014 /* If either line output is single ended we
1015 * need the VMID buffer */
1016 if (!wm8993->pdata.lineout1_diff ||
1017 !wm8993->pdata.lineout2_diff)
1018 snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1019 WM8993_LINEOUT_VMID_BUF_ENA,
1020 WM8993_LINEOUT_VMID_BUF_ENA);
1021
1022 /* VMID=2*40k */
1023 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1024 WM8993_VMID_SEL_MASK |
1025 WM8993_BIAS_ENA,
1026 WM8993_BIAS_ENA | 0x2);
1027 msleep(32);
1028
1029 /* Switch to normal bias */
1030 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1031 WM8993_BIAS_SRC |
1032 WM8993_STARTUP_BIAS_ENA, 0);
1033 }
1034
1035 /* VMID=2*240k */
1036 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1037 WM8993_VMID_SEL_MASK, 0x4);
1038
1039 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_2,
1040 WM8993_TSHUT_ENA, 0);
1041 break;
1042
1043 case SND_SOC_BIAS_OFF:
1044 snd_soc_component_update_bits(component, WM8993_ANTIPOP1,
1045 WM8993_LINEOUT_VMID_BUF_ENA, 0);
1046
1047 snd_soc_component_update_bits(component, WM8993_POWER_MANAGEMENT_1,
1048 WM8993_VMID_SEL_MASK | WM8993_BIAS_ENA,
1049 0);
1050
1051 snd_soc_component_update_bits(component, WM8993_ANTIPOP2,
1052 WM8993_STARTUP_BIAS_ENA |
1053 WM8993_VMID_BUF_ENA |
1054 WM8993_VMID_RAMP_MASK |
1055 WM8993_BIAS_SRC, 0);
1056
1057 regcache_cache_only(wm8993->regmap, true);
1058 regcache_mark_dirty(wm8993->regmap);
1059
1060 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies),
1061 wm8993->supplies);
1062 break;
1063 }
1064
1065 return 0;
1066}
1067
1068static int wm8993_set_sysclk(struct snd_soc_dai *codec_dai,
1069 int clk_id, unsigned int freq, int dir)
1070{
1071 struct snd_soc_component *component = codec_dai->component;
1072 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1073
1074 switch (clk_id) {
1075 case WM8993_SYSCLK_MCLK:
1076 wm8993->mclk_rate = freq;
1077 fallthrough;
1078 case WM8993_SYSCLK_FLL:
1079 wm8993->sysclk_source = clk_id;
1080 break;
1081
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 return 0;
1087}
1088
1089static int wm8993_set_dai_fmt(struct snd_soc_dai *dai,
1090 unsigned int fmt)
1091{
1092 struct snd_soc_component *component = dai->component;
1093 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1094 unsigned int aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1095 unsigned int aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1096
1097 aif1 &= ~(WM8993_BCLK_DIR | WM8993_AIF_BCLK_INV |
1098 WM8993_AIF_LRCLK_INV | WM8993_AIF_FMT_MASK);
1099 aif4 &= ~WM8993_LRCLK_DIR;
1100
1101 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1102 case SND_SOC_DAIFMT_CBC_CFC:
1103 wm8993->master = 0;
1104 break;
1105 case SND_SOC_DAIFMT_CBC_CFP:
1106 aif4 |= WM8993_LRCLK_DIR;
1107 wm8993->master = 1;
1108 break;
1109 case SND_SOC_DAIFMT_CBP_CFC:
1110 aif1 |= WM8993_BCLK_DIR;
1111 wm8993->master = 1;
1112 break;
1113 case SND_SOC_DAIFMT_CBP_CFP:
1114 aif1 |= WM8993_BCLK_DIR;
1115 aif4 |= WM8993_LRCLK_DIR;
1116 wm8993->master = 1;
1117 break;
1118 default:
1119 return -EINVAL;
1120 }
1121
1122 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1123 case SND_SOC_DAIFMT_DSP_B:
1124 aif1 |= WM8993_AIF_LRCLK_INV;
1125 fallthrough;
1126 case SND_SOC_DAIFMT_DSP_A:
1127 aif1 |= 0x18;
1128 break;
1129 case SND_SOC_DAIFMT_I2S:
1130 aif1 |= 0x10;
1131 break;
1132 case SND_SOC_DAIFMT_RIGHT_J:
1133 break;
1134 case SND_SOC_DAIFMT_LEFT_J:
1135 aif1 |= 0x8;
1136 break;
1137 default:
1138 return -EINVAL;
1139 }
1140
1141 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1142 case SND_SOC_DAIFMT_DSP_A:
1143 case SND_SOC_DAIFMT_DSP_B:
1144 /* frame inversion not valid for DSP modes */
1145 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1146 case SND_SOC_DAIFMT_NB_NF:
1147 break;
1148 case SND_SOC_DAIFMT_IB_NF:
1149 aif1 |= WM8993_AIF_BCLK_INV;
1150 break;
1151 default:
1152 return -EINVAL;
1153 }
1154 break;
1155
1156 case SND_SOC_DAIFMT_I2S:
1157 case SND_SOC_DAIFMT_RIGHT_J:
1158 case SND_SOC_DAIFMT_LEFT_J:
1159 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1160 case SND_SOC_DAIFMT_NB_NF:
1161 break;
1162 case SND_SOC_DAIFMT_IB_IF:
1163 aif1 |= WM8993_AIF_BCLK_INV | WM8993_AIF_LRCLK_INV;
1164 break;
1165 case SND_SOC_DAIFMT_IB_NF:
1166 aif1 |= WM8993_AIF_BCLK_INV;
1167 break;
1168 case SND_SOC_DAIFMT_NB_IF:
1169 aif1 |= WM8993_AIF_LRCLK_INV;
1170 break;
1171 default:
1172 return -EINVAL;
1173 }
1174 break;
1175 default:
1176 return -EINVAL;
1177 }
1178
1179 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1180 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1181
1182 return 0;
1183}
1184
1185static int wm8993_hw_params(struct snd_pcm_substream *substream,
1186 struct snd_pcm_hw_params *params,
1187 struct snd_soc_dai *dai)
1188{
1189 struct snd_soc_component *component = dai->component;
1190 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1191 int ret, i, best, best_val, cur_val;
1192 unsigned int clocking1, clocking3, aif1, aif4;
1193
1194 clocking1 = snd_soc_component_read(component, WM8993_CLOCKING_1);
1195 clocking1 &= ~WM8993_BCLK_DIV_MASK;
1196
1197 clocking3 = snd_soc_component_read(component, WM8993_CLOCKING_3);
1198 clocking3 &= ~(WM8993_CLK_SYS_RATE_MASK | WM8993_SAMPLE_RATE_MASK);
1199
1200 aif1 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_1);
1201 aif1 &= ~WM8993_AIF_WL_MASK;
1202
1203 aif4 = snd_soc_component_read(component, WM8993_AUDIO_INTERFACE_4);
1204 aif4 &= ~WM8993_LRCLK_RATE_MASK;
1205
1206 /* What BCLK do we need? */
1207 wm8993->fs = params_rate(params);
1208 wm8993->bclk = 2 * wm8993->fs;
1209 if (wm8993->tdm_slots) {
1210 dev_dbg(component->dev, "Configuring for %d %d bit TDM slots\n",
1211 wm8993->tdm_slots, wm8993->tdm_width);
1212 wm8993->bclk *= wm8993->tdm_width * wm8993->tdm_slots;
1213 } else {
1214 switch (params_width(params)) {
1215 case 16:
1216 wm8993->bclk *= 16;
1217 break;
1218 case 20:
1219 wm8993->bclk *= 20;
1220 aif1 |= 0x8;
1221 break;
1222 case 24:
1223 wm8993->bclk *= 24;
1224 aif1 |= 0x10;
1225 break;
1226 case 32:
1227 wm8993->bclk *= 32;
1228 aif1 |= 0x18;
1229 break;
1230 default:
1231 return -EINVAL;
1232 }
1233 }
1234
1235 dev_dbg(component->dev, "Target BCLK is %dHz\n", wm8993->bclk);
1236
1237 ret = configure_clock(component);
1238 if (ret != 0)
1239 return ret;
1240
1241 /* Select nearest CLK_SYS_RATE */
1242 best = 0;
1243 best_val = abs((wm8993->sysclk_rate / clk_sys_rates[0].ratio)
1244 - wm8993->fs);
1245 for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1246 cur_val = abs((wm8993->sysclk_rate /
1247 clk_sys_rates[i].ratio) - wm8993->fs);
1248 if (cur_val < best_val) {
1249 best = i;
1250 best_val = cur_val;
1251 }
1252 }
1253 dev_dbg(component->dev, "Selected CLK_SYS_RATIO of %d\n",
1254 clk_sys_rates[best].ratio);
1255 clocking3 |= (clk_sys_rates[best].clk_sys_rate
1256 << WM8993_CLK_SYS_RATE_SHIFT);
1257
1258 /* SAMPLE_RATE */
1259 best = 0;
1260 best_val = abs(wm8993->fs - sample_rates[0].rate);
1261 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1262 /* Closest match */
1263 cur_val = abs(wm8993->fs - sample_rates[i].rate);
1264 if (cur_val < best_val) {
1265 best = i;
1266 best_val = cur_val;
1267 }
1268 }
1269 dev_dbg(component->dev, "Selected SAMPLE_RATE of %dHz\n",
1270 sample_rates[best].rate);
1271 clocking3 |= (sample_rates[best].sample_rate
1272 << WM8993_SAMPLE_RATE_SHIFT);
1273
1274 /* BCLK_DIV */
1275 best = 0;
1276 best_val = INT_MAX;
1277 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1278 cur_val = ((wm8993->sysclk_rate * 10) / bclk_divs[i].div)
1279 - wm8993->bclk;
1280 if (cur_val < 0) /* Table is sorted */
1281 break;
1282 if (cur_val < best_val) {
1283 best = i;
1284 best_val = cur_val;
1285 }
1286 }
1287 wm8993->bclk = (wm8993->sysclk_rate * 10) / bclk_divs[best].div;
1288 dev_dbg(component->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1289 bclk_divs[best].div, wm8993->bclk);
1290 clocking1 |= bclk_divs[best].bclk_div << WM8993_BCLK_DIV_SHIFT;
1291
1292 /* LRCLK is a simple fraction of BCLK */
1293 dev_dbg(component->dev, "LRCLK_RATE is %d\n", wm8993->bclk / wm8993->fs);
1294 aif4 |= wm8993->bclk / wm8993->fs;
1295
1296 snd_soc_component_write(component, WM8993_CLOCKING_1, clocking1);
1297 snd_soc_component_write(component, WM8993_CLOCKING_3, clocking3);
1298 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_1, aif1);
1299 snd_soc_component_write(component, WM8993_AUDIO_INTERFACE_4, aif4);
1300
1301 /* ReTune Mobile? */
1302 if (wm8993->pdata.num_retune_configs) {
1303 u16 eq1 = snd_soc_component_read(component, WM8993_EQ1);
1304 struct wm8993_retune_mobile_setting *s;
1305
1306 best = 0;
1307 best_val = abs(wm8993->pdata.retune_configs[0].rate
1308 - wm8993->fs);
1309 for (i = 0; i < wm8993->pdata.num_retune_configs; i++) {
1310 cur_val = abs(wm8993->pdata.retune_configs[i].rate
1311 - wm8993->fs);
1312 if (cur_val < best_val) {
1313 best_val = cur_val;
1314 best = i;
1315 }
1316 }
1317 s = &wm8993->pdata.retune_configs[best];
1318
1319 dev_dbg(component->dev, "ReTune Mobile %s tuned for %dHz\n",
1320 s->name, s->rate);
1321
1322 /* Disable EQ while we reconfigure */
1323 snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, 0);
1324
1325 for (i = 1; i < ARRAY_SIZE(s->config); i++)
1326 snd_soc_component_write(component, WM8993_EQ1 + i, s->config[i]);
1327
1328 snd_soc_component_update_bits(component, WM8993_EQ1, WM8993_EQ_ENA, eq1);
1329 }
1330
1331 return 0;
1332}
1333
1334static int wm8993_mute(struct snd_soc_dai *codec_dai, int mute, int direction)
1335{
1336 struct snd_soc_component *component = codec_dai->component;
1337 unsigned int reg;
1338
1339 reg = snd_soc_component_read(component, WM8993_DAC_CTRL);
1340
1341 if (mute)
1342 reg |= WM8993_DAC_MUTE;
1343 else
1344 reg &= ~WM8993_DAC_MUTE;
1345
1346 snd_soc_component_write(component, WM8993_DAC_CTRL, reg);
1347
1348 return 0;
1349}
1350
1351static int wm8993_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1352 unsigned int rx_mask, int slots, int slot_width)
1353{
1354 struct snd_soc_component *component = dai->component;
1355 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1356 int aif1 = 0;
1357 int aif2 = 0;
1358
1359 /* Don't need to validate anything if we're turning off TDM */
1360 if (slots == 0) {
1361 wm8993->tdm_slots = 0;
1362 goto out;
1363 }
1364
1365 /* Note that we allow configurations we can't handle ourselves -
1366 * for example, we can generate clocks for slots 2 and up even if
1367 * we can't use those slots ourselves.
1368 */
1369 aif1 |= WM8993_AIFADC_TDM;
1370 aif2 |= WM8993_AIFDAC_TDM;
1371
1372 switch (rx_mask) {
1373 case 3:
1374 break;
1375 case 0xc:
1376 aif1 |= WM8993_AIFADC_TDM_CHAN;
1377 break;
1378 default:
1379 return -EINVAL;
1380 }
1381
1382
1383 switch (tx_mask) {
1384 case 3:
1385 break;
1386 case 0xc:
1387 aif2 |= WM8993_AIFDAC_TDM_CHAN;
1388 break;
1389 default:
1390 return -EINVAL;
1391 }
1392
1393out:
1394 wm8993->tdm_width = slot_width;
1395 wm8993->tdm_slots = slots / 2;
1396
1397 snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_1,
1398 WM8993_AIFADC_TDM | WM8993_AIFADC_TDM_CHAN, aif1);
1399 snd_soc_component_update_bits(component, WM8993_AUDIO_INTERFACE_2,
1400 WM8993_AIFDAC_TDM | WM8993_AIFDAC_TDM_CHAN, aif2);
1401
1402 return 0;
1403}
1404
1405static irqreturn_t wm8993_irq(int irq, void *data)
1406{
1407 struct wm8993_priv *wm8993 = data;
1408 int mask, val, ret;
1409
1410 ret = regmap_read(wm8993->regmap, WM8993_GPIO_CTRL_1, &val);
1411 if (ret != 0) {
1412 dev_err(wm8993->dev, "Failed to read interrupt status: %d\n",
1413 ret);
1414 return IRQ_NONE;
1415 }
1416
1417 ret = regmap_read(wm8993->regmap, WM8993_GPIOCTRL_2, &mask);
1418 if (ret != 0) {
1419 dev_err(wm8993->dev, "Failed to read interrupt mask: %d\n",
1420 ret);
1421 return IRQ_NONE;
1422 }
1423
1424 /* The IRQ pin status is visible in the register too */
1425 val &= ~(mask | WM8993_IRQ);
1426 if (!val)
1427 return IRQ_NONE;
1428
1429 if (val & WM8993_TEMPOK_EINT)
1430 dev_crit(wm8993->dev, "Thermal warning\n");
1431
1432 if (val & WM8993_FLL_LOCK_EINT) {
1433 dev_dbg(wm8993->dev, "FLL locked\n");
1434 complete(&wm8993->fll_lock);
1435 }
1436
1437 ret = regmap_write(wm8993->regmap, WM8993_GPIO_CTRL_1, val);
1438 if (ret != 0)
1439 dev_err(wm8993->dev, "Failed to ack interrupt: %d\n", ret);
1440
1441 return IRQ_HANDLED;
1442}
1443
1444static const struct snd_soc_dai_ops wm8993_ops = {
1445 .set_sysclk = wm8993_set_sysclk,
1446 .set_fmt = wm8993_set_dai_fmt,
1447 .hw_params = wm8993_hw_params,
1448 .mute_stream = wm8993_mute,
1449 .set_pll = wm8993_set_fll,
1450 .set_tdm_slot = wm8993_set_tdm_slot,
1451 .no_capture_mute = 1,
1452};
1453
1454#define WM8993_RATES SNDRV_PCM_RATE_8000_48000
1455
1456#define WM8993_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1457 SNDRV_PCM_FMTBIT_S20_3LE |\
1458 SNDRV_PCM_FMTBIT_S24_LE |\
1459 SNDRV_PCM_FMTBIT_S32_LE)
1460
1461static struct snd_soc_dai_driver wm8993_dai = {
1462 .name = "wm8993-hifi",
1463 .playback = {
1464 .stream_name = "Playback",
1465 .channels_min = 1,
1466 .channels_max = 2,
1467 .rates = WM8993_RATES,
1468 .formats = WM8993_FORMATS,
1469 .sig_bits = 24,
1470 },
1471 .capture = {
1472 .stream_name = "Capture",
1473 .channels_min = 1,
1474 .channels_max = 2,
1475 .rates = WM8993_RATES,
1476 .formats = WM8993_FORMATS,
1477 .sig_bits = 24,
1478 },
1479 .ops = &wm8993_ops,
1480 .symmetric_rate = 1,
1481};
1482
1483static int wm8993_probe(struct snd_soc_component *component)
1484{
1485 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1486 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1487
1488 wm8993->hubs_data.hp_startup_mode = 1;
1489 wm8993->hubs_data.dcs_codes_l = -2;
1490 wm8993->hubs_data.dcs_codes_r = -2;
1491 wm8993->hubs_data.series_startup = 1;
1492
1493 /* Latch volume update bits and default ZC on */
1494 snd_soc_component_update_bits(component, WM8993_RIGHT_DAC_DIGITAL_VOLUME,
1495 WM8993_DAC_VU, WM8993_DAC_VU);
1496 snd_soc_component_update_bits(component, WM8993_RIGHT_ADC_DIGITAL_VOLUME,
1497 WM8993_ADC_VU, WM8993_ADC_VU);
1498
1499 /* Manualy manage the HPOUT sequencing for independent stereo
1500 * control. */
1501 snd_soc_component_update_bits(component, WM8993_ANALOGUE_HP_0,
1502 WM8993_HPOUT1_AUTO_PU, 0);
1503
1504 /* Use automatic clock configuration */
1505 snd_soc_component_update_bits(component, WM8993_CLOCKING_4, WM8993_SR_MODE, 0);
1506
1507 wm_hubs_handle_analogue_pdata(component, wm8993->pdata.lineout1_diff,
1508 wm8993->pdata.lineout2_diff,
1509 wm8993->pdata.lineout1fb,
1510 wm8993->pdata.lineout2fb,
1511 wm8993->pdata.jd_scthr,
1512 wm8993->pdata.jd_thr,
1513 wm8993->pdata.micbias1_delay,
1514 wm8993->pdata.micbias2_delay,
1515 wm8993->pdata.micbias1_lvl,
1516 wm8993->pdata.micbias2_lvl);
1517
1518 snd_soc_add_component_controls(component, wm8993_snd_controls,
1519 ARRAY_SIZE(wm8993_snd_controls));
1520 if (wm8993->pdata.num_retune_configs != 0) {
1521 dev_dbg(component->dev, "Using ReTune Mobile\n");
1522 } else {
1523 dev_dbg(component->dev, "No ReTune Mobile, using normal EQ\n");
1524 snd_soc_add_component_controls(component, wm8993_eq_controls,
1525 ARRAY_SIZE(wm8993_eq_controls));
1526 }
1527
1528 snd_soc_dapm_new_controls(dapm, wm8993_dapm_widgets,
1529 ARRAY_SIZE(wm8993_dapm_widgets));
1530 wm_hubs_add_analogue_controls(component);
1531
1532 snd_soc_dapm_add_routes(dapm, routes, ARRAY_SIZE(routes));
1533 wm_hubs_add_analogue_routes(component, wm8993->pdata.lineout1_diff,
1534 wm8993->pdata.lineout2_diff);
1535
1536 /* If the line outputs are differential then we aren't presenting
1537 * VMID as an output and can disable it.
1538 */
1539 if (wm8993->pdata.lineout1_diff && wm8993->pdata.lineout2_diff)
1540 snd_soc_dapm_set_idle_bias(dapm, false);
1541
1542 return 0;
1543
1544}
1545
1546#ifdef CONFIG_PM
1547static int wm8993_suspend(struct snd_soc_component *component)
1548{
1549 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1550 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1551 int fll_fout = wm8993->fll_fout;
1552 int fll_fref = wm8993->fll_fref;
1553 int ret;
1554
1555 /* Stop the FLL in an orderly fashion */
1556 ret = _wm8993_set_fll(component, 0, 0, 0, 0);
1557 if (ret != 0) {
1558 dev_err(component->dev, "Failed to stop FLL\n");
1559 return ret;
1560 }
1561
1562 wm8993->fll_fout = fll_fout;
1563 wm8993->fll_fref = fll_fref;
1564
1565 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF);
1566
1567 return 0;
1568}
1569
1570static int wm8993_resume(struct snd_soc_component *component)
1571{
1572 struct wm8993_priv *wm8993 = snd_soc_component_get_drvdata(component);
1573 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component);
1574 int ret;
1575
1576 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY);
1577
1578 /* Restart the FLL? */
1579 if (wm8993->fll_fout) {
1580 int fll_fout = wm8993->fll_fout;
1581 int fll_fref = wm8993->fll_fref;
1582
1583 wm8993->fll_fref = 0;
1584 wm8993->fll_fout = 0;
1585
1586 ret = _wm8993_set_fll(component, 0, wm8993->fll_src,
1587 fll_fref, fll_fout);
1588 if (ret != 0)
1589 dev_err(component->dev, "Failed to restart FLL\n");
1590 }
1591
1592 return 0;
1593}
1594#else
1595#define wm8993_suspend NULL
1596#define wm8993_resume NULL
1597#endif
1598
1599/* Tune DC servo configuration */
1600static const struct reg_sequence wm8993_regmap_patch[] = {
1601 { 0x44, 3 },
1602 { 0x56, 3 },
1603 { 0x44, 0 },
1604};
1605
1606static const struct regmap_config wm8993_regmap = {
1607 .reg_bits = 8,
1608 .val_bits = 16,
1609
1610 .max_register = WM8993_MAX_REGISTER,
1611 .volatile_reg = wm8993_volatile,
1612 .readable_reg = wm8993_readable,
1613
1614 .cache_type = REGCACHE_MAPLE,
1615 .reg_defaults = wm8993_reg_defaults,
1616 .num_reg_defaults = ARRAY_SIZE(wm8993_reg_defaults),
1617};
1618
1619static const struct snd_soc_component_driver soc_component_dev_wm8993 = {
1620 .probe = wm8993_probe,
1621 .suspend = wm8993_suspend,
1622 .resume = wm8993_resume,
1623 .set_bias_level = wm8993_set_bias_level,
1624 .idle_bias_on = 1,
1625 .use_pmdown_time = 1,
1626 .endianness = 1,
1627};
1628
1629static int wm8993_i2c_probe(struct i2c_client *i2c)
1630{
1631 struct wm8993_priv *wm8993;
1632 unsigned int reg;
1633 int ret, i;
1634
1635 wm8993 = devm_kzalloc(&i2c->dev, sizeof(struct wm8993_priv),
1636 GFP_KERNEL);
1637 if (wm8993 == NULL)
1638 return -ENOMEM;
1639
1640 wm8993->dev = &i2c->dev;
1641 init_completion(&wm8993->fll_lock);
1642
1643 wm8993->regmap = devm_regmap_init_i2c(i2c, &wm8993_regmap);
1644 if (IS_ERR(wm8993->regmap)) {
1645 ret = PTR_ERR(wm8993->regmap);
1646 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1647 return ret;
1648 }
1649
1650 i2c_set_clientdata(i2c, wm8993);
1651
1652 for (i = 0; i < ARRAY_SIZE(wm8993->supplies); i++)
1653 wm8993->supplies[i].supply = wm8993_supply_names[i];
1654
1655 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8993->supplies),
1656 wm8993->supplies);
1657 if (ret != 0) {
1658 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1659 return ret;
1660 }
1661
1662 ret = regulator_bulk_enable(ARRAY_SIZE(wm8993->supplies),
1663 wm8993->supplies);
1664 if (ret != 0) {
1665 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
1666 return ret;
1667 }
1668
1669 ret = regmap_read(wm8993->regmap, WM8993_SOFTWARE_RESET, ®);
1670 if (ret != 0) {
1671 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1672 goto err_enable;
1673 }
1674
1675 if (reg != 0x8993) {
1676 dev_err(&i2c->dev, "Invalid ID register value %x\n", reg);
1677 ret = -EINVAL;
1678 goto err_enable;
1679 }
1680
1681 ret = regmap_write(wm8993->regmap, WM8993_SOFTWARE_RESET, 0xffff);
1682 if (ret != 0)
1683 goto err_enable;
1684
1685 ret = regmap_register_patch(wm8993->regmap, wm8993_regmap_patch,
1686 ARRAY_SIZE(wm8993_regmap_patch));
1687 if (ret != 0)
1688 dev_warn(wm8993->dev, "Failed to apply regmap patch: %d\n",
1689 ret);
1690
1691 if (i2c->irq) {
1692 /* Put GPIO1 into interrupt mode (only GPIO1 can output IRQ) */
1693 ret = regmap_update_bits(wm8993->regmap, WM8993_GPIO1,
1694 WM8993_GPIO1_PD |
1695 WM8993_GPIO1_SEL_MASK, 7);
1696 if (ret != 0)
1697 goto err_enable;
1698
1699 ret = request_threaded_irq(i2c->irq, NULL, wm8993_irq,
1700 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
1701 "wm8993", wm8993);
1702 if (ret != 0)
1703 goto err_enable;
1704
1705 }
1706
1707 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1708
1709 regcache_cache_only(wm8993->regmap, true);
1710
1711 ret = devm_snd_soc_register_component(&i2c->dev,
1712 &soc_component_dev_wm8993, &wm8993_dai, 1);
1713 if (ret != 0) {
1714 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1715 goto err_irq;
1716 }
1717
1718 return 0;
1719
1720err_irq:
1721 if (i2c->irq)
1722 free_irq(i2c->irq, wm8993);
1723err_enable:
1724 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1725 return ret;
1726}
1727
1728static void wm8993_i2c_remove(struct i2c_client *i2c)
1729{
1730 struct wm8993_priv *wm8993 = i2c_get_clientdata(i2c);
1731
1732 if (i2c->irq)
1733 free_irq(i2c->irq, wm8993);
1734 regulator_bulk_disable(ARRAY_SIZE(wm8993->supplies), wm8993->supplies);
1735}
1736
1737static const struct i2c_device_id wm8993_i2c_id[] = {
1738 { "wm8993" },
1739 { }
1740};
1741MODULE_DEVICE_TABLE(i2c, wm8993_i2c_id);
1742
1743static struct i2c_driver wm8993_i2c_driver = {
1744 .driver = {
1745 .name = "wm8993",
1746 },
1747 .probe = wm8993_i2c_probe,
1748 .remove = wm8993_i2c_remove,
1749 .id_table = wm8993_i2c_id,
1750};
1751
1752module_i2c_driver(wm8993_i2c_driver);
1753
1754MODULE_DESCRIPTION("ASoC WM8993 driver");
1755MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1756MODULE_LICENSE("GPL");