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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// rt1318.c -- RT1318 ALSA SoC audio amplifier driver
4// Author: Jack Yu <jack.yu@realtek.com>
5//
6// Copyright(c) 2024 Realtek Semiconductor Corp.
7//
8//
9
10#include <linux/acpi.h>
11#include <linux/fs.h>
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/regmap.h>
18#include <linux/i2c.h>
19#include <linux/platform_device.h>
20#include <linux/firmware.h>
21#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/soc.h>
25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
27#include <sound/tlv.h>
28#include <sound/rt1318.h>
29
30#include "rt1318.h"
31
32static const struct reg_sequence init_list[] = {
33 { 0x0000C000, 0x01},
34 { 0x0000F20D, 0x00},
35 { 0x0000F212, 0x3E},
36 { 0x0000C001, 0x02},
37 { 0x0000C003, 0x22},
38 { 0x0000C004, 0x44},
39 { 0x0000C005, 0x44},
40 { 0x0000C007, 0x64},
41 { 0x0000C00E, 0xE7},
42 { 0x0000F223, 0x7F},
43 { 0x0000F224, 0xDB},
44 { 0x0000F225, 0xEE},
45 { 0x0000F226, 0x3F},
46 { 0x0000F227, 0x0F},
47 { 0x0000F21A, 0x78},
48 { 0x0000F242, 0x3C},
49 { 0x0000C120, 0x40},
50 { 0x0000C125, 0x03},
51 { 0x0000C321, 0x0A},
52 { 0x0000C200, 0xD8},
53 { 0x0000C201, 0x27},
54 { 0x0000C202, 0x0F},
55 { 0x0000C400, 0x0E},
56 { 0x0000C401, 0x43},
57 { 0x0000C402, 0xE0},
58 { 0x0000C403, 0x00},
59 { 0x0000C404, 0x4C},
60 { 0x0000C406, 0x40},
61 { 0x0000C407, 0x02},
62 { 0x0000C408, 0x3F},
63 { 0x0000C300, 0x01},
64 { 0x0000C125, 0x03},
65 { 0x0000DF00, 0x10},
66 { 0x0000F20B, 0x2A},
67 { 0x0000DF5F, 0x01},
68 { 0x0000DF60, 0xA7},
69 { 0x0000C203, 0x84},
70 { 0x0000C206, 0x78},
71 { 0x0000F10A, 0x09},
72 { 0x0000F10B, 0x4C},
73 { 0x0000F104, 0xF4},
74 { 0x0000F105, 0x03},
75 { 0x0000F109, 0xE0},
76 { 0x0000F10B, 0x5C},
77 { 0x0000F104, 0xF4},
78 { 0x0000F105, 0x04},
79 { 0x0000F109, 0x65},
80 { 0x0000F10B, 0x5C},
81 { 0x0000F104, 0xF4},
82 { 0x0000F105, 0x02},
83 { 0x0000F109, 0x30},
84 { 0x0000F10B, 0x5C},
85 { 0x0000E706, 0x0F},
86 { 0x0000E707, 0x30},
87 { 0x0000E806, 0x0F},
88 { 0x0000E807, 0x30},
89 { 0x0000CE04, 0x03},
90 { 0x0000CE05, 0x5F},
91 { 0x0000CE06, 0xA2},
92 { 0x0000CE07, 0x6B},
93 { 0x0000CF04, 0x03},
94 { 0x0000CF05, 0x5F},
95 { 0x0000CF06, 0xA2},
96 { 0x0000CF07, 0x6B},
97 { 0x0000CE60, 0xE3},
98 { 0x0000C130, 0x51},
99 { 0x0000E000, 0xA8},
100 { 0x0000F102, 0x00},
101 { 0x0000F103, 0x00},
102 { 0x0000F104, 0xF5},
103 { 0x0000F105, 0x23},
104 { 0x0000F109, 0x04},
105 { 0x0000F10A, 0x0B},
106 { 0x0000F10B, 0x4C},
107 { 0x0000F10B, 0x5C},
108 { 0x41001888, 0x00},
109 { 0x0000C121, 0x0B},
110 { 0x0000F102, 0x00},
111 { 0x0000F103, 0x00},
112 { 0x0000F104, 0xF5},
113 { 0x0000F105, 0x23},
114 { 0x0000F109, 0x00},
115 { 0x0000F10A, 0x0B},
116 { 0x0000F10B, 0x4C},
117 { 0x0000F10B, 0x5C},
118 { 0x0000F800, 0x20},
119 { 0x0000CA00, 0x80},
120 { 0x0000CA10, 0x00},
121 { 0x0000CA02, 0x78},
122 { 0x0000CA12, 0x78},
123 { 0x0000ED00, 0x90},
124 { 0x0000E604, 0x00},
125 { 0x0000DB00, 0x0C},
126 { 0x0000DD00, 0x0C},
127 { 0x0000DC19, 0x00},
128 { 0x0000DC1A, 0x6A},
129 { 0x0000DC1B, 0xAA},
130 { 0x0000DC1C, 0xAB},
131 { 0x0000DC1D, 0x00},
132 { 0x0000DC1E, 0x16},
133 { 0x0000DC1F, 0xDB},
134 { 0x0000DC20, 0x6D},
135 { 0x0000DE19, 0x00},
136 { 0x0000DE1A, 0x6A},
137 { 0x0000DE1B, 0xAA},
138 { 0x0000DE1C, 0xAB},
139 { 0x0000DE1D, 0x00},
140 { 0x0000DE1E, 0x16},
141 { 0x0000DE1F, 0xDB},
142 { 0x0000DE20, 0x6D},
143 { 0x0000DB32, 0x00},
144 { 0x0000DD32, 0x00},
145 { 0x0000DB33, 0x0A},
146 { 0x0000DD33, 0x0A},
147 { 0x0000DB34, 0x1A},
148 { 0x0000DD34, 0x1A},
149 { 0x0000DB15, 0xEF},
150 { 0x0000DD15, 0xEF},
151 { 0x0000DB17, 0xEF},
152 { 0x0000DD17, 0xEF},
153 { 0x0000DB94, 0x70},
154 { 0x0000DD94, 0x70},
155 { 0x0000DB19, 0x40},
156 { 0x0000DD19, 0x40},
157 { 0x0000DB12, 0xC0},
158 { 0x0000DD12, 0xC0},
159 { 0x0000DB00, 0x4C},
160 { 0x0000DB04, 0x05},
161 { 0x0000DB05, 0x03},
162 { 0x0000DD04, 0x05},
163 { 0x0000DD05, 0x03},
164 { 0x0000DBBB, 0x09},
165 { 0x0000DBBC, 0x30},
166 { 0x0000DBBD, 0xF0},
167 { 0x0000DBBE, 0xF1},
168 { 0x0000DDBB, 0x09},
169 { 0x0000DDBC, 0x30},
170 { 0x0000DDBD, 0xF0},
171 { 0x0000DDBE, 0xF1},
172 { 0x0000DB01, 0x79},
173 { 0x0000DD01, 0x79},
174 { 0x0000DB08, 0x40},
175 { 0x0000DD08, 0x40},
176 { 0x0000DC52, 0xEF},
177 { 0x0000DE52, 0xEF},
178 { 0x0000DB00, 0xCC},
179 { 0x0000CC2C, 0x00},
180 { 0x0000CC2D, 0x2A},
181 { 0x0000CC2E, 0x83},
182 { 0x0000CC2F, 0xA8},
183 { 0x0000CD2C, 0x00},
184 { 0x0000CD2D, 0x2A},
185 { 0x0000CD2E, 0x83},
186 { 0x0000CD2F, 0xA8},
187 { 0x0000CC24, 0x00},
188 { 0x0000CC25, 0x51},
189 { 0x0000CC26, 0xEB},
190 { 0x0000CC27, 0x85},
191 { 0x0000CD24, 0x00},
192 { 0x0000CD25, 0x51},
193 { 0x0000CD26, 0xEB},
194 { 0x0000CD27, 0x85},
195 { 0x0000CC20, 0x00},
196 { 0x0000CC21, 0x00},
197 { 0x0000CC22, 0x43},
198 { 0x0000CD20, 0x00},
199 { 0x0000CD21, 0x00},
200 { 0x0000CD22, 0x43},
201 { 0x0000CC16, 0x0F},
202 { 0x0000CC17, 0x00},
203 { 0x0000CD16, 0x0F},
204 { 0x0000CD17, 0x00},
205 { 0x0000CC29, 0x5D},
206 { 0x0000CC2A, 0xC0},
207 { 0x0000CD29, 0x5D},
208 { 0x0000CD2A, 0xC0},
209 { 0x0000CC31, 0x20},
210 { 0x0000CC32, 0x00},
211 { 0x0000CC33, 0x00},
212 { 0x0000CC34, 0x00},
213 { 0x0000CD31, 0x20},
214 { 0x0000CD32, 0x00},
215 { 0x0000CD33, 0x00},
216 { 0x0000CD34, 0x00},
217 { 0x0000CC36, 0x79},
218 { 0x0000CC37, 0x99},
219 { 0x0000CC38, 0x99},
220 { 0x0000CC39, 0x99},
221 { 0x0000CD36, 0x79},
222 { 0x0000CD37, 0x99},
223 { 0x0000CD38, 0x99},
224 { 0x0000CD39, 0x99},
225 { 0x0000CC09, 0x00},
226 { 0x0000CC0A, 0x07},
227 { 0x0000CC0B, 0x5F},
228 { 0x0000CC0C, 0x6F},
229 { 0x0000CD09, 0x00},
230 { 0x0000CD0A, 0x07},
231 { 0x0000CD0B, 0x5F},
232 { 0x0000CD0C, 0x6F},
233 { 0x0000CC0E, 0x00},
234 { 0x0000CC0F, 0x03},
235 { 0x0000CC10, 0xAF},
236 { 0x0000CC11, 0xB7},
237 { 0x0000CD0E, 0x00},
238 { 0x0000CD0F, 0x03},
239 { 0x0000CD10, 0xAF},
240 { 0x0000CD11, 0xB7},
241 { 0x0000CCD6, 0x00},
242 { 0x0000CCD7, 0x03},
243 { 0x0000CDD6, 0x00},
244 { 0x0000CDD7, 0x03},
245 { 0x0000CCD8, 0x00},
246 { 0x0000CCD9, 0x03},
247 { 0x0000CDD8, 0x00},
248 { 0x0000CDD9, 0x03},
249 { 0x0000CCDA, 0x00},
250 { 0x0000CCDB, 0x03},
251 { 0x0000CDDA, 0x00},
252 { 0x0000CDDB, 0x03},
253 { 0x0000C320, 0x20},
254 { 0x0000C203, 0x9C},
255};
256
257static const struct reg_default rt1318_reg[] = {
258 { 0xc000, 0x00 },
259 { 0xc001, 0x43 },
260 { 0xc003, 0x22 },
261 { 0xc004, 0x44 },
262 { 0xc005, 0x44 },
263 { 0xc006, 0x33 },
264 { 0xc007, 0x64 },
265 { 0xc008, 0x05 },
266 { 0xc00a, 0xfc },
267 { 0xc00b, 0x0f },
268 { 0xc00c, 0x0e },
269 { 0xc00d, 0xef },
270 { 0xc00e, 0xe5 },
271 { 0xc00f, 0xff },
272 { 0xc120, 0xc0 },
273 { 0xc121, 0x00 },
274 { 0xc122, 0x00 },
275 { 0xc123, 0x14 },
276 { 0xc125, 0x00 },
277 { 0xc130, 0x59 },
278 { 0xc200, 0x00 },
279 { 0xc201, 0x00 },
280 { 0xc202, 0x00 },
281 { 0xc203, 0x04 },
282 { 0xc204, 0x00 },
283 { 0xc205, 0x00 },
284 { 0xc206, 0x68 },
285 { 0xc207, 0x70 },
286 { 0xc208, 0x00 },
287 { 0xc20a, 0x00 },
288 { 0xc20b, 0x01 },
289 { 0xc20c, 0x7f },
290 { 0xc20d, 0x01 },
291 { 0xc20e, 0x7f },
292 { 0xc300, 0x00 },
293 { 0xc301, 0x00 },
294 { 0xc303, 0x80 },
295 { 0xc320, 0x00 },
296 { 0xc321, 0x09 },
297 { 0xc322, 0x02 },
298 { 0xc400, 0x00 },
299 { 0xc401, 0x00 },
300 { 0xc402, 0x00 },
301 { 0xc403, 0x00 },
302 { 0xc404, 0x00 },
303 { 0xc405, 0x00 },
304 { 0xc406, 0x00 },
305 { 0xc407, 0x00 },
306 { 0xc408, 0x00 },
307 { 0xc410, 0x04 },
308 { 0xc430, 0x00 },
309 { 0xc431, 0x00 },
310 { 0xca00, 0x10 },
311 { 0xca01, 0x00 },
312 { 0xca02, 0x0b },
313 { 0xca10, 0x10 },
314 { 0xca11, 0x00 },
315 { 0xca12, 0x0b },
316 { 0xce04, 0x08 },
317 { 0xce05, 0x00 },
318 { 0xce06, 0x00 },
319 { 0xce07, 0x00 },
320 { 0xce60, 0x63 },
321 { 0xcf04, 0x08 },
322 { 0xcf05, 0x00 },
323 { 0xcf06, 0x00 },
324 { 0xcf07, 0x00 },
325 { 0xdb00, 0x00 },
326 { 0xdb08, 0x40 },
327 { 0xdb12, 0x00 },
328 { 0xdb35, 0x00 },
329 { 0xdbb5, 0x00 },
330 { 0xdbb6, 0x40 },
331 { 0xdbb7, 0x00 },
332 { 0xdbb8, 0x00 },
333 { 0xdbc5, 0x00 },
334 { 0xdbc6, 0x00 },
335 { 0xdbc7, 0x00 },
336 { 0xdbc8, 0x00 },
337 { 0xdd08, 0x40 },
338 { 0xdd12, 0x00 },
339 { 0xdd35, 0x00 },
340 { 0xddb5, 0x00 },
341 { 0xddb6, 0x40 },
342 { 0xddb7, 0x00 },
343 { 0xddb8, 0x00 },
344 { 0xddc5, 0x00 },
345 { 0xddc6, 0x00 },
346 { 0xddc7, 0x00 },
347 { 0xddc8, 0x00 },
348 { 0xdd93, 0x00 },
349 { 0xdd94, 0x64 },
350 { 0xdf00, 0x00 },
351 { 0xdf5f, 0x00 },
352 { 0xdf60, 0x00 },
353 { 0xe000, 0x08 },
354 { 0xe300, 0xa0 },
355 { 0xe400, 0x22 },
356 { 0xe706, 0x2f },
357 { 0xe707, 0x2f },
358 { 0xe806, 0x2f },
359 { 0xe807, 0x2f },
360 { 0xea00, 0x43 },
361 { 0xed00, 0x80 },
362 { 0xed01, 0x0f },
363 { 0xed02, 0xff },
364 { 0xed03, 0x00 },
365 { 0xed04, 0x00 },
366 { 0xed05, 0x0f },
367 { 0xed06, 0xff },
368 { 0xf010, 0x10 },
369 { 0xf011, 0xec },
370 { 0xf012, 0x68 },
371 { 0xf013, 0x21 },
372 { 0xf102, 0x00 },
373 { 0xf103, 0x00 },
374 { 0xf104, 0x00 },
375 { 0xf105, 0x00 },
376 { 0xf106, 0x00 },
377 { 0xf107, 0x00 },
378 { 0xf108, 0x00 },
379 { 0xf109, 0x00 },
380 { 0xf10a, 0x03 },
381 { 0xf10b, 0x40 },
382 { 0xf20b, 0x28 },
383 { 0xf20d, 0x00 },
384 { 0xf212, 0x00 },
385 { 0xf21a, 0x00 },
386 { 0xf223, 0x40 },
387 { 0xf224, 0x00 },
388 { 0xf225, 0x00 },
389 { 0xf226, 0x00 },
390 { 0xf227, 0x00 },
391 { 0xf242, 0x0c },
392 { 0xf800, 0x00 },
393 { 0xf801, 0x12 },
394 { 0xf802, 0xe0 },
395 { 0xf803, 0x2f },
396 { 0xf804, 0x00 },
397 { 0xf805, 0x00 },
398 { 0xf806, 0x07 },
399 { 0xf807, 0xff },
400};
401
402static bool rt1318_volatile_register(struct device *dev, unsigned int reg)
403{
404 switch (reg) {
405 case 0xc000:
406 case 0xc301:
407 case 0xc410:
408 case 0xc430 ... 0xc431:
409 case 0xdb06:
410 case 0xdb12:
411 case 0xdb1d ... 0xdb1f:
412 case 0xdb35:
413 case 0xdb37:
414 case 0xdb8a ... 0xdb92:
415 case 0xdbc5 ... 0xdbc8:
416 case 0xdc2b ... 0xdc49:
417 case 0xdd0b:
418 case 0xdd12:
419 case 0xdd1d ... 0xdd1f:
420 case 0xdd35:
421 case 0xdd8a ... 0xdd92:
422 case 0xddc5 ... 0xddc8:
423 case 0xde2b ... 0xde44:
424 case 0xdf4a ... 0xdf55:
425 case 0xe224 ... 0xe23b:
426 case 0xea01:
427 case 0xebc5:
428 case 0xebc8:
429 case 0xebcb ... 0xebcc:
430 case 0xed03 ... 0xed06:
431 case 0xf010 ... 0xf014:
432 return true;
433
434 default:
435 return false;
436 }
437}
438
439static bool rt1318_readable_register(struct device *dev, unsigned int reg)
440{
441 switch (reg) {
442 case 0xc000 ... 0xc00f:
443 case 0xc120 ... 0xc130:
444 case 0xc200 ... 0xc20e:
445 case 0xc300 ... 0xc303:
446 case 0xc320 ... 0xc322:
447 case 0xc400 ... 0xc408:
448 case 0xc430 ... 0xc431:
449 case 0xca00 ... 0xca02:
450 case 0xca10 ... 0xca12:
451 case 0xcb00 ... 0xcb0b:
452 case 0xcc00 ... 0xcce5:
453 case 0xcd00 ... 0xcde5:
454 case 0xce00 ... 0xce6a:
455 case 0xcf00 ... 0xcf53:
456 case 0xd000 ... 0xd0cc:
457 case 0xd100 ... 0xd1b9:
458 case 0xdb00 ... 0xdc53:
459 case 0xdd00 ... 0xde53:
460 case 0xdf00 ... 0xdf6b:
461 case 0xe000:
462 case 0xe300:
463 case 0xe400:
464 case 0xe706 ... 0xe707:
465 case 0xe806 ... 0xe807:
466 case 0xea00:
467 case 0xeb00 ... 0xebcc:
468 case 0xec00 ... 0xecb9:
469 case 0xed00 ... 0xed06:
470 case 0xf010 ... 0xf014:
471 case 0xf102 ... 0xf10b:
472 case 0xf20b:
473 case 0xf20d ... 0xf242:
474 case 0xf800 ... 0xf807:
475 return true;
476 default:
477 return false;
478 }
479}
480
481static int rt1318_dac_event(struct snd_soc_dapm_widget *w,
482 struct snd_kcontrol *kcontrol, int event)
483{
484 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
485 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
486
487 switch (event) {
488 case SND_SOC_DAPM_PRE_PMU:
489 regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
490 RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_HIGH);
491 break;
492
493 case SND_SOC_DAPM_POST_PMD:
494 regmap_update_bits(rt1318->regmap, RT1318_PWR_STA1,
495 RT1318_PDB_CTRL_MASK, RT1318_PDB_CTRL_LOW);
496 break;
497
498 default:
499 break;
500 }
501 return 0;
502}
503
504static int rt1318_dvol_put(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
508 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
509
510 rt1318->rt1318_dvol = ucontrol->value.integer.value[0];
511
512 if (rt1318->rt1318_dvol <= RT1318_DVOL_STEP && rt1318->rt1318_dvol >= 0) {
513 regmap_write(rt1318->regmap, RT1318_DA_VOL_L_8,
514 rt1318->rt1318_dvol >> 8);
515 regmap_write(rt1318->regmap, RT1318_DA_VOL_L_1_7,
516 rt1318->rt1318_dvol & 0xff);
517 regmap_write(rt1318->regmap, RT1318_DA_VOL_R_8,
518 rt1318->rt1318_dvol >> 8);
519 regmap_write(rt1318->regmap, RT1318_DA_VOL_R_1_7,
520 rt1318->rt1318_dvol & 0xff);
521 return 1;
522 }
523
524 return 0;
525}
526
527static int rt1318_dvol_get(struct snd_kcontrol *kcontrol,
528 struct snd_ctl_elem_value *ucontrol)
529{
530 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
531 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
532
533 ucontrol->value.integer.value[0] = rt1318->rt1318_dvol;
534
535 return 0;
536}
537
538static const struct snd_kcontrol_new rt1318_snd_controls[] = {
539 SOC_SINGLE_EXT("Amp Playback Volume", SND_SOC_NOPM, 0, 383, 0,
540 rt1318_dvol_get, rt1318_dvol_put),
541};
542
543static const struct snd_soc_dapm_widget rt1318_dapm_widgets[] = {
544 /* Audio Interface */
545 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
546 /* DACs */
547 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
548 rt1318_dac_event, SND_SOC_DAPM_PRE_PMU |
549 SND_SOC_DAPM_POST_PMD),
550 /* Output Lines */
551 SND_SOC_DAPM_OUTPUT("Amp"),
552};
553
554static const struct snd_soc_dapm_route rt1318_dapm_routes[] = {
555 {"DAC", NULL, "AIF1RX"},
556 {"Amp", NULL, "DAC"},
557};
558
559static int rt1318_get_clk_info(int sclk, int rate)
560{
561 int i, pd[] = {1, 2, 4, 8, 16, 24};
562
563 if (sclk <= 0 || rate <= 0)
564 return -EINVAL;
565
566 rate = rate << 8;
567 for (i = 0; i < ARRAY_SIZE(pd); i++)
568 if (sclk == rate * pd[i])
569 return i;
570
571 return -EINVAL;
572}
573
574static int rt1318_clk_ip_info(struct snd_soc_component *component, int lrclk)
575{
576 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
577
578 switch (lrclk) {
579 case RT1318_LRCLK_48000:
580 case RT1318_LRCLK_44100:
581 case RT1318_LRCLK_16000:
582 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
583 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
584 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON4);
585 break;
586 case RT1318_LRCLK_96000:
587 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
588 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
589 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON2);
590 break;
591 case RT1318_LRCLK_192000:
592 regmap_update_bits(rt1318->regmap, RT1318_SRC_TCON,
593 RT1318_SRCIN_F12288_MASK | RT1318_SRCIN_DACLK_MASK,
594 RT1318_SRCIN_TCON4 | RT1318_DACLK_TCON1);
595 break;
596 default:
597 dev_err(component->dev, "Unsupported clock rate.\n");
598 return -EINVAL;
599 }
600
601 return 0;
602}
603
604static int rt1318_hw_params(struct snd_pcm_substream *substream,
605 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
606{
607 struct snd_soc_component *component = dai->component;
608 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
609 int data_len = 0, ch_len = 0;
610 int pre_div, ret;
611
612 rt1318->lrck = params_rate(params);
613 pre_div = rt1318_get_clk_info(rt1318->sysclk, rt1318->lrck);
614 if (pre_div < 0) {
615 dev_err(component->dev, "Unsupported clock setting\n");
616 return -EINVAL;
617 }
618 ret = rt1318_clk_ip_info(component, rt1318->lrck);
619 if (ret < 0) {
620 dev_err(component->dev, "Unsupported clock setting\n");
621 return -EINVAL;
622 }
623
624 switch (params_width(params)) {
625 case 16:
626 break;
627 case 20:
628 data_len = RT1318_I2S_DL_20;
629 ch_len = RT1318_I2S_DL_20;
630 break;
631 case 24:
632 data_len = RT1318_I2S_DL_24;
633 ch_len = RT1318_I2S_DL_24;
634 break;
635 case 32:
636 data_len = RT1318_I2S_DL_32;
637 ch_len = RT1318_I2S_DL_32;
638 break;
639 case 8:
640 data_len = RT1318_I2S_DL_8;
641 ch_len = RT1318_I2S_DL_8;
642 break;
643 default:
644 return -EINVAL;
645 }
646
647 regmap_update_bits(rt1318->regmap, RT1318_CLK2,
648 RT1318_DIV_AP_MASK | RT1318_DIV_DAMOD_MASK,
649 pre_div << RT1318_DIV_AP_SFT |
650 pre_div << RT1318_DIV_DAMOD_SFT);
651 regmap_update_bits(rt1318->regmap, RT1318_CLK3,
652 RT1318_AD_STO1_MASK | RT1318_AD_STO2_MASK,
653 pre_div << RT1318_AD_STO1_SFT |
654 pre_div << RT1318_AD_STO2_SFT);
655 regmap_update_bits(rt1318->regmap, RT1318_CLK4,
656 RT1318_AD_ANA_STO1_MASK | RT1318_AD_ANA_STO2_MASK,
657 pre_div << RT1318_AD_ANA_STO1_SFT |
658 pre_div << RT1318_AD_ANA_STO2_SFT);
659 regmap_update_bits(rt1318->regmap, RT1318_CLK5,
660 RT1318_DIV_FIFO_IN_MASK | RT1318_DIV_FIFO_OUT_MASK,
661 pre_div << RT1318_DIV_FIFO_IN_SFT |
662 pre_div << RT1318_DIV_FIFO_OUT_SFT);
663 regmap_update_bits(rt1318->regmap, RT1318_CLK6,
664 RT1318_DIV_NLMS_MASK | RT1318_DIV_AD_MONO_MASK |
665 RT1318_DIV_POST_G_MASK, pre_div << RT1318_DIV_NLMS_SFT |
666 pre_div << RT1318_DIV_AD_MONO_SFT |
667 pre_div << RT1318_DIV_POST_G_SFT);
668
669 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
670 RT1318_I2S_DL_MASK, data_len << RT1318_I2S_DL_SFT);
671 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
672 RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK,
673 ch_len << RT1318_I2S_TX_CHL_SFT |
674 ch_len << RT1318_I2S_RX_CHL_SFT);
675
676 return 0;
677}
678
679static int rt1318_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
680{
681 struct snd_soc_component *component = dai->component;
682 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
683 unsigned int reg_val = 0, reg_val2 = 0;
684
685 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
686 case SND_SOC_DAIFMT_NB_NF:
687 break;
688 case SND_SOC_DAIFMT_IB_NF:
689 reg_val2 |= RT1318_TDM_BCLK_INV;
690 break;
691 default:
692 return -EINVAL;
693 }
694
695 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
696 case SND_SOC_DAIFMT_I2S:
697 break;
698
699 case SND_SOC_DAIFMT_LEFT_J:
700 reg_val |= RT1318_FMT_LEFT_J;
701 break;
702
703 case SND_SOC_DAIFMT_DSP_A:
704 reg_val |= RT1318_FMT_PCM_A_R;
705 break;
706
707 case SND_SOC_DAIFMT_DSP_B:
708 reg_val |= RT1318_FMT_PCM_B_R;
709 break;
710
711 default:
712 return -EINVAL;
713 }
714
715 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
716 RT1318_I2S_FMT_MASK, reg_val);
717 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL1,
718 RT1318_TDM_BCLK_MASK, reg_val2);
719
720 return 0;
721}
722
723static int rt1318_set_dai_sysclk(struct snd_soc_dai *dai,
724 int clk_id, unsigned int freq, int dir)
725{
726 struct snd_soc_component *component = dai->component;
727 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
728 int reg_val = 0;
729
730 if (freq == rt1318->sysclk && clk_id == rt1318->sysclk_src)
731 return 0;
732
733 switch (clk_id) {
734 case RT1318_SCLK_S_BCLK:
735 reg_val |= RT1318_SYSCLK_BCLK;
736 break;
737 case RT1318_SCLK_S_SDW:
738 reg_val |= RT1318_SYSCLK_SDW;
739 break;
740 case RT1318_SCLK_S_PLL2F:
741 reg_val |= RT1318_SYSCLK_PLL2F;
742 break;
743 case RT1318_SCLK_S_PLL2B:
744 reg_val |= RT1318_SYSCLK_PLL2B;
745 break;
746 case RT1318_SCLK_S_MCLK:
747 reg_val |= RT1318_SYSCLK_MCLK;
748 break;
749 case RT1318_SCLK_S_RC0:
750 reg_val |= RT1318_SYSCLK_RC1;
751 break;
752 case RT1318_SCLK_S_RC1:
753 reg_val |= RT1318_SYSCLK_RC2;
754 break;
755 case RT1318_SCLK_S_RC2:
756 reg_val |= RT1318_SYSCLK_RC3;
757 break;
758 default:
759 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
760 return -EINVAL;
761 }
762
763 rt1318->sysclk = freq;
764 rt1318->sysclk_src = clk_id;
765 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
766 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
767 RT1318_SYSCLK_SEL_MASK, reg_val);
768
769 return 0;
770}
771
772static const struct pll_calc_map pll_preset_table[] = {
773 {512000, 4096000, 22, 190, 0, true, false},
774 {1024000, 4096000, 22, 94, 0, true, false},
775 {1024000, 16384000, 4, 190, 0, true, false},
776 {1411200, 11289600, 6, 62, 0, true, false},
777 {1536000, 12288000, 6, 62, 0, true, false},
778 {2822400, 11289600, 6, 62, 0, true, false},
779 {2822400, 45158400, 0, 62, 0, true, false},
780 {2822400, 49152000, 0, 62, 0, true, false},
781 {3072000, 12288000, 6, 62, 0, true, false},
782 {3072000, 24576000, 2, 62, 0, true, false},
783 {3072000, 49152000, 0, 62, 0, true, false},
784 {6144000, 24576000, 2, 94, 4, false, false},
785 {6144000, 49152000, 0, 30, 0, true, false},
786 {6144000, 98304000, 0, 94, 4, false, true},
787 {12288000, 49152000, 0, 62, 6, false, false},
788};
789
790static int rt1318_pll_calc(const unsigned int freq_in,
791 const unsigned int freq_out, struct rt1318_pll_code *pll_code)
792{
793 int max_n = RT1318_PLL_N_MAX, max_m = RT1318_PLL_M_MAX;
794 int i, k, red, n_t, pll_out, in_t, out_t;
795 int n = 0, m = 0, m_t = 0;
796 int red_t = abs(freq_out - freq_in);
797 bool m_bypass = false, k_bypass = false;
798
799 if (RT1318_PLL_INP_MAX < freq_in || RT1318_PLL_INP_MIN > freq_in)
800 return -EINVAL;
801
802 for (i = 0; i < ARRAY_SIZE(pll_preset_table); i++) {
803 if (freq_in == pll_preset_table[i].pll_in &&
804 freq_out == pll_preset_table[i].pll_out) {
805 k = pll_preset_table[i].k;
806 m = pll_preset_table[i].m;
807 n = pll_preset_table[i].n;
808 m_bypass = pll_preset_table[i].m_bp;
809 k_bypass = pll_preset_table[i].k_bp;
810 goto code_find;
811 }
812 }
813
814 k = 100000000 / freq_out - 2;
815 if (k > RT1318_PLL_K_MAX)
816 k = RT1318_PLL_K_MAX;
817 if (k < 0) {
818 k = 0;
819 k_bypass = true;
820 }
821 for (n_t = 0; n_t <= max_n; n_t++) {
822 in_t = freq_in / (k_bypass ? 1 : (k + 2));
823 pll_out = freq_out / (n_t + 2);
824 if (in_t < 0)
825 continue;
826 if (in_t == pll_out) {
827 m_bypass = true;
828 n = n_t;
829 goto code_find;
830 }
831 red = abs(in_t - pll_out);
832 if (red < red_t) {
833 m_bypass = true;
834 n = n_t;
835 m = m_t;
836 if (red == 0)
837 goto code_find;
838 red_t = red;
839 }
840 for (m_t = 0; m_t <= max_m; m_t++) {
841 out_t = in_t / (m_t + 2);
842 red = abs(out_t - pll_out);
843 if (red < red_t) {
844 m_bypass = false;
845 n = n_t;
846 m = m_t;
847 if (red == 0)
848 goto code_find;
849 red_t = red;
850 }
851 }
852 }
853 pr_debug("Only get approximation about PLL\n");
854
855code_find:
856
857 pll_code->m_bp = m_bypass;
858 pll_code->k_bp = k_bypass;
859 pll_code->m_code = m;
860 pll_code->n_code = n;
861 pll_code->k_code = k;
862 return 0;
863}
864
865static int rt1318_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
866 unsigned int freq_in, unsigned int freq_out)
867{
868 struct snd_soc_component *component = dai->component;
869 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
870 struct rt1318_pll_code pll_code;
871 int ret;
872
873 if (!freq_in || !freq_out) {
874 dev_dbg(component->dev, "PLL disabled\n");
875 rt1318->pll_in = 0;
876 rt1318->pll_out = 0;
877 return 0;
878 }
879
880 if (source == rt1318->pll_src && freq_in == rt1318->pll_in &&
881 freq_out == rt1318->pll_out)
882 return 0;
883
884 switch (source) {
885 case RT1318_PLL_S_BCLK0:
886 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
887 RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK0);
888 break;
889 case RT1318_PLL_S_BCLK1:
890 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
891 RT1318_PLLIN_MASK, RT1318_PLLIN_BCLK1);
892 break;
893 case RT1318_PLL_S_RC:
894 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
895 RT1318_PLLIN_MASK, RT1318_PLLIN_RC);
896 break;
897 case RT1318_PLL_S_MCLK:
898 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
899 RT1318_PLLIN_MASK, RT1318_PLLIN_MCLK);
900 break;
901 case RT1318_PLL_S_SDW_IN_PLL:
902 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
903 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW1);
904 break;
905 case RT1318_PLL_S_SDW_0:
906 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
907 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW2);
908 break;
909 case RT1318_PLL_S_SDW_1:
910 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
911 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW3);
912 break;
913 case RT1318_PLL_S_SDW_2:
914 regmap_update_bits(rt1318->regmap, RT1318_CLK1,
915 RT1318_PLLIN_MASK, RT1318_PLLIN_SDW4);
916 break;
917 default:
918 dev_err(component->dev, "Unknown PLL source %d\n", source);
919 return -EINVAL;
920 }
921
922 ret = rt1318_pll_calc(freq_in, freq_out, &pll_code);
923 if (ret < 0) {
924 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
925 return ret;
926 }
927
928 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
929 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
930 pll_code.n_code, pll_code.k_code);
931
932 regmap_update_bits(rt1318->regmap, RT1318_PLL1_K,
933 RT1318_K_PLL1_MASK, pll_code.k_code);
934 regmap_update_bits(rt1318->regmap, RT1318_PLL1_M,
935 RT1318_M_PLL1_MASK, (pll_code.m_bp ? 0 : pll_code.m_code));
936 regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_8,
937 RT1318_N_8_PLL1_MASK, pll_code.n_code >> 8);
938 regmap_update_bits(rt1318->regmap, RT1318_PLL1_N_7_0,
939 RT1318_N_7_0_PLL1_MASK, pll_code.n_code);
940
941 rt1318->pll_in = freq_in;
942 rt1318->pll_out = freq_out;
943 rt1318->pll_src = source;
944
945 return 0;
946}
947
948static int rt1318_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
949 unsigned int rx_mask, int slots, int slot_width)
950{
951 struct snd_soc_component *component = dai->component;
952 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
953 unsigned int cn = 0, cl = 0, rx_slotnum;
954 int ret = 0, first_bit;
955
956 switch (slots) {
957 case 4:
958 cn |= RT1318_I2S_CH_TX_4CH;
959 cn |= RT1318_I2S_CH_RX_4CH;
960 break;
961 case 6:
962 cn |= RT1318_I2S_CH_TX_6CH;
963 cn |= RT1318_I2S_CH_RX_6CH;
964 break;
965 case 8:
966 cn |= RT1318_I2S_CH_TX_8CH;
967 cn |= RT1318_I2S_CH_RX_8CH;
968 break;
969 case 2:
970 break;
971 default:
972 return -EINVAL;
973 }
974
975 switch (slot_width) {
976 case 20:
977 cl |= RT1318_I2S_TX_CHL_20;
978 cl |= RT1318_I2S_RX_CHL_20;
979 break;
980 case 24:
981 cl |= RT1318_I2S_TX_CHL_24;
982 cl |= RT1318_I2S_RX_CHL_24;
983 break;
984 case 32:
985 cl |= RT1318_I2S_TX_CHL_32;
986 cl |= RT1318_I2S_RX_CHL_32;
987 break;
988 case 8:
989 cl |= RT1318_I2S_TX_CHL_8;
990 cl |= RT1318_I2S_RX_CHL_8;
991 break;
992 case 16:
993 break;
994 default:
995 return -EINVAL;
996 }
997
998 /* Rx slot configuration */
999 rx_slotnum = hweight_long(rx_mask);
1000 if (rx_slotnum != 1) {
1001 ret = -EINVAL;
1002 dev_err(component->dev, "too many rx slots or zero slot\n");
1003 goto _set_tdm_err_;
1004 }
1005
1006 first_bit = __ffs(rx_mask);
1007 switch (first_bit) {
1008 case 0:
1009 case 2:
1010 case 4:
1011 case 6:
1012 regmap_update_bits(rt1318->regmap,
1013 RT1318_TDM_CTRL9,
1014 RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1015 RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1016 (first_bit << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1017 ((first_bit + 1) << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1018 break;
1019 case 1:
1020 case 3:
1021 case 5:
1022 case 7:
1023 regmap_update_bits(rt1318->regmap,
1024 RT1318_TDM_CTRL9,
1025 RT1318_TDM_I2S_TX_L_DAC1_1_MASK |
1026 RT1318_TDM_I2S_TX_R_DAC1_1_MASK,
1027 ((first_bit - 1) << RT1318_TDM_I2S_TX_L_DAC1_1_SFT) |
1028 (first_bit << RT1318_TDM_I2S_TX_R_DAC1_1_SFT));
1029 break;
1030 default:
1031 ret = -EINVAL;
1032 goto _set_tdm_err_;
1033 }
1034
1035 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL2,
1036 RT1318_I2S_CH_TX_MASK | RT1318_I2S_CH_RX_MASK, cn);
1037 regmap_update_bits(rt1318->regmap, RT1318_TDM_CTRL3,
1038 RT1318_I2S_TX_CHL_MASK | RT1318_I2S_RX_CHL_MASK, cl);
1039
1040_set_tdm_err_:
1041 return ret;
1042}
1043
1044static int rt1318_probe(struct snd_soc_component *component)
1045{
1046 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1047
1048 rt1318->component = component;
1049
1050 schedule_work(&rt1318->cali_work);
1051 rt1318->rt1318_dvol = RT1318_DVOL_STEP;
1052
1053 return 0;
1054}
1055
1056static void rt1318_remove(struct snd_soc_component *component)
1057{
1058 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1059
1060 cancel_work_sync(&rt1318->cali_work);
1061}
1062
1063#ifdef CONFIG_PM
1064static int rt1318_suspend(struct snd_soc_component *component)
1065{
1066 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1067
1068 regcache_cache_only(rt1318->regmap, true);
1069 regcache_mark_dirty(rt1318->regmap);
1070 return 0;
1071}
1072
1073static int rt1318_resume(struct snd_soc_component *component)
1074{
1075 struct rt1318_priv *rt1318 = snd_soc_component_get_drvdata(component);
1076
1077 regcache_cache_only(rt1318->regmap, false);
1078 regcache_sync(rt1318->regmap);
1079 return 0;
1080}
1081#else
1082#define rt1318_suspend NULL
1083#define rt1318_resume NULL
1084#endif
1085
1086#define RT1318_STEREO_RATES SNDRV_PCM_RATE_8000_192000
1087#define RT1318_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1088 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1089
1090static const struct snd_soc_dai_ops rt1318_aif_dai_ops = {
1091 .hw_params = rt1318_hw_params,
1092 .set_fmt = rt1318_set_dai_fmt,
1093 .set_sysclk = rt1318_set_dai_sysclk,
1094 .set_pll = rt1318_set_dai_pll,
1095 .set_tdm_slot = rt1318_set_tdm_slot,
1096};
1097
1098static struct snd_soc_dai_driver rt1318_dai[] = {
1099 {
1100 .name = "rt1318-aif",
1101 .id = 0,
1102 .playback = {
1103 .stream_name = "AIF1 Playback",
1104 .channels_min = 1,
1105 .channels_max = 2,
1106 .rates = RT1318_STEREO_RATES,
1107 .formats = RT1318_FORMATS,
1108 },
1109 .ops = &rt1318_aif_dai_ops,
1110 }
1111};
1112
1113static const struct snd_soc_component_driver soc_component_dev_rt1318 = {
1114 .probe = rt1318_probe,
1115 .remove = rt1318_remove,
1116 .suspend = rt1318_suspend,
1117 .resume = rt1318_resume,
1118 .controls = rt1318_snd_controls,
1119 .num_controls = ARRAY_SIZE(rt1318_snd_controls),
1120 .dapm_widgets = rt1318_dapm_widgets,
1121 .num_dapm_widgets = ARRAY_SIZE(rt1318_dapm_widgets),
1122 .dapm_routes = rt1318_dapm_routes,
1123 .num_dapm_routes = ARRAY_SIZE(rt1318_dapm_routes),
1124 .use_pmdown_time = 1,
1125 .endianness = 1,
1126};
1127
1128static const struct regmap_config rt1318_regmap = {
1129 .reg_bits = 32,
1130 .val_bits = 8,
1131 .readable_reg = rt1318_readable_register,
1132 .volatile_reg = rt1318_volatile_register,
1133 .max_register = 0x41001888,
1134 .reg_defaults = rt1318_reg,
1135 .num_reg_defaults = ARRAY_SIZE(rt1318_reg),
1136 .cache_type = REGCACHE_RBTREE,
1137 .use_single_read = true,
1138 .use_single_write = true,
1139};
1140
1141static const struct i2c_device_id rt1318_i2c_id[] = {
1142 { "rt1318" },
1143 { }
1144};
1145MODULE_DEVICE_TABLE(i2c, rt1318_i2c_id);
1146
1147static const struct of_device_id rt1318_of_match[] = {
1148 { .compatible = "realtek,rt1318", },
1149 { }
1150};
1151MODULE_DEVICE_TABLE(of, rt1318_of_match);
1152
1153#ifdef CONFIG_ACPI
1154static const struct acpi_device_id rt1318_acpi_match[] = {
1155 { "10EC1318" },
1156 { }
1157};
1158MODULE_DEVICE_TABLE(acpi, rt1318_acpi_match);
1159#endif
1160
1161static int rt1318_parse_dt(struct rt1318_priv *rt1318, struct device *dev)
1162{
1163 device_property_read_u32(dev, "realtek,r0_l",
1164 &rt1318->pdata.init_r0_l);
1165 device_property_read_u32(dev, "realtek,r0_r",
1166 &rt1318->pdata.init_r0_r);
1167
1168 return 0;
1169}
1170
1171static void rt1318_calibration_sequence(struct rt1318_priv *rt1318)
1172{
1173 regmap_write(rt1318->regmap, RT1318_CLK1, 0x22);
1174 regmap_write(rt1318->regmap, RT1318_PLL1_N_7_0, 0x06);
1175 regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xCC);
1176 regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x40);
1177 regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x40);
1178 regmap_write(rt1318->regmap, RT1318_SINE_GEN0, 0x20);
1179 regmap_write(rt1318->regmap, RT1318_SPK_VOL_TH, 0x00);
1180 regmap_write(rt1318->regmap, RT1318_FEEDBACK_PATH, 0x0B);
1181 regmap_write(rt1318->regmap, RT1318_TCON, 0x1C);
1182 regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x58);
1183 regmap_write(rt1318->regmap, RT1318_TCON_RELATE, 0x78);
1184 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xC2);
1185}
1186
1187static void rt1318_r0_calculate(struct rt1318_priv *rt1318)
1188{
1189 unsigned int r0_l, r0_l_byte0, r0_l_byte1, r0_l_byte2, r0_l_byte3;
1190 unsigned int r0_r, r0_r_byte0, r0_r_byte1, r0_r_byte2, r0_r_byte3;
1191 unsigned int r0_l_integer, r0_l_factor, r0_r_integer, r0_r_factor;
1192 unsigned int format = 16777216; /* 2^24 */
1193
1194 regmap_read(rt1318->regmap, RT1318_R0_L_24, &r0_l_byte0);
1195 regmap_read(rt1318->regmap, RT1318_R0_L_23_16, &r0_l_byte1);
1196 regmap_read(rt1318->regmap, RT1318_R0_L_15_8, &r0_l_byte2);
1197 regmap_read(rt1318->regmap, RT1318_R0_L_7_0, &r0_l_byte3);
1198 r0_l = r0_l_byte0 << 24 | r0_l_byte1 << 16 | r0_l_byte2 << 8 | r0_l_byte3;
1199 r0_l_integer = format / r0_l;
1200 r0_l_factor = (format * 10) / r0_l - r0_l_integer * 10;
1201
1202 regmap_read(rt1318->regmap, RT1318_R0_R_24, &r0_r_byte0);
1203 regmap_read(rt1318->regmap, RT1318_R0_R_23_16, &r0_r_byte1);
1204 regmap_read(rt1318->regmap, RT1318_R0_R_15_8, &r0_r_byte2);
1205 regmap_read(rt1318->regmap, RT1318_R0_R_7_0, &r0_r_byte3);
1206 r0_r = r0_r_byte0 << 24 | r0_r_byte1 << 16 | r0_r_byte2 << 8 | r0_r_byte3;
1207 r0_r_integer = format / r0_r;
1208 r0_r_factor = (format * 10) / r0_r - r0_r_integer * 10;
1209
1210 dev_dbg(rt1318->component->dev, "r0_l_ch:%d.%d ohm\n", r0_l_integer, r0_l_factor);
1211 dev_dbg(rt1318->component->dev, "r0_r_ch:%d.%d ohm\n", r0_r_integer, r0_r_factor);
1212}
1213
1214static void rt1318_r0_restore(struct rt1318_priv *rt1318)
1215{
1216 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_24,
1217 (rt1318->pdata.init_r0_l >> 24) & 0xff);
1218 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_23_16,
1219 (rt1318->pdata.init_r0_l >> 16) & 0xff);
1220 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_15_8,
1221 (rt1318->pdata.init_r0_l >> 8) & 0xff);
1222 regmap_write(rt1318->regmap, RT1318_PRE_R0_L_7_0,
1223 (rt1318->pdata.init_r0_l >> 0) & 0xff);
1224 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_24,
1225 (rt1318->pdata.init_r0_r >> 24) & 0xff);
1226 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_23_16,
1227 (rt1318->pdata.init_r0_r >> 16) & 0xff);
1228 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_15_8,
1229 (rt1318->pdata.init_r0_r >> 8) & 0xff);
1230 regmap_write(rt1318->regmap, RT1318_PRE_R0_R_7_0,
1231 (rt1318->pdata.init_r0_r >> 0) & 0xff);
1232 regmap_write(rt1318->regmap, RT1318_STP_SEL_L, 0x80);
1233 regmap_write(rt1318->regmap, RT1318_STP_SEL_R, 0x80);
1234 regmap_write(rt1318->regmap, RT1318_R0_CMP_L_FLAG, 0xc0);
1235 regmap_write(rt1318->regmap, RT1318_R0_CMP_R_FLAG, 0xc0);
1236 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_L, 0xc0);
1237 regmap_write(rt1318->regmap, RT1318_STP_R0_EN_R, 0xc0);
1238 regmap_write(rt1318->regmap, RT1318_STP_TEMP_L, 0xcc);
1239 regmap_write(rt1318->regmap, RT1318_TCON, 0x9c);
1240}
1241
1242static int rt1318_calibrate(struct rt1318_priv *rt1318)
1243{
1244 int chk_cnt = 30, count = 0;
1245 int val, val2;
1246
1247 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x1);
1248 usleep_range(0, 10000);
1249 rt1318_calibration_sequence(rt1318);
1250
1251 while (count < chk_cnt) {
1252 msleep(100);
1253 regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1254 regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1255 val = (val >> 1) & 0x1;
1256 val2 = (val2 >> 1) & 0x1;
1257 if (val & val2) {
1258 dev_dbg(rt1318->component->dev, "Calibration done.\n");
1259 break;
1260 }
1261 count++;
1262 if (count == chk_cnt) {
1263 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1264 return RT1318_R0_CALIB_NOT_DONE;
1265 }
1266 }
1267 regmap_write(rt1318->regmap, RT1318_PWR_STA1, 0x0);
1268 regmap_read(rt1318->regmap, RT1318_R0_CMP_L_FLAG, &val);
1269 regmap_read(rt1318->regmap, RT1318_R0_CMP_R_FLAG, &val2);
1270 if ((val & 0x1) & (val2 & 0x1))
1271 return RT1318_R0_IN_RANGE;
1272 else
1273 return RT1318_R0_OUT_OF_RANGE;
1274}
1275
1276static void rt1318_calibration_work(struct work_struct *work)
1277{
1278 struct rt1318_priv *rt1318 =
1279 container_of(work, struct rt1318_priv, cali_work);
1280 int ret;
1281
1282 if (rt1318->pdata.init_r0_l && rt1318->pdata.init_r0_r)
1283 rt1318_r0_restore(rt1318);
1284 else {
1285 ret = rt1318_calibrate(rt1318);
1286 if (ret == RT1318_R0_IN_RANGE)
1287 rt1318_r0_calculate(rt1318);
1288 dev_dbg(rt1318->component->dev, "Calibrate R0 result:%d\n", ret);
1289 }
1290}
1291
1292static int rt1318_i2c_probe(struct i2c_client *i2c)
1293{
1294 struct rt1318_platform_data *pdata = dev_get_platdata(&i2c->dev);
1295 struct rt1318_priv *rt1318;
1296 int ret, val, val2, dev_id;
1297
1298 rt1318 = devm_kzalloc(&i2c->dev, sizeof(struct rt1318_priv),
1299 GFP_KERNEL);
1300 if (!rt1318)
1301 return -ENOMEM;
1302
1303 i2c_set_clientdata(i2c, rt1318);
1304
1305 if (pdata)
1306 rt1318->pdata = *pdata;
1307 else
1308 rt1318_parse_dt(rt1318, &i2c->dev);
1309
1310 rt1318->regmap = devm_regmap_init_i2c(i2c, &rt1318_regmap);
1311 if (IS_ERR(rt1318->regmap)) {
1312 ret = PTR_ERR(rt1318->regmap);
1313 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1314 ret);
1315 return ret;
1316 }
1317
1318 regmap_read(rt1318->regmap, RT1318_DEV_ID1, &val);
1319 regmap_read(rt1318->regmap, RT1318_DEV_ID2, &val2);
1320 dev_id = (val << 8) | val2;
1321 if (dev_id != 0x6821) {
1322 dev_err(&i2c->dev,
1323 "Device with ID register %#x is not rt1318\n",
1324 dev_id);
1325 return -ENODEV;
1326 }
1327
1328 ret = regmap_register_patch(rt1318->regmap, init_list,
1329 ARRAY_SIZE(init_list));
1330 if (ret != 0)
1331 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1332
1333 INIT_WORK(&rt1318->cali_work, rt1318_calibration_work);
1334
1335 return devm_snd_soc_register_component(&i2c->dev,
1336 &soc_component_dev_rt1318, rt1318_dai, ARRAY_SIZE(rt1318_dai));
1337}
1338
1339static struct i2c_driver rt1318_i2c_driver = {
1340 .driver = {
1341 .name = "rt1318",
1342 .of_match_table = of_match_ptr(rt1318_of_match),
1343 .acpi_match_table = ACPI_PTR(rt1318_acpi_match),
1344 },
1345 .probe = rt1318_i2c_probe,
1346 .id_table = rt1318_i2c_id,
1347};
1348module_i2c_driver(rt1318_i2c_driver);
1349
1350MODULE_DESCRIPTION("ASoC RT1318 driver");
1351MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1352MODULE_LICENSE("GPL");