tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / sound / soc / codecs / nau8822.c
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1// SPDX-License-Identifier: GPL-2.0 2// 3// nau8822.c -- NAU8822 ALSA Soc Audio driver 4// 5// Copyright 2017 Nuvoton Technology Crop. 6// 7// Author: David Lin <ctlin0@nuvoton.com> 8// Co-author: John Hsu <kchsu0@nuvoton.com> 9// Co-author: Seven Li <wtli@nuvoton.com> 10// 11// Based on WM8974.c 12 13#include <linux/module.h> 14#include <linux/moduleparam.h> 15#include <linux/kernel.h> 16#include <linux/init.h> 17#include <linux/clk.h> 18#include <linux/delay.h> 19#include <linux/pm.h> 20#include <linux/i2c.h> 21#include <linux/regmap.h> 22#include <linux/slab.h> 23#include <sound/core.h> 24#include <sound/pcm.h> 25#include <sound/pcm_params.h> 26#include <sound/soc.h> 27#include <sound/initval.h> 28#include <sound/tlv.h> 29#include <asm/div64.h> 30#include "nau8822.h" 31 32#define NAU_PLL_FREQ_MAX 100000000 33#define NAU_PLL_FREQ_MIN 90000000 34#define NAU_PLL_REF_MAX 33000000 35#define NAU_PLL_REF_MIN 8000000 36#define NAU_PLL_OPTOP_MIN 6 37 38static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 }; 39 40static const struct reg_default nau8822_reg_defaults[] = { 41 { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 }, 42 { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 }, 43 { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 }, 44 { NAU8822_REG_AUDIO_INTERFACE, 0x0050 }, 45 { NAU8822_REG_COMPANDING_CONTROL, 0x0000 }, 46 { NAU8822_REG_CLOCKING, 0x0140 }, 47 { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 }, 48 { NAU8822_REG_GPIO_CONTROL, 0x0000 }, 49 { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 }, 50 { NAU8822_REG_DAC_CONTROL, 0x0000 }, 51 { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff }, 52 { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff }, 53 { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 }, 54 { NAU8822_REG_ADC_CONTROL, 0x0100 }, 55 { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff }, 56 { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff }, 57 { NAU8822_REG_EQ1, 0x012c }, 58 { NAU8822_REG_EQ2, 0x002c }, 59 { NAU8822_REG_EQ3, 0x002c }, 60 { NAU8822_REG_EQ4, 0x002c }, 61 { NAU8822_REG_EQ5, 0x002c }, 62 { NAU8822_REG_DAC_LIMITER_1, 0x0032 }, 63 { NAU8822_REG_DAC_LIMITER_2, 0x0000 }, 64 { NAU8822_REG_NOTCH_FILTER_1, 0x0000 }, 65 { NAU8822_REG_NOTCH_FILTER_2, 0x0000 }, 66 { NAU8822_REG_NOTCH_FILTER_3, 0x0000 }, 67 { NAU8822_REG_NOTCH_FILTER_4, 0x0000 }, 68 { NAU8822_REG_ALC_CONTROL_1, 0x0038 }, 69 { NAU8822_REG_ALC_CONTROL_2, 0x000b }, 70 { NAU8822_REG_ALC_CONTROL_3, 0x0032 }, 71 { NAU8822_REG_NOISE_GATE, 0x0010 }, 72 { NAU8822_REG_PLL_N, 0x0008 }, 73 { NAU8822_REG_PLL_K1, 0x000c }, 74 { NAU8822_REG_PLL_K2, 0x0093 }, 75 { NAU8822_REG_PLL_K3, 0x00e9 }, 76 { NAU8822_REG_3D_CONTROL, 0x0000 }, 77 { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 }, 78 { NAU8822_REG_INPUT_CONTROL, 0x0033 }, 79 { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 }, 80 { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 }, 81 { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 }, 82 { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 }, 83 { NAU8822_REG_OUTPUT_CONTROL, 0x0002 }, 84 { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 }, 85 { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 }, 86 { NAU8822_REG_LHP_VOLUME, 0x0039 }, 87 { NAU8822_REG_RHP_VOLUME, 0x0039 }, 88 { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 }, 89 { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 }, 90 { NAU8822_REG_AUX2_MIXER, 0x0001 }, 91 { NAU8822_REG_AUX1_MIXER, 0x0001 }, 92 { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 }, 93 { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 }, 94 { NAU8822_REG_MISC, 0x0020 }, 95 { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 }, 96 { NAU8822_REG_DEVICE_REVISION, 0x007f }, 97 { NAU8822_REG_DEVICE_ID, 0x001a }, 98 { NAU8822_REG_DAC_DITHER, 0x0114 }, 99 { NAU8822_REG_ALC_ENHANCE_1, 0x0000 }, 100 { NAU8822_REG_ALC_ENHANCE_2, 0x0000 }, 101 { NAU8822_REG_192KHZ_SAMPLING, 0x0008 }, 102 { NAU8822_REG_MISC_CONTROL, 0x0000 }, 103 { NAU8822_REG_INPUT_TIEOFF, 0x0000 }, 104 { NAU8822_REG_POWER_REDUCTION, 0x0000 }, 105 { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 }, 106 { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 }, 107 { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 }, 108 { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 }, 109}; 110 111static bool nau8822_readable_reg(struct device *dev, unsigned int reg) 112{ 113 switch (reg) { 114 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1: 115 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME: 116 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME: 117 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5: 118 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2: 119 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4: 120 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3: 121 case NAU8822_REG_3D_CONTROL: 122 case NAU8822_REG_RIGHT_SPEAKER_CONTROL: 123 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL: 124 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER: 125 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID: 126 case NAU8822_REG_DAC_DITHER: 127 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL: 128 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF: 129 return true; 130 default: 131 return false; 132 } 133} 134 135static bool nau8822_writeable_reg(struct device *dev, unsigned int reg) 136{ 137 switch (reg) { 138 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1: 139 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME: 140 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME: 141 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5: 142 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2: 143 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4: 144 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3: 145 case NAU8822_REG_3D_CONTROL: 146 case NAU8822_REG_RIGHT_SPEAKER_CONTROL: 147 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL: 148 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER: 149 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID: 150 case NAU8822_REG_DAC_DITHER: 151 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL: 152 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF: 153 return true; 154 default: 155 return false; 156 } 157} 158 159static bool nau8822_volatile(struct device *dev, unsigned int reg) 160{ 161 switch (reg) { 162 case NAU8822_REG_RESET: 163 case NAU8822_REG_DEVICE_REVISION: 164 case NAU8822_REG_DEVICE_ID: 165 case NAU8822_REG_AGC_PEAK2PEAK: 166 case NAU8822_REG_AGC_PEAK_DETECT: 167 case NAU8822_REG_AUTOMUTE_CONTROL: 168 return true; 169 default: 170 return false; 171 } 172} 173 174/* The EQ parameters get function is to get the 5 band equalizer control. 175 * The regmap raw read can't work here because regmap doesn't provide 176 * value format for value width of 9 bits. Therefore, the driver reads data 177 * from cache and makes value format according to the endianness of 178 * bytes type control element. 179 */ 180static int nau8822_eq_get(struct snd_kcontrol *kcontrol, 181 struct snd_ctl_elem_value *ucontrol) 182{ 183 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 184 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 185 int i, reg; 186 u16 reg_val, *val; 187 __be16 tmp; 188 189 val = (u16 *)ucontrol->value.bytes.data; 190 reg = NAU8822_REG_EQ1; 191 for (i = 0; i < params->max / sizeof(u16); i++) { 192 reg_val = snd_soc_component_read(component, reg + i); 193 /* conversion of 16-bit integers between native CPU format 194 * and big endian format 195 */ 196 tmp = cpu_to_be16(reg_val); 197 memcpy(val + i, &tmp, sizeof(tmp)); 198 } 199 200 return 0; 201} 202 203/* The EQ parameters put function is to make configuration of 5 band equalizer 204 * control. These configuration includes central frequency, equalizer gain, 205 * cut-off frequency, bandwidth control, and equalizer path. 206 * The regmap raw write can't work here because regmap doesn't provide 207 * register and value format for register with address 7 bits and value 9 bits. 208 * Therefore, the driver makes value format according to the endianness of 209 * bytes type control element and writes data to codec. 210 */ 211static int nau8822_eq_put(struct snd_kcontrol *kcontrol, 212 struct snd_ctl_elem_value *ucontrol) 213{ 214 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 215 struct soc_bytes_ext *params = (void *)kcontrol->private_value; 216 void *data; 217 u16 *val, value; 218 int i, reg, ret; 219 __be16 *tmp; 220 221 data = kmemdup(ucontrol->value.bytes.data, 222 params->max, GFP_KERNEL | GFP_DMA); 223 if (!data) 224 return -ENOMEM; 225 226 val = (u16 *)data; 227 reg = NAU8822_REG_EQ1; 228 for (i = 0; i < params->max / sizeof(u16); i++) { 229 /* conversion of 16-bit integers between native CPU format 230 * and big endian format 231 */ 232 tmp = (__be16 *)(val + i); 233 value = be16_to_cpup(tmp); 234 ret = snd_soc_component_write(component, reg + i, value); 235 if (ret) { 236 dev_err(component->dev, 237 "EQ configuration fail, register: %x ret: %d\n", 238 reg + i, ret); 239 kfree(data); 240 return ret; 241 } 242 } 243 kfree(data); 244 245 return 0; 246} 247 248static const char * const nau8822_companding[] = { 249 "Off", "NC", "u-law", "A-law"}; 250 251static const struct soc_enum nau8822_companding_adc_enum = 252 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT, 253 ARRAY_SIZE(nau8822_companding), nau8822_companding); 254 255static const struct soc_enum nau8822_companding_dac_enum = 256 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT, 257 ARRAY_SIZE(nau8822_companding), nau8822_companding); 258 259static const char * const nau8822_eqmode[] = {"Capture", "Playback"}; 260 261static const struct soc_enum nau8822_eqmode_enum = 262 SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT, 263 ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode); 264 265static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"}; 266static const char * const nau8822_alc3[] = {"Normal", "Limiter"}; 267 268static const struct soc_enum nau8822_alc_enable_enum = 269 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT, 270 ARRAY_SIZE(nau8822_alc1), nau8822_alc1); 271 272static const struct soc_enum nau8822_alc_mode_enum = 273 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT, 274 ARRAY_SIZE(nau8822_alc3), nau8822_alc3); 275 276static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1); 277static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0); 278static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0); 279static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0); 280static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1); 281static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0); 282 283static const struct snd_kcontrol_new nau8822_snd_controls[] = { 284 SOC_ENUM("ADC Companding", nau8822_companding_adc_enum), 285 SOC_ENUM("DAC Companding", nau8822_companding_dac_enum), 286 287 SOC_ENUM("EQ Function", nau8822_eqmode_enum), 288 SND_SOC_BYTES_EXT("EQ Parameters", 10, 289 nau8822_eq_get, nau8822_eq_put), 290 291 SOC_DOUBLE("DAC Inversion Switch", 292 NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0), 293 SOC_DOUBLE_R_TLV("PCM Volume", 294 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 295 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv), 296 297 SOC_SINGLE("High Pass Filter Switch", 298 NAU8822_REG_ADC_CONTROL, 8, 1, 0), 299 SOC_SINGLE("High Pass Cut Off", 300 NAU8822_REG_ADC_CONTROL, 4, 7, 0), 301 302 SOC_DOUBLE("ADC Inversion Switch", 303 NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0), 304 SOC_DOUBLE_R_TLV("ADC Volume", 305 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 306 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv), 307 308 SOC_SINGLE("DAC Limiter Switch", 309 NAU8822_REG_DAC_LIMITER_1, 8, 1, 0), 310 SOC_SINGLE("DAC Limiter Decay", 311 NAU8822_REG_DAC_LIMITER_1, 4, 15, 0), 312 SOC_SINGLE("DAC Limiter Attack", 313 NAU8822_REG_DAC_LIMITER_1, 0, 15, 0), 314 SOC_SINGLE("DAC Limiter Threshold", 315 NAU8822_REG_DAC_LIMITER_2, 4, 7, 0), 316 SOC_SINGLE_TLV("DAC Limiter Volume", 317 NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv), 318 319 SOC_ENUM("ALC Mode", nau8822_alc_mode_enum), 320 SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum), 321 SOC_SINGLE("ALC Min Gain", 322 NAU8822_REG_ALC_CONTROL_1, 0, 7, 0), 323 SOC_SINGLE("ALC Max Gain", 324 NAU8822_REG_ALC_CONTROL_1, 3, 7, 0), 325 SOC_SINGLE("ALC Hold", 326 NAU8822_REG_ALC_CONTROL_2, 4, 10, 0), 327 SOC_SINGLE("ALC Target", 328 NAU8822_REG_ALC_CONTROL_2, 0, 15, 0), 329 SOC_SINGLE("ALC Decay", 330 NAU8822_REG_ALC_CONTROL_3, 4, 10, 0), 331 SOC_SINGLE("ALC Attack", 332 NAU8822_REG_ALC_CONTROL_3, 0, 10, 0), 333 SOC_SINGLE("ALC Noise Gate Switch", 334 NAU8822_REG_NOISE_GATE, 3, 1, 0), 335 SOC_SINGLE("ALC Noise Gate Threshold", 336 NAU8822_REG_NOISE_GATE, 0, 7, 0), 337 338 SOC_DOUBLE_R("PGA ZC Switch", 339 NAU8822_REG_LEFT_INP_PGA_CONTROL, 340 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 341 7, 1, 0), 342 SOC_DOUBLE_R_TLV("PGA Volume", 343 NAU8822_REG_LEFT_INP_PGA_CONTROL, 344 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv), 345 346 SOC_DOUBLE_R("Headphone ZC Switch", 347 NAU8822_REG_LHP_VOLUME, 348 NAU8822_REG_RHP_VOLUME, 7, 1, 0), 349 SOC_DOUBLE_R("Headphone Playback Switch", 350 NAU8822_REG_LHP_VOLUME, 351 NAU8822_REG_RHP_VOLUME, 6, 1, 1), 352 SOC_DOUBLE_R_TLV("Headphone Volume", 353 NAU8822_REG_LHP_VOLUME, 354 NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv), 355 356 SOC_DOUBLE_R("Speaker ZC Switch", 357 NAU8822_REG_LSPKOUT_VOLUME, 358 NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0), 359 SOC_DOUBLE_R("Speaker Playback Switch", 360 NAU8822_REG_LSPKOUT_VOLUME, 361 NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1), 362 SOC_DOUBLE_R_TLV("Speaker Volume", 363 NAU8822_REG_LSPKOUT_VOLUME, 364 NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv), 365 366 SOC_DOUBLE_R("AUXOUT Playback Switch", 367 NAU8822_REG_AUX2_MIXER, 368 NAU8822_REG_AUX1_MIXER, 6, 1, 1), 369 370 SOC_DOUBLE_R_TLV("PGA Boost Volume", 371 NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 372 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv), 373 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume", 374 NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 375 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv), 376 SOC_DOUBLE_R_TLV("Aux Boost Volume", 377 NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 378 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv), 379 380 SOC_SINGLE("DAC 128x Oversampling Switch", 381 NAU8822_REG_DAC_CONTROL, 5, 1, 0), 382 SOC_SINGLE("ADC 128x Oversampling Switch", 383 NAU8822_REG_ADC_CONTROL, 5, 1, 0), 384}; 385 386/* LMAIN and RMAIN Mixer */ 387static const struct snd_kcontrol_new nau8822_left_out_mixer[] = { 388 SOC_DAPM_SINGLE("LINMIX Switch", 389 NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0), 390 SOC_DAPM_SINGLE("LAUX Switch", 391 NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0), 392 SOC_DAPM_SINGLE("LDAC Switch", 393 NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0), 394 SOC_DAPM_SINGLE("RDAC Switch", 395 NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0), 396}; 397 398static const struct snd_kcontrol_new nau8822_right_out_mixer[] = { 399 SOC_DAPM_SINGLE("RINMIX Switch", 400 NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0), 401 SOC_DAPM_SINGLE("RAUX Switch", 402 NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0), 403 SOC_DAPM_SINGLE("RDAC Switch", 404 NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0), 405 SOC_DAPM_SINGLE("LDAC Switch", 406 NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0), 407}; 408 409/* AUX1 and AUX2 Mixer */ 410static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = { 411 SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0), 412 SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0), 413 SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0), 414 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0), 415 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0), 416}; 417 418static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = { 419 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0), 420 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0), 421 SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0), 422 SOC_DAPM_SINGLE("AUX1MIX Output Switch", 423 NAU8822_REG_AUX2_MIXER, 3, 1, 0), 424}; 425 426/* Input PGA */ 427static const struct snd_kcontrol_new nau8822_left_input_mixer[] = { 428 SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0), 429 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0), 430 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0), 431}; 432static const struct snd_kcontrol_new nau8822_right_input_mixer[] = { 433 SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0), 434 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0), 435 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0), 436}; 437 438/* Loopback Switch */ 439static const struct snd_kcontrol_new nau8822_loopback = 440 SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL, 441 NAU8822_ADDAP_SFT, 1, 0); 442 443static int check_mclk_select_pll(struct snd_soc_dapm_widget *source, 444 struct snd_soc_dapm_widget *sink) 445{ 446 struct snd_soc_component *component = 447 snd_soc_dapm_to_component(source->dapm); 448 unsigned int value; 449 450 value = snd_soc_component_read(component, NAU8822_REG_CLOCKING); 451 452 return (value & NAU8822_CLKM_MASK); 453} 454 455static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = { 456 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", 457 NAU8822_REG_POWER_MANAGEMENT_3, 0, 0), 458 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", 459 NAU8822_REG_POWER_MANAGEMENT_3, 1, 0), 460 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture", 461 NAU8822_REG_POWER_MANAGEMENT_2, 0, 0), 462 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture", 463 NAU8822_REG_POWER_MANAGEMENT_2, 1, 0), 464 465 SOC_MIXER_ARRAY("Left Output Mixer", 466 NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer), 467 SOC_MIXER_ARRAY("Right Output Mixer", 468 NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer), 469 SOC_MIXER_ARRAY("AUX1 Output Mixer", 470 NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer), 471 SOC_MIXER_ARRAY("AUX2 Output Mixer", 472 NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer), 473 474 SOC_MIXER_ARRAY("Left Input Mixer", 475 NAU8822_REG_POWER_MANAGEMENT_2, 476 2, 0, nau8822_left_input_mixer), 477 SOC_MIXER_ARRAY("Right Input Mixer", 478 NAU8822_REG_POWER_MANAGEMENT_2, 479 3, 0, nau8822_right_input_mixer), 480 481 SND_SOC_DAPM_PGA("Left Boost Mixer", 482 NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0), 483 SND_SOC_DAPM_PGA("Right Boost Mixer", 484 NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0), 485 486 SND_SOC_DAPM_PGA("Left Capture PGA", 487 NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0), 488 SND_SOC_DAPM_PGA("Right Capture PGA", 489 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0), 490 491 SND_SOC_DAPM_PGA("Left Headphone Out", 492 NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0), 493 SND_SOC_DAPM_PGA("Right Headphone Out", 494 NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0), 495 496 SND_SOC_DAPM_PGA("Left Speaker Out", 497 NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0), 498 SND_SOC_DAPM_PGA("Right Speaker Out", 499 NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0), 500 501 SND_SOC_DAPM_PGA("AUX1 Out", 502 NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0), 503 SND_SOC_DAPM_PGA("AUX2 Out", 504 NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0), 505 506 SND_SOC_DAPM_SUPPLY("Mic Bias", 507 NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0), 508 SND_SOC_DAPM_SUPPLY("PLL", 509 NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0), 510 511 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0, 512 &nau8822_loopback), 513 514 SND_SOC_DAPM_INPUT("LMICN"), 515 SND_SOC_DAPM_INPUT("LMICP"), 516 SND_SOC_DAPM_INPUT("RMICN"), 517 SND_SOC_DAPM_INPUT("RMICP"), 518 SND_SOC_DAPM_INPUT("LAUX"), 519 SND_SOC_DAPM_INPUT("RAUX"), 520 SND_SOC_DAPM_INPUT("L2"), 521 SND_SOC_DAPM_INPUT("R2"), 522 SND_SOC_DAPM_OUTPUT("LHP"), 523 SND_SOC_DAPM_OUTPUT("RHP"), 524 SND_SOC_DAPM_OUTPUT("LSPK"), 525 SND_SOC_DAPM_OUTPUT("RSPK"), 526 SND_SOC_DAPM_OUTPUT("AUXOUT1"), 527 SND_SOC_DAPM_OUTPUT("AUXOUT2"), 528}; 529 530static const struct snd_soc_dapm_route nau8822_dapm_routes[] = { 531 {"Right DAC", NULL, "PLL", check_mclk_select_pll}, 532 {"Left DAC", NULL, "PLL", check_mclk_select_pll}, 533 534 /* LMAIN and RMAIN Mixer */ 535 {"Right Output Mixer", "LDAC Switch", "Left DAC"}, 536 {"Right Output Mixer", "RDAC Switch", "Right DAC"}, 537 {"Right Output Mixer", "RAUX Switch", "RAUX"}, 538 {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"}, 539 540 {"Left Output Mixer", "LDAC Switch", "Left DAC"}, 541 {"Left Output Mixer", "RDAC Switch", "Right DAC"}, 542 {"Left Output Mixer", "LAUX Switch", "LAUX"}, 543 {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"}, 544 545 /* AUX1 and AUX2 Mixer */ 546 {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"}, 547 {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"}, 548 {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"}, 549 {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"}, 550 {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"}, 551 552 {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"}, 553 {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"}, 554 {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"}, 555 {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"}, 556 557 /* Outputs */ 558 {"Right Headphone Out", NULL, "Right Output Mixer"}, 559 {"RHP", NULL, "Right Headphone Out"}, 560 561 {"Left Headphone Out", NULL, "Left Output Mixer"}, 562 {"LHP", NULL, "Left Headphone Out"}, 563 564 {"Right Speaker Out", NULL, "Right Output Mixer"}, 565 {"RSPK", NULL, "Right Speaker Out"}, 566 567 {"Left Speaker Out", NULL, "Left Output Mixer"}, 568 {"LSPK", NULL, "Left Speaker Out"}, 569 570 {"AUX1 Out", NULL, "AUX1 Output Mixer"}, 571 {"AUX2 Out", NULL, "AUX2 Output Mixer"}, 572 {"AUXOUT1", NULL, "AUX1 Out"}, 573 {"AUXOUT2", NULL, "AUX2 Out"}, 574 575 /* Boost Mixer */ 576 {"Right ADC", NULL, "PLL", check_mclk_select_pll}, 577 {"Left ADC", NULL, "PLL", check_mclk_select_pll}, 578 579 {"Right ADC", NULL, "Right Boost Mixer"}, 580 581 {"Right Boost Mixer", NULL, "RAUX"}, 582 {"Right Boost Mixer", NULL, "Right Capture PGA"}, 583 {"Right Boost Mixer", NULL, "R2"}, 584 585 {"Left ADC", NULL, "Left Boost Mixer"}, 586 587 {"Left Boost Mixer", NULL, "LAUX"}, 588 {"Left Boost Mixer", NULL, "Left Capture PGA"}, 589 {"Left Boost Mixer", NULL, "L2"}, 590 591 /* Input PGA */ 592 {"Right Capture PGA", NULL, "Right Input Mixer"}, 593 {"Left Capture PGA", NULL, "Left Input Mixer"}, 594 595 /* Enable Microphone Power */ 596 {"Right Capture PGA", NULL, "Mic Bias"}, 597 {"Left Capture PGA", NULL, "Mic Bias"}, 598 599 {"Right Input Mixer", "R2 Switch", "R2"}, 600 {"Right Input Mixer", "MicN Switch", "RMICN"}, 601 {"Right Input Mixer", "MicP Switch", "RMICP"}, 602 603 {"Left Input Mixer", "L2 Switch", "L2"}, 604 {"Left Input Mixer", "MicN Switch", "LMICN"}, 605 {"Left Input Mixer", "MicP Switch", "LMICP"}, 606 607 /* Digital Loopback */ 608 {"Digital Loopback", "Switch", "Left ADC"}, 609 {"Digital Loopback", "Switch", "Right ADC"}, 610 {"Left DAC", NULL, "Digital Loopback"}, 611 {"Right DAC", NULL, "Digital Loopback"}, 612}; 613 614static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs, 615 struct nau8822_pll *pll_param) 616{ 617 u64 f2, f2_max, pll_ratio; 618 int i, scal_sel; 619 620 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN) 621 return -EINVAL; 622 f2_max = 0; 623 scal_sel = ARRAY_SIZE(nau8822_mclk_scaler); 624 625 for (i = 0; i < scal_sel; i++) { 626 f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10; 627 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX && 628 f2_max < f2) { 629 f2_max = f2; 630 scal_sel = i; 631 } 632 } 633 634 if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel) 635 return -EINVAL; 636 pll_param->mclk_scaler = scal_sel; 637 f2 = f2_max; 638 639 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional 640 * input; round up the 24+4bit. 641 */ 642 pll_ratio = div_u64(f2 << 28, pll_in); 643 pll_param->pre_factor = 0; 644 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) { 645 pll_ratio <<= 1; 646 pll_param->pre_factor = 1; 647 } 648 pll_param->pll_int = (pll_ratio >> 28) & 0xF; 649 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4); 650 651 return 0; 652} 653 654static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate) 655{ 656 struct snd_soc_component *component = dai->component; 657 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 658 struct nau8822_pll *pll = &nau8822->pll; 659 int i, sclk, imclk; 660 661 switch (nau8822->div_id) { 662 case NAU8822_CLK_MCLK: 663 /* Configure the master clock prescaler div to make system 664 * clock to approximate the internal master clock (IMCLK); 665 * and large or equal to IMCLK. 666 */ 667 div = 0; 668 imclk = rate * 256; 669 for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) { 670 sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i]; 671 if (sclk < imclk) 672 break; 673 div = i; 674 } 675 dev_dbg(component->dev, "master clock prescaler %x for fs %d\n", 676 div, rate); 677 678 /* master clock from MCLK and disable PLL */ 679 snd_soc_component_update_bits(component, 680 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, 681 (div << NAU8822_MCLKSEL_SFT)); 682 snd_soc_component_update_bits(component, 683 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, 684 NAU8822_CLKM_MCLK); 685 break; 686 687 case NAU8822_CLK_PLL: 688 /* master clock from PLL and enable PLL */ 689 if (pll->mclk_scaler != div) { 690 dev_err(component->dev, 691 "master clock prescaler not meet PLL parameters\n"); 692 return -EINVAL; 693 } 694 snd_soc_component_update_bits(component, 695 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, 696 (div << NAU8822_MCLKSEL_SFT)); 697 snd_soc_component_update_bits(component, 698 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, 699 NAU8822_CLKM_PLL); 700 break; 701 702 default: 703 return -EINVAL; 704 } 705 706 return 0; 707} 708 709static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source, 710 unsigned int freq_in, unsigned int freq_out) 711{ 712 struct snd_soc_component *component = dai->component; 713 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 714 struct nau8822_pll *pll_param = &nau8822->pll; 715 int ret, fs; 716 717 if (freq_in == pll_param->freq_in && 718 freq_out == pll_param->freq_out) 719 return 0; 720 721 if (freq_out == 0) { 722 dev_dbg(component->dev, "PLL disabled\n"); 723 snd_soc_component_update_bits(component, 724 NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF); 725 return 0; 726 } 727 728 fs = freq_out / 256; 729 730 ret = nau8822_calc_pll(freq_in, fs, pll_param); 731 if (ret < 0) { 732 dev_err(component->dev, "Unsupported input clock %d\n", 733 freq_in); 734 return ret; 735 } 736 737 dev_dbg(component->dev, 738 "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n", 739 pll_param->pll_int, pll_param->pll_frac, 740 pll_param->mclk_scaler, pll_param->pre_factor); 741 742 snd_soc_component_update_bits(component, 743 NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_OFF); 744 snd_soc_component_update_bits(component, 745 NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK, 746 (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) | 747 pll_param->pll_int); 748 snd_soc_component_write(component, 749 NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) & 750 NAU8822_PLLK1_MASK); 751 snd_soc_component_write(component, 752 NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) & 753 NAU8822_PLLK2_MASK); 754 snd_soc_component_write(component, 755 NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK); 756 snd_soc_component_update_bits(component, 757 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK, 758 pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT); 759 snd_soc_component_update_bits(component, 760 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL); 761 snd_soc_component_update_bits(component, 762 NAU8822_REG_POWER_MANAGEMENT_1, NAU8822_PLL_EN_MASK, NAU8822_PLL_ON); 763 764 pll_param->freq_in = freq_in; 765 pll_param->freq_out = freq_out; 766 767 return 0; 768} 769 770static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 771 unsigned int freq, int dir) 772{ 773 struct snd_soc_component *component = dai->component; 774 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 775 unsigned long mclk_freq; 776 777 nau8822->div_id = clk_id; 778 nau8822->sysclk = freq; 779 780 if (nau8822->mclk) { 781 mclk_freq = clk_get_rate(nau8822->mclk); 782 if (mclk_freq != freq) { 783 int ret = nau8822_set_pll(dai, NAU8822_CLK_MCLK, 784 NAU8822_CLK_MCLK, mclk_freq, freq); 785 if (ret) { 786 dev_err(component->dev, "Failed to set PLL\n"); 787 return ret; 788 } 789 nau8822->div_id = NAU8822_CLK_PLL; 790 } 791 } 792 793 dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq, 794 nau8822->div_id == NAU8822_CLK_PLL ? "PLL" : "MCLK"); 795 796 return 0; 797} 798 799static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 800{ 801 struct snd_soc_component *component = dai->component; 802 u16 ctrl1_val = 0, ctrl2_val = 0; 803 804 dev_dbg(component->dev, "%s\n", __func__); 805 806 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 807 case SND_SOC_DAIFMT_CBP_CFP: 808 ctrl2_val |= 1; 809 break; 810 case SND_SOC_DAIFMT_CBC_CFC: 811 ctrl2_val &= ~1; 812 break; 813 default: 814 return -EINVAL; 815 } 816 817 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 818 case SND_SOC_DAIFMT_I2S: 819 ctrl1_val |= 0x10; 820 break; 821 case SND_SOC_DAIFMT_RIGHT_J: 822 break; 823 case SND_SOC_DAIFMT_LEFT_J: 824 ctrl1_val |= 0x8; 825 break; 826 case SND_SOC_DAIFMT_DSP_A: 827 ctrl1_val |= 0x18; 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 834 case SND_SOC_DAIFMT_NB_NF: 835 break; 836 case SND_SOC_DAIFMT_IB_IF: 837 ctrl1_val |= 0x180; 838 break; 839 case SND_SOC_DAIFMT_IB_NF: 840 ctrl1_val |= 0x100; 841 break; 842 case SND_SOC_DAIFMT_NB_IF: 843 ctrl1_val |= 0x80; 844 break; 845 default: 846 return -EINVAL; 847 } 848 849 snd_soc_component_update_bits(component, 850 NAU8822_REG_AUDIO_INTERFACE, 851 NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK, 852 ctrl1_val); 853 snd_soc_component_update_bits(component, 854 NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val); 855 856 return 0; 857} 858 859static int nau8822_hw_params(struct snd_pcm_substream *substream, 860 struct snd_pcm_hw_params *params, 861 struct snd_soc_dai *dai) 862{ 863 struct snd_soc_component *component = dai->component; 864 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 865 int div = 0, val_len = 0, val_rate = 0; 866 unsigned int ctrl_val, bclk_fs, bclk_div; 867 868 /* make BCLK and LRC divide configuration if the codec as master. */ 869 ctrl_val = snd_soc_component_read(component, NAU8822_REG_CLOCKING); 870 if (ctrl_val & NAU8822_CLK_MASTER) { 871 /* get the bclk and fs ratio */ 872 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params); 873 if (bclk_fs <= 32) 874 bclk_div = NAU8822_BCLKDIV_8; 875 else if (bclk_fs <= 64) 876 bclk_div = NAU8822_BCLKDIV_4; 877 else if (bclk_fs <= 128) 878 bclk_div = NAU8822_BCLKDIV_2; 879 else 880 return -EINVAL; 881 snd_soc_component_update_bits(component, NAU8822_REG_CLOCKING, 882 NAU8822_BCLKSEL_MASK, bclk_div); 883 } 884 885 switch (params_format(params)) { 886 case SNDRV_PCM_FORMAT_S16_LE: 887 break; 888 case SNDRV_PCM_FORMAT_S20_3LE: 889 val_len |= NAU8822_WLEN_20; 890 break; 891 case SNDRV_PCM_FORMAT_S24_LE: 892 val_len |= NAU8822_WLEN_24; 893 break; 894 case SNDRV_PCM_FORMAT_S32_LE: 895 val_len |= NAU8822_WLEN_32; 896 break; 897 default: 898 return -EINVAL; 899 } 900 901 switch (params_rate(params)) { 902 case 8000: 903 val_rate |= NAU8822_SMPLR_8K; 904 break; 905 case 11025: 906 val_rate |= NAU8822_SMPLR_12K; 907 break; 908 case 16000: 909 val_rate |= NAU8822_SMPLR_16K; 910 break; 911 case 22050: 912 val_rate |= NAU8822_SMPLR_24K; 913 break; 914 case 32000: 915 val_rate |= NAU8822_SMPLR_32K; 916 break; 917 case 44100: 918 case 48000: 919 break; 920 default: 921 return -EINVAL; 922 } 923 924 snd_soc_component_update_bits(component, 925 NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len); 926 snd_soc_component_update_bits(component, 927 NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate); 928 929 /* If the master clock is from MCLK, provide the runtime FS for driver 930 * to get the master clock prescaler configuration. 931 */ 932 if (nau8822->div_id != NAU8822_CLK_MCLK) 933 div = nau8822->pll.mclk_scaler; 934 935 nau8822_config_clkdiv(dai, div, params_rate(params)); 936 937 return 0; 938} 939 940static int nau8822_mute(struct snd_soc_dai *dai, int mute, int direction) 941{ 942 struct snd_soc_component *component = dai->component; 943 944 dev_dbg(component->dev, "%s: %d\n", __func__, mute); 945 946 if (mute) 947 snd_soc_component_update_bits(component, 948 NAU8822_REG_DAC_CONTROL, 0x40, 0x40); 949 else 950 snd_soc_component_update_bits(component, 951 NAU8822_REG_DAC_CONTROL, 0x40, 0); 952 953 return 0; 954} 955 956static int nau8822_set_bias_level(struct snd_soc_component *component, 957 enum snd_soc_bias_level level) 958{ 959 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 960 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 961 962 switch (level) { 963 case SND_SOC_BIAS_ON: 964 break; 965 966 case SND_SOC_BIAS_PREPARE: 967 if (nau8822->mclk && 968 snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_ON) { 969 int ret = clk_prepare_enable(nau8822->mclk); 970 971 if (ret) { 972 dev_err(component->dev, 973 "Failed to enable MCLK: %d\n", ret); 974 return ret; 975 } 976 } 977 978 snd_soc_component_update_bits(component, 979 NAU8822_REG_POWER_MANAGEMENT_1, 980 NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K); 981 break; 982 983 case SND_SOC_BIAS_STANDBY: 984 if (nau8822->mclk && 985 snd_soc_dapm_get_bias_level(dapm) != SND_SOC_BIAS_OFF) 986 clk_disable_unprepare(nau8822->mclk); 987 988 snd_soc_component_update_bits(component, 989 NAU8822_REG_POWER_MANAGEMENT_1, 990 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN, 991 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN); 992 993 if (snd_soc_dapm_get_bias_level(dapm) == SND_SOC_BIAS_OFF) { 994 snd_soc_component_update_bits(component, 995 NAU8822_REG_POWER_MANAGEMENT_1, 996 NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K); 997 mdelay(100); 998 } 999 snd_soc_component_update_bits(component, 1000 NAU8822_REG_POWER_MANAGEMENT_1, 1001 NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K); 1002 break; 1003 1004 case SND_SOC_BIAS_OFF: 1005 snd_soc_component_write(component, 1006 NAU8822_REG_POWER_MANAGEMENT_1, 0); 1007 snd_soc_component_write(component, 1008 NAU8822_REG_POWER_MANAGEMENT_2, 0); 1009 snd_soc_component_write(component, 1010 NAU8822_REG_POWER_MANAGEMENT_3, 0); 1011 break; 1012 } 1013 1014 dev_dbg(component->dev, "%s: %d\n", __func__, level); 1015 1016 return 0; 1017} 1018 1019#define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000) 1020 1021#define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 1022 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1023 1024static const struct snd_soc_dai_ops nau8822_dai_ops = { 1025 .hw_params = nau8822_hw_params, 1026 .mute_stream = nau8822_mute, 1027 .set_fmt = nau8822_set_dai_fmt, 1028 .set_sysclk = nau8822_set_dai_sysclk, 1029 .set_pll = nau8822_set_pll, 1030 .no_capture_mute = 1, 1031}; 1032 1033static struct snd_soc_dai_driver nau8822_dai = { 1034 .name = "nau8822-hifi", 1035 .playback = { 1036 .stream_name = "Playback", 1037 .channels_min = 1, 1038 .channels_max = 2, 1039 .rates = NAU8822_RATES, 1040 .formats = NAU8822_FORMATS, 1041 }, 1042 .capture = { 1043 .stream_name = "Capture", 1044 .channels_min = 1, 1045 .channels_max = 2, 1046 .rates = NAU8822_RATES, 1047 .formats = NAU8822_FORMATS, 1048 }, 1049 .ops = &nau8822_dai_ops, 1050 .symmetric_rate = 1, 1051}; 1052 1053static int nau8822_suspend(struct snd_soc_component *component) 1054{ 1055 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 1056 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1057 1058 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_OFF); 1059 1060 regcache_mark_dirty(nau8822->regmap); 1061 1062 return 0; 1063} 1064 1065static int nau8822_resume(struct snd_soc_component *component) 1066{ 1067 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component); 1068 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1069 1070 regcache_sync(nau8822->regmap); 1071 1072 snd_soc_dapm_force_bias_level(dapm, SND_SOC_BIAS_STANDBY); 1073 1074 return 0; 1075} 1076 1077/* 1078 * These registers contain an "update" bit - bit 8. This means, for example, 1079 * that one can write new DAC digital volume for both channels, but only when 1080 * the update bit is set, will also the volume be updated - simultaneously for 1081 * both channels. 1082 */ 1083static const int update_reg[] = { 1084 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 1085 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 1086 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 1087 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 1088 NAU8822_REG_LEFT_INP_PGA_CONTROL, 1089 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 1090 NAU8822_REG_LHP_VOLUME, 1091 NAU8822_REG_RHP_VOLUME, 1092 NAU8822_REG_LSPKOUT_VOLUME, 1093 NAU8822_REG_RSPKOUT_VOLUME, 1094}; 1095 1096static int nau8822_probe(struct snd_soc_component *component) 1097{ 1098 int i; 1099 struct device_node *of_node = component->dev->of_node; 1100 1101 /* 1102 * Set the update bit in all registers, that have one. This way all 1103 * writes to those registers will also cause the update bit to be 1104 * written. 1105 */ 1106 for (i = 0; i < ARRAY_SIZE(update_reg); i++) 1107 snd_soc_component_update_bits(component, 1108 update_reg[i], 0x100, 0x100); 1109 1110 /* Check property to configure the two loudspeaker outputs as 1111 * a single Bridge Tied Load output 1112 */ 1113 if (of_property_read_bool(of_node, "nuvoton,spk-btl")) 1114 snd_soc_component_update_bits(component, 1115 NAU8822_REG_RIGHT_SPEAKER_CONTROL, 1116 NAU8822_RSUBBYP, NAU8822_RSUBBYP); 1117 1118 return 0; 1119} 1120 1121static const struct snd_soc_component_driver soc_component_dev_nau8822 = { 1122 .probe = nau8822_probe, 1123 .suspend = nau8822_suspend, 1124 .resume = nau8822_resume, 1125 .set_bias_level = nau8822_set_bias_level, 1126 .controls = nau8822_snd_controls, 1127 .num_controls = ARRAY_SIZE(nau8822_snd_controls), 1128 .dapm_widgets = nau8822_dapm_widgets, 1129 .num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets), 1130 .dapm_routes = nau8822_dapm_routes, 1131 .num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes), 1132 .idle_bias_on = 1, 1133 .use_pmdown_time = 1, 1134 .endianness = 1, 1135}; 1136 1137static const struct regmap_config nau8822_regmap_config = { 1138 .reg_bits = 7, 1139 .val_bits = 9, 1140 1141 .max_register = NAU8822_REG_MAX_REGISTER, 1142 .volatile_reg = nau8822_volatile, 1143 1144 .readable_reg = nau8822_readable_reg, 1145 .writeable_reg = nau8822_writeable_reg, 1146 1147 .cache_type = REGCACHE_RBTREE, 1148 .reg_defaults = nau8822_reg_defaults, 1149 .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults), 1150}; 1151 1152static int nau8822_i2c_probe(struct i2c_client *i2c) 1153{ 1154 struct device *dev = &i2c->dev; 1155 struct nau8822 *nau8822 = dev_get_platdata(dev); 1156 int ret; 1157 1158 if (!nau8822) { 1159 nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL); 1160 if (nau8822 == NULL) 1161 return -ENOMEM; 1162 } 1163 i2c_set_clientdata(i2c, nau8822); 1164 1165 nau8822->mclk = devm_clk_get_optional(&i2c->dev, "mclk"); 1166 if (IS_ERR(nau8822->mclk)) 1167 return dev_err_probe(&i2c->dev, PTR_ERR(nau8822->mclk), 1168 "Error getting mclk\n"); 1169 1170 nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config); 1171 if (IS_ERR(nau8822->regmap)) { 1172 ret = PTR_ERR(nau8822->regmap); 1173 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 1174 return ret; 1175 } 1176 nau8822->dev = dev; 1177 1178 /* Reset the codec */ 1179 ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00); 1180 if (ret != 0) { 1181 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret); 1182 return ret; 1183 } 1184 1185 ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822, 1186 &nau8822_dai, 1); 1187 if (ret != 0) { 1188 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret); 1189 return ret; 1190 } 1191 1192 return 0; 1193} 1194 1195static const struct i2c_device_id nau8822_i2c_id[] = { 1196 { "nau8822" }, 1197 { } 1198}; 1199MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id); 1200 1201#ifdef CONFIG_OF 1202static const struct of_device_id nau8822_of_match[] = { 1203 { .compatible = "nuvoton,nau8822", }, 1204 { } 1205}; 1206MODULE_DEVICE_TABLE(of, nau8822_of_match); 1207#endif 1208 1209static struct i2c_driver nau8822_i2c_driver = { 1210 .driver = { 1211 .name = "nau8822", 1212 .of_match_table = of_match_ptr(nau8822_of_match), 1213 }, 1214 .probe = nau8822_i2c_probe, 1215 .id_table = nau8822_i2c_id, 1216}; 1217module_i2c_driver(nau8822_i2c_driver); 1218 1219MODULE_DESCRIPTION("ASoC NAU8822 codec driver"); 1220MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>"); 1221MODULE_LICENSE("GPL v2");