tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11#ifndef _ACP_IP_OFFSET_HEADER
12#define _ACP_IP_OFFSET_HEADER
13
14#define ACPAXI2AXI_ATU_CTRL 0xC40
15#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0xC00
16#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0xC04
17#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0xC08
18#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0xC0C
19#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0xC20
20#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0xC24
21
22#define GRP1_OFFSET 0x0
23#define GRP2_OFFSET 0x4000
24
25#define ACP_PGFSM_CONTROL 0x141C
26#define ACP_PGFSM_STATUS 0x1420
27#define ACP_SOFT_RESET 0x1000
28#define ACP_CONTROL 0x1004
29#define ACP_PIN_CONFIG 0x1440
30#define ACP3X_PIN_CONFIG 0x1400
31
32#define ACP_EXTERNAL_INTR_REG_ADDR(chip, offset, ctrl) \
33 (chip->base + chip->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
34
35#define ACP_EXTERNAL_INTR_ENB(chip) ACP_EXTERNAL_INTR_REG_ADDR(chip, 0x0, 0x0)
36#define ACP_EXTERNAL_INTR_CNTL(chip, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(chip, 0x4, ctrl)
37#define ACP_EXTERNAL_INTR_STAT(chip, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(chip, \
38 (0x4 + (chip->rsrc->no_of_ctrls * 0x04)), ctrl)
39
40/* Registers from ACP_AUDIO_BUFFERS block */
41
42#define ACP_I2S_REG_ADDR(acp_adata, addr) \
43 ((addr) + (acp_adata->rsrc->irqp_used * \
44 acp_adata->rsrc->irq_reg_offset))
45
46#define ACP_I2S_RX_RINGBUFADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2000)
47#define ACP_I2S_RX_RINGBUFSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2004)
48#define ACP_I2S_RX_LINKPOSITIONCNTR(adata) ACP_I2S_REG_ADDR(adata, 0x2008)
49#define ACP_I2S_RX_FIFOADDR(adata) ACP_I2S_REG_ADDR(adata, 0x200C)
50#define ACP_I2S_RX_FIFOSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2010)
51#define ACP_I2S_RX_DMA_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2014)
52#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH(adata) ACP_I2S_REG_ADDR(adata, 0x2018)
53#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW(adata) ACP_I2S_REG_ADDR(adata, 0x201C)
54#define ACP_I2S_RX_INTR_WATERMARK_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2020)
55#define ACP_I2S_TX_RINGBUFADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2024)
56#define ACP_I2S_TX_RINGBUFSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2028)
57#define ACP_I2S_TX_LINKPOSITIONCNTR(adata) ACP_I2S_REG_ADDR(adata, 0x202C)
58#define ACP_I2S_TX_FIFOADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2030)
59#define ACP_I2S_TX_FIFOSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2034)
60#define ACP_I2S_TX_DMA_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2038)
61#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH(adata) ACP_I2S_REG_ADDR(adata, 0x203C)
62#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW(adata) ACP_I2S_REG_ADDR(adata, 0x2040)
63#define ACP_I2S_TX_INTR_WATERMARK_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2044)
64#define ACP_BT_RX_RINGBUFADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2048)
65#define ACP_BT_RX_RINGBUFSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x204C)
66#define ACP_BT_RX_LINKPOSITIONCNTR(adata) ACP_I2S_REG_ADDR(adata, 0x2050)
67#define ACP_BT_RX_FIFOADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2054)
68#define ACP_BT_RX_FIFOSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2058)
69#define ACP_BT_RX_DMA_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x205C)
70#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH(adata) ACP_I2S_REG_ADDR(adata, 0x2060)
71#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW(adata) ACP_I2S_REG_ADDR(adata, 0x2064)
72#define ACP_BT_RX_INTR_WATERMARK_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2068)
73#define ACP_BT_TX_RINGBUFADDR(adata) ACP_I2S_REG_ADDR(adata, 0x206C)
74#define ACP_BT_TX_RINGBUFSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2070)
75#define ACP_BT_TX_LINKPOSITIONCNTR(adata) ACP_I2S_REG_ADDR(adata, 0x2074)
76#define ACP_BT_TX_FIFOADDR(adata) ACP_I2S_REG_ADDR(adata, 0x2078)
77#define ACP_BT_TX_FIFOSIZE(adata) ACP_I2S_REG_ADDR(adata, 0x207C)
78#define ACP_BT_TX_DMA_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x2080)
79#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH(adata) ACP_I2S_REG_ADDR(adata, 0x2084)
80#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW(adata) ACP_I2S_REG_ADDR(adata, 0x2088)
81#define ACP_BT_TX_INTR_WATERMARK_SIZE(adata) ACP_I2S_REG_ADDR(adata, 0x208C)
82
83#define ACP_HS_RX_RINGBUFADDR 0x3A90
84#define ACP_HS_RX_RINGBUFSIZE 0x3A94
85#define ACP_HS_RX_LINKPOSITIONCNTR 0x3A98
86#define ACP_HS_RX_FIFOADDR 0x3A9C
87#define ACP_HS_RX_FIFOSIZE 0x3AA0
88#define ACP_HS_RX_DMA_SIZE 0x3AA4
89#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x3AA8
90#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x3AAC
91#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x3AB0
92#define ACP_HS_TX_RINGBUFADDR 0x3AB4
93#define ACP_HS_TX_RINGBUFSIZE 0x3AB8
94#define ACP_HS_TX_LINKPOSITIONCNTR 0x3ABC
95#define ACP_HS_TX_FIFOADDR 0x3AC0
96#define ACP_HS_TX_FIFOSIZE 0x3AC4
97#define ACP_HS_TX_DMA_SIZE 0x3AC8
98#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x3ACC
99#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x3AD0
100#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x3AD4
101
102#define ACP_I2STDM_IER 0x2400
103#define ACP_I2STDM_IRER 0x2404
104#define ACP_I2STDM_RXFRMT 0x2408
105#define ACP_I2STDM_ITER 0x240C
106#define ACP_I2STDM_TXFRMT 0x2410
107
108/* Registers from ACP_BT_TDM block */
109
110#define ACP_BTTDM_IER 0x2800
111#define ACP_BTTDM_IRER 0x2804
112#define ACP_BTTDM_RXFRMT 0x2808
113#define ACP_BTTDM_ITER 0x280C
114#define ACP_BTTDM_TXFRMT 0x2810
115
116/* Registers from ACP_HS_TDM block */
117#define ACP_HSTDM_IER 0x2814
118#define ACP_HSTDM_IRER 0x2818
119#define ACP_HSTDM_RXFRMT 0x281C
120#define ACP_HSTDM_ITER 0x2820
121#define ACP_HSTDM_TXFRMT 0x2824
122
123/* Registers from ACP_WOV_PDM block */
124
125#define ACP_WOV_PDM_ENABLE 0x2C04
126#define ACP_WOV_PDM_DMA_ENABLE 0x2C08
127#define ACP_WOV_RX_RINGBUFADDR 0x2C0C
128#define ACP_WOV_RX_RINGBUFSIZE 0x2C10
129#define ACP_WOV_RX_LINKPOSITIONCNTR 0x2C14
130#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x2C18
131#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x2C1C
132#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x2C20
133#define ACP_WOV_PDM_FIFO_FLUSH 0x2C24
134#define ACP_WOV_PDM_NO_OF_CHANNELS 0x2C28
135#define ACP_WOV_PDM_DECIMATION_FACTOR 0x2C2C
136#define ACP_WOV_PDM_VAD_CTRL 0x2C30
137#define ACP_WOV_BUFFER_STATUS 0x2C58
138#define ACP_WOV_MISC_CTRL 0x2C5C
139#define ACP_WOV_CLK_CTRL 0x2C60
140#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x2C64
141#define ACP_WOV_ERROR_STATUS_REGISTER 0x2C68
142
143#define ACP_I2STDM0_MSTRCLKGEN 0x2414
144#define ACP_I2STDM1_MSTRCLKGEN 0x2418
145#define ACP_I2STDM2_MSTRCLKGEN 0x241C
146#endif