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1// SPDX-License-Identifier: GPL-2.0-only
2/***************************************************************************
3
4 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
5 All rights reserved
6 www.echoaudio.com
7
8 This file is part of Echo Digital Audio's generic driver library.
9 *************************************************************************
10
11 Translation from C++ and adaptation for use in ALSA-Driver
12 were made by Giuliano Pochini <pochini@shiny.it>
13
14****************************************************************************/
15
16
17static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
18{
19 int err;
20
21 if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA20))
22 return -ENODEV;
23
24 err = init_dsp_comm_page(chip);
25 if (err) {
26 dev_err(chip->card->dev,
27 "init_hw: could not initialize DSP comm page\n");
28 return err;
29 }
30
31 chip->device_id = device_id;
32 chip->subdevice_id = subdevice_id;
33 chip->bad_board = true;
34 chip->dsp_code_to_load = FW_DARLA20_DSP;
35 chip->spdif_status = GD_SPDIF_STATUS_UNDEF;
36 chip->clock_state = GD_CLOCK_UNDEF;
37 /* Since this card has no ASIC, mark it as loaded so everything
38 works OK */
39 chip->asic_loaded = true;
40 chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL;
41
42 err = load_firmware(chip);
43 if (err < 0)
44 return err;
45 chip->bad_board = false;
46
47 return err;
48}
49
50
51
52static int set_mixer_defaults(struct echoaudio *chip)
53{
54 return init_line_levels(chip);
55}
56
57
58
59/* The Darla20 has no external clock sources */
60static u32 detect_input_clocks(const struct echoaudio *chip)
61{
62 return ECHO_CLOCK_BIT_INTERNAL;
63}
64
65
66
67/* The Darla20 has no ASIC. Just do nothing */
68static int load_asic(struct echoaudio *chip)
69{
70 return 0;
71}
72
73
74
75static int set_sample_rate(struct echoaudio *chip, u32 rate)
76{
77 u8 clock_state, spdif_status;
78
79 if (wait_handshake(chip))
80 return -EIO;
81
82 switch (rate) {
83 case 44100:
84 clock_state = GD_CLOCK_44;
85 spdif_status = GD_SPDIF_STATUS_44;
86 break;
87 case 48000:
88 clock_state = GD_CLOCK_48;
89 spdif_status = GD_SPDIF_STATUS_48;
90 break;
91 default:
92 clock_state = GD_CLOCK_NOCHANGE;
93 spdif_status = GD_SPDIF_STATUS_NOCHANGE;
94 break;
95 }
96
97 if (chip->clock_state == clock_state)
98 clock_state = GD_CLOCK_NOCHANGE;
99 if (spdif_status == chip->spdif_status)
100 spdif_status = GD_SPDIF_STATUS_NOCHANGE;
101
102 chip->comm_page->sample_rate = cpu_to_le32(rate);
103 chip->comm_page->gd_clock_state = clock_state;
104 chip->comm_page->gd_spdif_status = spdif_status;
105 chip->comm_page->gd_resampler_state = 3; /* magic number - should always be 3 */
106
107 /* Save the new audio state if it changed */
108 if (clock_state != GD_CLOCK_NOCHANGE)
109 chip->clock_state = clock_state;
110 if (spdif_status != GD_SPDIF_STATUS_NOCHANGE)
111 chip->spdif_status = spdif_status;
112 chip->sample_rate = rate;
113
114 clear_handshake(chip);
115 return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
116}