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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2/* Copyright (C) 2018-2025, Advanced Micro Devices, Inc */ 3 4#ifndef IONIC_ABI_H 5#define IONIC_ABI_H 6 7#include <linux/types.h> 8 9#define IONIC_ABI_VERSION 1 10 11#define IONIC_EXPDB_64 1 12#define IONIC_EXPDB_128 2 13#define IONIC_EXPDB_256 4 14#define IONIC_EXPDB_512 8 15 16#define IONIC_EXPDB_SQ 1 17#define IONIC_EXPDB_RQ 2 18 19#define IONIC_CMB_ENABLE 1 20#define IONIC_CMB_REQUIRE 2 21#define IONIC_CMB_EXPDB 4 22#define IONIC_CMB_WC 8 23#define IONIC_CMB_UC 16 24 25struct ionic_ctx_req { 26 __u32 rsvd[2]; 27}; 28 29struct ionic_ctx_resp { 30 __u32 rsvd; 31 __u32 page_shift; 32 33 __aligned_u64 dbell_offset; 34 35 __u16 version; 36 __u8 qp_opcodes; 37 __u8 admin_opcodes; 38 39 __u8 sq_qtype; 40 __u8 rq_qtype; 41 __u8 cq_qtype; 42 __u8 admin_qtype; 43 44 __u8 max_stride; 45 __u8 max_spec; 46 __u8 udma_count; 47 __u8 expdb_mask; 48 __u8 expdb_qtypes; 49 50 __u8 rsvd2[3]; 51}; 52 53struct ionic_qdesc { 54 __aligned_u64 addr; 55 __u32 size; 56 __u16 mask; 57 __u8 depth_log2; 58 __u8 stride_log2; 59}; 60 61struct ionic_ah_resp { 62 __u32 ahid; 63 __u32 pad; 64}; 65 66struct ionic_cq_req { 67 struct ionic_qdesc cq[2]; 68 __u8 udma_mask; 69 __u8 rsvd[7]; 70}; 71 72struct ionic_cq_resp { 73 __u32 cqid[2]; 74 __u8 udma_mask; 75 __u8 rsvd[7]; 76}; 77 78struct ionic_qp_req { 79 struct ionic_qdesc sq; 80 struct ionic_qdesc rq; 81 __u8 sq_spec; 82 __u8 rq_spec; 83 __u8 sq_cmb; 84 __u8 rq_cmb; 85 __u8 udma_mask; 86 __u8 rsvd[3]; 87}; 88 89struct ionic_qp_resp { 90 __u32 qpid; 91 __u8 sq_cmb; 92 __u8 rq_cmb; 93 __u8 udma_idx; 94 __u8 rsvd[1]; 95 __aligned_u64 sq_cmb_offset; 96 __aligned_u64 rq_cmb_offset; 97}; 98 99struct ionic_srq_req { 100 struct ionic_qdesc rq; 101 __u8 rq_spec; 102 __u8 rq_cmb; 103 __u8 udma_mask; 104 __u8 rsvd[5]; 105}; 106 107struct ionic_srq_resp { 108 __u32 qpid; 109 __u8 rq_cmb; 110 __u8 udma_idx; 111 __u8 rsvd[2]; 112 __aligned_u64 rq_cmb_offset; 113}; 114 115#endif /* IONIC_ABI_H */