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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2021-2024 Advanced Micro Devices, Inc.
4 */
5#ifndef _AMD_APML_H_
6#define _AMD_APML_H_
7
8#include <linux/types.h>
9
10/* Mailbox data size for data_in and data_out */
11#define AMD_SBI_MB_DATA_SIZE 4
12
13struct apml_mbox_msg {
14 /*
15 * Mailbox Message ID
16 */
17 __u32 cmd;
18 /*
19 * [0]...[3] mailbox 32bit input/output data
20 */
21 __u32 mb_in_out;
22 /*
23 * Error code is returned in case of soft mailbox error
24 */
25 __u32 fw_ret_code;
26};
27
28struct apml_cpuid_msg {
29 /*
30 * CPUID input
31 * [0]...[3] cpuid func,
32 * [4][5] cpuid: thread
33 * [6] cpuid: ext function & read eax/ebx or ecx/edx
34 * [7:0] -> bits [7:4] -> ext function &
35 * bit [0] read eax/ebx or ecx/edx
36 * CPUID output
37 */
38 __u64 cpu_in_out;
39 /*
40 * Status code for CPUID read
41 */
42 __u32 fw_ret_code;
43 __u32 pad;
44};
45
46struct apml_mcamsr_msg {
47 /*
48 * MCAMSR input
49 * [0]...[3] mca msr func,
50 * [4][5] thread
51 * MCAMSR output
52 */
53 __u64 mcamsr_in_out;
54 /*
55 * Status code for MCA/MSR access
56 */
57 __u32 fw_ret_code;
58 __u32 pad;
59};
60
61struct apml_reg_xfer_msg {
62 /*
63 * RMI register address offset
64 */
65 __u16 reg_addr;
66 /*
67 * Register data for read/write
68 */
69 __u8 data_in_out;
70 /*
71 * Register read or write
72 */
73 __u8 rflag;
74};
75
76/*
77 * AMD sideband interface base IOCTL
78 */
79#define SB_BASE_IOCTL_NR 0xF9
80
81/**
82 * DOC: SBRMI_IOCTL_MBOX_CMD
83 *
84 * @Parameters
85 *
86 * @struct apml_mbox_msg
87 * Pointer to the &struct apml_mbox_msg that will contain the protocol
88 * information
89 *
90 * @Description
91 * IOCTL command for APML messages using generic _IOWR
92 * The IOCTL provides userspace access to AMD sideband mailbox protocol
93 * - Mailbox message read/write(0x0~0xFF)
94 * - returning "-EFAULT" if none of the above
95 * "-EPROTOTYPE" error is returned to provide additional error details
96 */
97#define SBRMI_IOCTL_MBOX_CMD _IOWR(SB_BASE_IOCTL_NR, 0, struct apml_mbox_msg)
98
99/**
100 * DOC: SBRMI_IOCTL_CPUID_CMD
101 *
102 * @Parameters
103 *
104 * @struct apml_cpuid_msg
105 * Pointer to the &struct apml_cpuid_msg that will contain the protocol
106 * information
107 *
108 * @Description
109 * IOCTL command for APML messages using generic _IOWR
110 * The IOCTL provides userspace access to AMD sideband cpuid protocol
111 * - CPUID protocol to get CPU details for Function/Ext Function
112 * at thread level
113 * - returning "-EFAULT" if none of the above
114 * "-EPROTOTYPE" error is returned to provide additional error details
115 */
116#define SBRMI_IOCTL_CPUID_CMD _IOWR(SB_BASE_IOCTL_NR, 1, struct apml_cpuid_msg)
117
118/**
119 * DOC: SBRMI_IOCTL_MCAMSR_CMD
120 *
121 * @Parameters
122 *
123 * @struct apml_mcamsr_msg
124 * Pointer to the &struct apml_mcamsr_msg that will contain the protocol
125 * information
126 *
127 * @Description
128 * IOCTL command for APML messages using generic _IOWR
129 * The IOCTL provides userspace access to AMD sideband MCAMSR protocol
130 * - MCAMSR protocol to get MCA bank details for Function at thread level
131 * - returning "-EFAULT" if none of the above
132 * "-EPROTOTYPE" error is returned to provide additional error details
133 */
134#define SBRMI_IOCTL_MCAMSR_CMD _IOWR(SB_BASE_IOCTL_NR, 2, struct apml_mcamsr_msg)
135
136/**
137 * DOC: SBRMI_IOCTL_REG_XFER_CMD
138 *
139 * @Parameters
140 *
141 * @struct apml_reg_xfer_msg
142 * Pointer to the &struct apml_reg_xfer_msg that will contain the protocol
143 * information
144 *
145 * @Description
146 * IOCTL command for APML messages using generic _IOWR
147 * The IOCTL provides userspace access to AMD sideband register xfer protocol
148 * - Register xfer protocol to get/set hardware register for given offset
149 */
150#define SBRMI_IOCTL_REG_XFER_CMD _IOWR(SB_BASE_IOCTL_NR, 3, struct apml_reg_xfer_msg)
151
152#endif /*_AMD_APML_H_*/