Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2/* Do not edit directly, auto-generated from: */
3/* Documentation/netlink/specs/dpll.yaml */
4/* YNL-GEN uapi header */
5/* To regenerate run: tools/net/ynl/ynl-regen.sh */
6
7#ifndef _UAPI_LINUX_DPLL_H
8#define _UAPI_LINUX_DPLL_H
9
10#define DPLL_FAMILY_NAME "dpll"
11#define DPLL_FAMILY_VERSION 1
12
13/**
14 * enum dpll_mode - working modes a dpll can support, differentiates if and how
15 * dpll selects one of its inputs to syntonize with it, valid values for
16 * DPLL_A_MODE attribute
17 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
18 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
19 */
20enum dpll_mode {
21 DPLL_MODE_MANUAL = 1,
22 DPLL_MODE_AUTOMATIC,
23
24 /* private: */
25 __DPLL_MODE_MAX,
26 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
27};
28
29/**
30 * enum dpll_lock_status - provides information of dpll device lock status,
31 * valid values for DPLL_A_LOCK_STATUS attribute
32 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
33 * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
34 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
35 * available
36 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
37 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
38 * was forced by disconnecting all the pins (latter possible only when dpll
39 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
40 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
41 * DPLL_LOCK_STATUS_UNLOCKED)
42 */
43enum dpll_lock_status {
44 DPLL_LOCK_STATUS_UNLOCKED = 1,
45 DPLL_LOCK_STATUS_LOCKED,
46 DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
47 DPLL_LOCK_STATUS_HOLDOVER,
48
49 /* private: */
50 __DPLL_LOCK_STATUS_MAX,
51 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
52};
53
54/**
55 * enum dpll_lock_status_error - if previous status change was done due to a
56 * failure, this provides information of dpll device lock status error. Valid
57 * values for DPLL_A_LOCK_STATUS_ERROR attribute
58 * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without
59 * any error
60 * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due
61 * to undefined error. Driver fills this value up in case it is not able to
62 * obtain suitable exact error type.
63 * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed
64 * because of associated media got down. This may happen for example if dpll
65 * device was previously locked on an input pin of type
66 * PIN_TYPE_SYNCE_ETH_PORT.
67 * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO
68 * (Fractional Frequency Offset) between the RX and TX symbol rate on the
69 * media got too high. This may happen for example if dpll device was
70 * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
71 */
72enum dpll_lock_status_error {
73 DPLL_LOCK_STATUS_ERROR_NONE = 1,
74 DPLL_LOCK_STATUS_ERROR_UNDEFINED,
75 DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,
76 DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,
77
78 /* private: */
79 __DPLL_LOCK_STATUS_ERROR_MAX,
80 DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
81};
82
83/*
84 * level of quality of a clock device. This mainly applies when the dpll
85 * lock-status is DPLL_LOCK_STATUS_HOLDOVER. The current list is defined
86 * according to the table 11-7 contained in ITU-T G.8264/Y.1364 document. One
87 * may extend this list freely by other ITU-T defined clock qualities, or
88 * different ones defined by another standardization body (for those, please
89 * use different prefix).
90 */
91enum dpll_clock_quality_level {
92 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRC = 1,
93 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_A,
94 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_SSU_B,
95 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEC1,
96 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_PRTC,
97 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRTC,
98 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EEEC,
99 DPLL_CLOCK_QUALITY_LEVEL_ITU_OPT1_EPRC,
100
101 /* private: */
102 __DPLL_CLOCK_QUALITY_LEVEL_MAX,
103 DPLL_CLOCK_QUALITY_LEVEL_MAX = (__DPLL_CLOCK_QUALITY_LEVEL_MAX - 1)
104};
105
106#define DPLL_TEMP_DIVIDER 1000
107
108/**
109 * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
110 * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
111 * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
112 */
113enum dpll_type {
114 DPLL_TYPE_PPS = 1,
115 DPLL_TYPE_EEC,
116
117 /* private: */
118 __DPLL_TYPE_MAX,
119 DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
120};
121
122/**
123 * enum dpll_pin_type - defines possible types of a pin, valid values for
124 * DPLL_A_PIN_TYPE attribute
125 * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
126 * @DPLL_PIN_TYPE_EXT: external input
127 * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
128 * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
129 * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
130 */
131enum dpll_pin_type {
132 DPLL_PIN_TYPE_MUX = 1,
133 DPLL_PIN_TYPE_EXT,
134 DPLL_PIN_TYPE_SYNCE_ETH_PORT,
135 DPLL_PIN_TYPE_INT_OSCILLATOR,
136 DPLL_PIN_TYPE_GNSS,
137
138 /* private: */
139 __DPLL_PIN_TYPE_MAX,
140 DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
141};
142
143/**
144 * enum dpll_pin_direction - defines possible direction of a pin, valid values
145 * for DPLL_A_PIN_DIRECTION attribute
146 * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
147 * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
148 */
149enum dpll_pin_direction {
150 DPLL_PIN_DIRECTION_INPUT = 1,
151 DPLL_PIN_DIRECTION_OUTPUT,
152
153 /* private: */
154 __DPLL_PIN_DIRECTION_MAX,
155 DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
156};
157
158#define DPLL_PIN_FREQUENCY_1_HZ 1
159#define DPLL_PIN_FREQUENCY_10_KHZ 10000
160#define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
161#define DPLL_PIN_FREQUENCY_10_MHZ 10000000
162
163/**
164 * enum dpll_pin_state - defines possible states of a pin, valid values for
165 * DPLL_A_PIN_STATE attribute
166 * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
167 * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
168 * input
169 * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
170 */
171enum dpll_pin_state {
172 DPLL_PIN_STATE_CONNECTED = 1,
173 DPLL_PIN_STATE_DISCONNECTED,
174 DPLL_PIN_STATE_SELECTABLE,
175
176 /* private: */
177 __DPLL_PIN_STATE_MAX,
178 DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
179};
180
181/**
182 * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
183 * flags on DPLL_A_PIN_CAPABILITIES attribute
184 * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
185 * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
186 * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
187 */
188enum dpll_pin_capabilities {
189 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
190 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
191 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
192};
193
194#define DPLL_PHASE_OFFSET_DIVIDER 1000
195
196/**
197 * enum dpll_feature_state - Allow control (enable/disable) and status checking
198 * over features.
199 * @DPLL_FEATURE_STATE_DISABLE: feature shall be disabled
200 * @DPLL_FEATURE_STATE_ENABLE: feature shall be enabled
201 */
202enum dpll_feature_state {
203 DPLL_FEATURE_STATE_DISABLE,
204 DPLL_FEATURE_STATE_ENABLE,
205};
206
207enum dpll_a {
208 DPLL_A_ID = 1,
209 DPLL_A_MODULE_NAME,
210 DPLL_A_PAD,
211 DPLL_A_CLOCK_ID,
212 DPLL_A_MODE,
213 DPLL_A_MODE_SUPPORTED,
214 DPLL_A_LOCK_STATUS,
215 DPLL_A_TEMP,
216 DPLL_A_TYPE,
217 DPLL_A_LOCK_STATUS_ERROR,
218 DPLL_A_CLOCK_QUALITY_LEVEL,
219 DPLL_A_PHASE_OFFSET_MONITOR,
220 DPLL_A_PHASE_OFFSET_AVG_FACTOR,
221
222 __DPLL_A_MAX,
223 DPLL_A_MAX = (__DPLL_A_MAX - 1)
224};
225
226enum dpll_a_pin {
227 DPLL_A_PIN_ID = 1,
228 DPLL_A_PIN_PARENT_ID,
229 DPLL_A_PIN_MODULE_NAME,
230 DPLL_A_PIN_PAD,
231 DPLL_A_PIN_CLOCK_ID,
232 DPLL_A_PIN_BOARD_LABEL,
233 DPLL_A_PIN_PANEL_LABEL,
234 DPLL_A_PIN_PACKAGE_LABEL,
235 DPLL_A_PIN_TYPE,
236 DPLL_A_PIN_DIRECTION,
237 DPLL_A_PIN_FREQUENCY,
238 DPLL_A_PIN_FREQUENCY_SUPPORTED,
239 DPLL_A_PIN_FREQUENCY_MIN,
240 DPLL_A_PIN_FREQUENCY_MAX,
241 DPLL_A_PIN_PRIO,
242 DPLL_A_PIN_STATE,
243 DPLL_A_PIN_CAPABILITIES,
244 DPLL_A_PIN_PARENT_DEVICE,
245 DPLL_A_PIN_PARENT_PIN,
246 DPLL_A_PIN_PHASE_ADJUST_MIN,
247 DPLL_A_PIN_PHASE_ADJUST_MAX,
248 DPLL_A_PIN_PHASE_ADJUST,
249 DPLL_A_PIN_PHASE_OFFSET,
250 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
251 DPLL_A_PIN_ESYNC_FREQUENCY,
252 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
253 DPLL_A_PIN_ESYNC_PULSE,
254 DPLL_A_PIN_REFERENCE_SYNC,
255 DPLL_A_PIN_PHASE_ADJUST_GRAN,
256
257 __DPLL_A_PIN_MAX,
258 DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
259};
260
261enum dpll_cmd {
262 DPLL_CMD_DEVICE_ID_GET = 1,
263 DPLL_CMD_DEVICE_GET,
264 DPLL_CMD_DEVICE_SET,
265 DPLL_CMD_DEVICE_CREATE_NTF,
266 DPLL_CMD_DEVICE_DELETE_NTF,
267 DPLL_CMD_DEVICE_CHANGE_NTF,
268 DPLL_CMD_PIN_ID_GET,
269 DPLL_CMD_PIN_GET,
270 DPLL_CMD_PIN_SET,
271 DPLL_CMD_PIN_CREATE_NTF,
272 DPLL_CMD_PIN_DELETE_NTF,
273 DPLL_CMD_PIN_CHANGE_NTF,
274
275 __DPLL_CMD_MAX,
276 DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
277};
278
279#define DPLL_MCGRP_MONITOR "monitor"
280
281#endif /* _UAPI_LINUX_DPLL_H */