Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
4 */
5
6#ifndef _UAPI_AMDXDNA_ACCEL_H_
7#define _UAPI_AMDXDNA_ACCEL_H_
8
9#include <linux/stddef.h>
10#include "drm.h"
11
12#if defined(__cplusplus)
13extern "C" {
14#endif
15
16#define AMDXDNA_INVALID_CMD_HANDLE (~0UL)
17#define AMDXDNA_INVALID_ADDR (~0UL)
18#define AMDXDNA_INVALID_CTX_HANDLE 0
19#define AMDXDNA_INVALID_BO_HANDLE 0
20#define AMDXDNA_INVALID_FENCE_HANDLE 0
21
22enum amdxdna_device_type {
23 AMDXDNA_DEV_TYPE_UNKNOWN = -1,
24 AMDXDNA_DEV_TYPE_KMQ,
25};
26
27enum amdxdna_drm_ioctl_id {
28 DRM_AMDXDNA_CREATE_HWCTX,
29 DRM_AMDXDNA_DESTROY_HWCTX,
30 DRM_AMDXDNA_CONFIG_HWCTX,
31 DRM_AMDXDNA_CREATE_BO,
32 DRM_AMDXDNA_GET_BO_INFO,
33 DRM_AMDXDNA_SYNC_BO,
34 DRM_AMDXDNA_EXEC_CMD,
35 DRM_AMDXDNA_GET_INFO,
36 DRM_AMDXDNA_SET_STATE,
37 DRM_AMDXDNA_GET_ARRAY = 10,
38};
39
40/**
41 * struct qos_info - QoS information for driver.
42 * @gops: Giga operations per second.
43 * @fps: Frames per second.
44 * @dma_bandwidth: DMA bandwidtha.
45 * @latency: Frame response latency.
46 * @frame_exec_time: Frame execution time.
47 * @priority: Request priority.
48 *
49 * User program can provide QoS hints to driver.
50 */
51struct amdxdna_qos_info {
52 __u32 gops;
53 __u32 fps;
54 __u32 dma_bandwidth;
55 __u32 latency;
56 __u32 frame_exec_time;
57 __u32 priority;
58};
59
60/**
61 * struct amdxdna_drm_create_hwctx - Create hardware context.
62 * @ext: MBZ.
63 * @ext_flags: MBZ.
64 * @qos_p: Address of QoS info.
65 * @umq_bo: BO handle for user mode queue(UMQ).
66 * @log_buf_bo: BO handle for log buffer.
67 * @max_opc: Maximum operations per cycle.
68 * @num_tiles: Number of AIE tiles.
69 * @mem_size: Size of AIE tile memory.
70 * @umq_doorbell: Returned offset of doorbell associated with UMQ.
71 * @handle: Returned hardware context handle.
72 * @syncobj_handle: Returned syncobj handle for command completion.
73 */
74struct amdxdna_drm_create_hwctx {
75 __u64 ext;
76 __u64 ext_flags;
77 __u64 qos_p;
78 __u32 umq_bo;
79 __u32 log_buf_bo;
80 __u32 max_opc;
81 __u32 num_tiles;
82 __u32 mem_size;
83 __u32 umq_doorbell;
84 __u32 handle;
85 __u32 syncobj_handle;
86};
87
88/**
89 * struct amdxdna_drm_destroy_hwctx - Destroy hardware context.
90 * @handle: Hardware context handle.
91 * @pad: MBZ.
92 */
93struct amdxdna_drm_destroy_hwctx {
94 __u32 handle;
95 __u32 pad;
96};
97
98/**
99 * struct amdxdna_cu_config - configuration for one CU
100 * @cu_bo: CU configuration buffer bo handle.
101 * @cu_func: Function of a CU.
102 * @pad: MBZ.
103 */
104struct amdxdna_cu_config {
105 __u32 cu_bo;
106 __u8 cu_func;
107 __u8 pad[3];
108};
109
110/**
111 * struct amdxdna_hwctx_param_config_cu - configuration for CUs in hardware context
112 * @num_cus: Number of CUs to configure.
113 * @pad: MBZ.
114 * @cu_configs: Array of CU configurations of struct amdxdna_cu_config.
115 */
116struct amdxdna_hwctx_param_config_cu {
117 __u16 num_cus;
118 __u16 pad[3];
119 struct amdxdna_cu_config cu_configs[] __counted_by(num_cus);
120};
121
122enum amdxdna_drm_config_hwctx_param {
123 DRM_AMDXDNA_HWCTX_CONFIG_CU,
124 DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF,
125 DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF,
126};
127
128/**
129 * struct amdxdna_drm_config_hwctx - Configure hardware context.
130 * @handle: hardware context handle.
131 * @param_type: Value in enum amdxdna_drm_config_hwctx_param. Specifies the
132 * structure passed in via param_val.
133 * @param_val: A structure specified by the param_type struct member.
134 * @param_val_size: Size of the parameter buffer pointed to by the param_val.
135 * If param_val is not a pointer, driver can ignore this.
136 * @pad: MBZ.
137 *
138 * Note: if the param_val is a pointer pointing to a buffer, the maximum size
139 * of the buffer is 4KiB(PAGE_SIZE).
140 */
141struct amdxdna_drm_config_hwctx {
142 __u32 handle;
143 __u32 param_type;
144 __u64 param_val;
145 __u32 param_val_size;
146 __u32 pad;
147};
148
149enum amdxdna_bo_type {
150 AMDXDNA_BO_INVALID = 0,
151 AMDXDNA_BO_SHMEM,
152 AMDXDNA_BO_DEV_HEAP,
153 AMDXDNA_BO_DEV,
154 AMDXDNA_BO_CMD,
155};
156
157/**
158 * struct amdxdna_drm_va_entry
159 * @vaddr: Virtual address.
160 * @len: Size of entry.
161 */
162struct amdxdna_drm_va_entry {
163 __u64 vaddr;
164 __u64 len;
165};
166
167/**
168 * struct amdxdna_drm_va_tbl
169 * @dmabuf_fd: The fd of dmabuf.
170 * @num_entries: Number of va entries.
171 * @va_entries: Array of va entries.
172 *
173 * The input can be either a dmabuf fd or a virtual address entry table.
174 * When dmabuf_fd is used, num_entries must be zero.
175 */
176struct amdxdna_drm_va_tbl {
177 __s32 dmabuf_fd;
178 __u32 num_entries;
179 struct amdxdna_drm_va_entry va_entries[];
180};
181
182/**
183 * struct amdxdna_drm_create_bo - Create a buffer object.
184 * @flags: Buffer flags. MBZ.
185 * @vaddr: User VA of buffer if applied. MBZ.
186 * @size: Size in bytes.
187 * @type: Buffer type.
188 * @handle: Returned DRM buffer object handle.
189 */
190struct amdxdna_drm_create_bo {
191 __u64 flags;
192 __u64 vaddr;
193 __u64 size;
194 __u32 type;
195 __u32 handle;
196};
197
198/**
199 * struct amdxdna_drm_get_bo_info - Get buffer object information.
200 * @ext: MBZ.
201 * @ext_flags: MBZ.
202 * @handle: DRM buffer object handle.
203 * @pad: MBZ.
204 * @map_offset: Returned DRM fake offset for mmap().
205 * @vaddr: Returned user VA of buffer. 0 in case user needs mmap().
206 * @xdna_addr: Returned XDNA device virtual address.
207 */
208struct amdxdna_drm_get_bo_info {
209 __u64 ext;
210 __u64 ext_flags;
211 __u32 handle;
212 __u32 pad;
213 __u64 map_offset;
214 __u64 vaddr;
215 __u64 xdna_addr;
216};
217
218/**
219 * struct amdxdna_drm_sync_bo - Sync buffer object.
220 * @handle: Buffer object handle.
221 * @direction: Direction of sync, can be from device or to device.
222 * @offset: Offset in the buffer to sync.
223 * @size: Size in bytes.
224 */
225struct amdxdna_drm_sync_bo {
226 __u32 handle;
227#define SYNC_DIRECT_TO_DEVICE 0U
228#define SYNC_DIRECT_FROM_DEVICE 1U
229 __u32 direction;
230 __u64 offset;
231 __u64 size;
232};
233
234enum amdxdna_cmd_type {
235 AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0,
236 AMDXDNA_CMD_SUBMIT_DEPENDENCY,
237 AMDXDNA_CMD_SUBMIT_SIGNAL,
238};
239
240/**
241 * struct amdxdna_drm_exec_cmd - Execute command.
242 * @ext: MBZ.
243 * @ext_flags: MBZ.
244 * @hwctx: Hardware context handle.
245 * @type: One of command type in enum amdxdna_cmd_type.
246 * @cmd_handles: Array of command handles or the command handle itself
247 * in case of just one.
248 * @args: Array of arguments for all command handles.
249 * @cmd_count: Number of command handles in the cmd_handles array.
250 * @arg_count: Number of arguments in the args array.
251 * @seq: Returned sequence number for this command.
252 */
253struct amdxdna_drm_exec_cmd {
254 __u64 ext;
255 __u64 ext_flags;
256 __u32 hwctx;
257 __u32 type;
258 __u64 cmd_handles;
259 __u64 args;
260 __u32 cmd_count;
261 __u32 arg_count;
262 __u64 seq;
263};
264
265/**
266 * struct amdxdna_drm_query_aie_status - Query the status of the AIE hardware
267 * @buffer: The user space buffer that will return the AIE status.
268 * @buffer_size: The size of the user space buffer.
269 * @cols_filled: A bitmap of AIE columns whose data has been returned in the buffer.
270 */
271struct amdxdna_drm_query_aie_status {
272 __u64 buffer; /* out */
273 __u32 buffer_size; /* in */
274 __u32 cols_filled; /* out */
275};
276
277/**
278 * struct amdxdna_drm_query_aie_version - Query the version of the AIE hardware
279 * @major: The major version number.
280 * @minor: The minor version number.
281 */
282struct amdxdna_drm_query_aie_version {
283 __u32 major; /* out */
284 __u32 minor; /* out */
285};
286
287/**
288 * struct amdxdna_drm_query_aie_tile_metadata - Query the metadata of AIE tile (core, mem, shim)
289 * @row_count: The number of rows.
290 * @row_start: The starting row number.
291 * @dma_channel_count: The number of dma channels.
292 * @lock_count: The number of locks.
293 * @event_reg_count: The number of events.
294 * @pad: Structure padding.
295 */
296struct amdxdna_drm_query_aie_tile_metadata {
297 __u16 row_count;
298 __u16 row_start;
299 __u16 dma_channel_count;
300 __u16 lock_count;
301 __u16 event_reg_count;
302 __u16 pad[3];
303};
304
305/**
306 * struct amdxdna_drm_query_aie_metadata - Query the metadata of the AIE hardware
307 * @col_size: The size of a column in bytes.
308 * @cols: The total number of columns.
309 * @rows: The total number of rows.
310 * @version: The version of the AIE hardware.
311 * @core: The metadata for all core tiles.
312 * @mem: The metadata for all mem tiles.
313 * @shim: The metadata for all shim tiles.
314 */
315struct amdxdna_drm_query_aie_metadata {
316 __u32 col_size;
317 __u16 cols;
318 __u16 rows;
319 struct amdxdna_drm_query_aie_version version;
320 struct amdxdna_drm_query_aie_tile_metadata core;
321 struct amdxdna_drm_query_aie_tile_metadata mem;
322 struct amdxdna_drm_query_aie_tile_metadata shim;
323};
324
325/**
326 * struct amdxdna_drm_query_clock - Metadata for a clock
327 * @name: The clock name.
328 * @freq_mhz: The clock frequency.
329 * @pad: Structure padding.
330 */
331struct amdxdna_drm_query_clock {
332 __u8 name[16];
333 __u32 freq_mhz;
334 __u32 pad;
335};
336
337/**
338 * struct amdxdna_drm_query_clock_metadata - Query metadata for clocks
339 * @mp_npu_clock: The metadata for MP-NPU clock.
340 * @h_clock: The metadata for H clock.
341 */
342struct amdxdna_drm_query_clock_metadata {
343 struct amdxdna_drm_query_clock mp_npu_clock;
344 struct amdxdna_drm_query_clock h_clock;
345};
346
347enum amdxdna_sensor_type {
348 AMDXDNA_SENSOR_TYPE_POWER
349};
350
351/**
352 * struct amdxdna_drm_query_sensor - The data for single sensor.
353 * @label: The name for a sensor.
354 * @input: The current value of the sensor.
355 * @max: The maximum value possible for the sensor.
356 * @average: The average value of the sensor.
357 * @highest: The highest recorded sensor value for this driver load for the sensor.
358 * @status: The sensor status.
359 * @units: The sensor units.
360 * @unitm: Translates value member variables into the correct unit via (pow(10, unitm) * value).
361 * @type: The sensor type from enum amdxdna_sensor_type.
362 * @pad: Structure padding.
363 */
364struct amdxdna_drm_query_sensor {
365 __u8 label[64];
366 __u32 input;
367 __u32 max;
368 __u32 average;
369 __u32 highest;
370 __u8 status[64];
371 __u8 units[16];
372 __s8 unitm;
373 __u8 type;
374 __u8 pad[6];
375};
376
377/**
378 * struct amdxdna_drm_query_hwctx - The data for single context.
379 * @context_id: The ID for this context.
380 * @start_col: The starting column for the partition assigned to this context.
381 * @num_col: The number of columns in the partition assigned to this context.
382 * @pad: Structure padding.
383 * @pid: The Process ID of the process that created this context.
384 * @command_submissions: The number of commands submitted to this context.
385 * @command_completions: The number of commands completed by this context.
386 * @migrations: The number of times this context has been moved to a different partition.
387 * @preemptions: The number of times this context has been preempted by another context in the
388 * same partition.
389 * @errors: The errors for this context.
390 */
391struct amdxdna_drm_query_hwctx {
392 __u32 context_id;
393 __u32 start_col;
394 __u32 num_col;
395 __u32 pad;
396 __s64 pid;
397 __u64 command_submissions;
398 __u64 command_completions;
399 __u64 migrations;
400 __u64 preemptions;
401 __u64 errors;
402};
403
404enum amdxdna_power_mode_type {
405 POWER_MODE_DEFAULT, /* Fallback to calculated DPM */
406 POWER_MODE_LOW, /* Set frequency to lowest DPM */
407 POWER_MODE_MEDIUM, /* Set frequency to medium DPM */
408 POWER_MODE_HIGH, /* Set frequency to highest DPM */
409 POWER_MODE_TURBO, /* Maximum power */
410};
411
412/**
413 * struct amdxdna_drm_get_power_mode - Get the configured power mode
414 * @power_mode: The mode type from enum amdxdna_power_mode_type
415 * @pad: Structure padding.
416 */
417struct amdxdna_drm_get_power_mode {
418 __u8 power_mode;
419 __u8 pad[7];
420};
421
422/**
423 * struct amdxdna_drm_query_firmware_version - Query the firmware version
424 * @major: The major version number
425 * @minor: The minor version number
426 * @patch: The patch level version number
427 * @build: The build ID
428 */
429struct amdxdna_drm_query_firmware_version {
430 __u32 major; /* out */
431 __u32 minor; /* out */
432 __u32 patch; /* out */
433 __u32 build; /* out */
434};
435
436enum amdxdna_drm_get_param {
437 DRM_AMDXDNA_QUERY_AIE_STATUS,
438 DRM_AMDXDNA_QUERY_AIE_METADATA,
439 DRM_AMDXDNA_QUERY_AIE_VERSION,
440 DRM_AMDXDNA_QUERY_CLOCK_METADATA,
441 DRM_AMDXDNA_QUERY_SENSORS,
442 DRM_AMDXDNA_QUERY_HW_CONTEXTS,
443 DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8,
444 DRM_AMDXDNA_GET_POWER_MODE,
445 DRM_AMDXDNA_QUERY_TELEMETRY,
446 DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE,
447 DRM_AMDXDNA_QUERY_RESOURCE_INFO,
448 DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE,
449};
450
451/**
452 * struct amdxdna_drm_get_resource_info - Get resource information
453 */
454struct amdxdna_drm_get_resource_info {
455 /** @npu_clk_max: max H-Clocks */
456 __u64 npu_clk_max;
457 /** @npu_tops_max: max TOPs */
458 __u64 npu_tops_max;
459 /** @npu_task_max: max number of tasks */
460 __u64 npu_task_max;
461 /** @npu_tops_curr: current TOPs */
462 __u64 npu_tops_curr;
463 /** @npu_task_curr: current number of tasks */
464 __u64 npu_task_curr;
465};
466
467/**
468 * struct amdxdna_drm_attribute_state - State of an attribute
469 */
470struct amdxdna_drm_attribute_state {
471 /** @state: enabled or disabled */
472 __u8 state;
473 /** @pad: MBZ */
474 __u8 pad[7];
475};
476
477/**
478 * struct amdxdna_drm_query_telemetry_header - Telemetry data header
479 */
480struct amdxdna_drm_query_telemetry_header {
481 /** @major: Firmware telemetry interface major version number */
482 __u32 major;
483 /** @minor: Firmware telemetry interface minor version number */
484 __u32 minor;
485 /** @type: Telemetry query type */
486 __u32 type;
487 /** @map_num_elements: Total number of elements in the map table */
488 __u32 map_num_elements;
489 /** @map: Element map */
490 __u32 map[];
491};
492
493/**
494 * struct amdxdna_drm_get_info - Get some information from the AIE hardware.
495 * @param: Value in enum amdxdna_drm_get_param. Specifies the structure passed in the buffer.
496 * @buffer_size: Size of the input buffer. Size needed/written by the kernel.
497 * @buffer: A structure specified by the param struct member.
498 */
499struct amdxdna_drm_get_info {
500 __u32 param; /* in */
501 __u32 buffer_size; /* in/out */
502 __u64 buffer; /* in/out */
503};
504
505#define AMDXDNA_HWCTX_STATE_IDLE 0
506#define AMDXDNA_HWCTX_STATE_ACTIVE 1
507
508/**
509 * struct amdxdna_drm_hwctx_entry - The hardware context array entry
510 */
511struct amdxdna_drm_hwctx_entry {
512 /** @context_id: Context ID. */
513 __u32 context_id;
514 /** @start_col: Start AIE array column assigned to context. */
515 __u32 start_col;
516 /** @num_col: Number of AIE array columns assigned to context. */
517 __u32 num_col;
518 /** @hwctx_id: The real hardware context id. */
519 __u32 hwctx_id;
520 /** @pid: ID of process which created this context. */
521 __s64 pid;
522 /** @command_submissions: Number of commands submitted. */
523 __u64 command_submissions;
524 /** @command_completions: Number of commands completed. */
525 __u64 command_completions;
526 /** @migrations: Number of times been migrated. */
527 __u64 migrations;
528 /** @preemptions: Number of times been preempted. */
529 __u64 preemptions;
530 /** @errors: Number of errors happened. */
531 __u64 errors;
532 /** @priority: Context priority. */
533 __u64 priority;
534 /** @heap_usage: Usage of device heap buffer. */
535 __u64 heap_usage;
536 /** @suspensions: Number of times been suspended. */
537 __u64 suspensions;
538 /**
539 * @state: Context state.
540 * %AMDXDNA_HWCTX_STATE_IDLE
541 * %AMDXDNA_HWCTX_STATE_ACTIVE
542 */
543 __u32 state;
544 /** @pasid: PASID been bound. */
545 __u32 pasid;
546 /** @gops: Giga operations per second. */
547 __u32 gops;
548 /** @fps: Frames per second. */
549 __u32 fps;
550 /** @dma_bandwidth: DMA bandwidth. */
551 __u32 dma_bandwidth;
552 /** @latency: Frame response latency. */
553 __u32 latency;
554 /** @frame_exec_time: Frame execution time. */
555 __u32 frame_exec_time;
556 /** @txn_op_idx: Index of last control code executed. */
557 __u32 txn_op_idx;
558 /** @ctx_pc: Program counter. */
559 __u32 ctx_pc;
560 /** @fatal_error_type: Fatal error type if context crashes. */
561 __u32 fatal_error_type;
562 /** @fatal_error_exception_type: Firmware exception type. */
563 __u32 fatal_error_exception_type;
564 /** @fatal_error_exception_pc: Firmware exception program counter. */
565 __u32 fatal_error_exception_pc;
566 /** @fatal_error_app_module: Exception module name. */
567 __u32 fatal_error_app_module;
568 /** @pad: Structure pad. */
569 __u32 pad;
570};
571
572/**
573 * struct amdxdna_async_error - XDNA async error structure
574 */
575struct amdxdna_async_error {
576 /** @err_code: Error code. */
577 __u64 err_code;
578 /** @ts_us: Timestamp. */
579 __u64 ts_us;
580 /** @ex_err_code: Extra error code */
581 __u64 ex_err_code;
582};
583
584#define DRM_AMDXDNA_HW_CONTEXT_ALL 0
585#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR 2
586
587/**
588 * struct amdxdna_drm_get_array - Get information array.
589 */
590struct amdxdna_drm_get_array {
591 /**
592 * @param:
593 *
594 * Supported params:
595 *
596 * %DRM_AMDXDNA_HW_CONTEXT_ALL:
597 * Returns all created hardware contexts.
598 */
599 __u32 param;
600 /**
601 * @element_size:
602 *
603 * Specifies maximum element size and returns the actual element size.
604 */
605 __u32 element_size;
606 /**
607 * @num_element:
608 *
609 * Specifies maximum number of elements and returns the actual number
610 * of elements.
611 */
612 __u32 num_element; /* in/out */
613 /** @pad: MBZ */
614 __u32 pad;
615 /**
616 * @buffer:
617 *
618 * Specifies the match conditions and returns the matched information
619 * array.
620 */
621 __u64 buffer;
622};
623
624enum amdxdna_drm_set_param {
625 DRM_AMDXDNA_SET_POWER_MODE,
626 DRM_AMDXDNA_WRITE_AIE_MEM,
627 DRM_AMDXDNA_WRITE_AIE_REG,
628 DRM_AMDXDNA_SET_FORCE_PREEMPT,
629 DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT,
630};
631
632/**
633 * struct amdxdna_drm_set_state - Set the state of the AIE hardware.
634 * @param: Value in enum amdxdna_drm_set_param.
635 * @buffer_size: Size of the input param.
636 * @buffer: Pointer to the input param.
637 */
638struct amdxdna_drm_set_state {
639 __u32 param; /* in */
640 __u32 buffer_size; /* in */
641 __u64 buffer; /* in */
642};
643
644/**
645 * struct amdxdna_drm_set_power_mode - Set the power mode of the AIE hardware
646 * @power_mode: The sensor type from enum amdxdna_power_mode_type
647 * @pad: MBZ.
648 */
649struct amdxdna_drm_set_power_mode {
650 __u8 power_mode;
651 __u8 pad[7];
652};
653
654#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
655 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
656 struct amdxdna_drm_create_hwctx)
657
658#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
659 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
660 struct amdxdna_drm_destroy_hwctx)
661
662#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \
663 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
664 struct amdxdna_drm_config_hwctx)
665
666#define DRM_IOCTL_AMDXDNA_CREATE_BO \
667 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \
668 struct amdxdna_drm_create_bo)
669
670#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
671 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
672 struct amdxdna_drm_get_bo_info)
673
674#define DRM_IOCTL_AMDXDNA_SYNC_BO \
675 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
676 struct amdxdna_drm_sync_bo)
677
678#define DRM_IOCTL_AMDXDNA_EXEC_CMD \
679 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
680 struct amdxdna_drm_exec_cmd)
681
682#define DRM_IOCTL_AMDXDNA_GET_INFO \
683 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \
684 struct amdxdna_drm_get_info)
685
686#define DRM_IOCTL_AMDXDNA_SET_STATE \
687 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \
688 struct amdxdna_drm_set_state)
689
690#define DRM_IOCTL_AMDXDNA_GET_ARRAY \
691 DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \
692 struct amdxdna_drm_get_array)
693
694#if defined(__cplusplus)
695} /* extern c end */
696#endif
697
698#endif /* _UAPI_AMDXDNA_ACCEL_H_ */