Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31*/
32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
35#include "mlx5_ifc_fpga.h"
36
37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
64};
65
66enum {
67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
68 MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS = 0x1,
69 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
70 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
71 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4,
72 MLX5_SET_HCA_CAP_OP_MOD_IPSEC = 0x15,
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2 = 0x20,
74 MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION = 0x25,
75};
76
77enum {
78 MLX5_SHARED_RESOURCE_UID = 0xffff,
79};
80
81enum {
82 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
84 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
85 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
86 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
87 MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT = 0x23,
88 MLX5_OBJ_TYPE_STC = 0x0040,
89 MLX5_OBJ_TYPE_RTC = 0x0041,
90 MLX5_OBJ_TYPE_STE = 0x0042,
91 MLX5_OBJ_TYPE_MODIFY_HDR_PATTERN = 0x0043,
92 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
93 MLX5_OBJ_TYPE_MKEY = 0xff01,
94 MLX5_OBJ_TYPE_QP = 0xff02,
95 MLX5_OBJ_TYPE_PSV = 0xff03,
96 MLX5_OBJ_TYPE_RMP = 0xff04,
97 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
98 MLX5_OBJ_TYPE_RQ = 0xff06,
99 MLX5_OBJ_TYPE_SQ = 0xff07,
100 MLX5_OBJ_TYPE_TIR = 0xff08,
101 MLX5_OBJ_TYPE_TIS = 0xff09,
102 MLX5_OBJ_TYPE_DCT = 0xff0a,
103 MLX5_OBJ_TYPE_XRQ = 0xff0b,
104 MLX5_OBJ_TYPE_RQT = 0xff0e,
105 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
106 MLX5_OBJ_TYPE_CQ = 0xff10,
107 MLX5_OBJ_TYPE_FT_ALIAS = 0xff15,
108};
109
110enum {
111 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
112 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
113 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
114 MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
115 (1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
116 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
117};
118
119enum {
120 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
121 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
122 MLX5_CMD_OP_INIT_HCA = 0x102,
123 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
124 MLX5_CMD_OP_ENABLE_HCA = 0x104,
125 MLX5_CMD_OP_DISABLE_HCA = 0x105,
126 MLX5_CMD_OP_QUERY_PAGES = 0x107,
127 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
128 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
129 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
130 MLX5_CMD_OP_SET_ISSI = 0x10b,
131 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
132 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
133 MLX5_CMD_OP_ALLOC_SF = 0x113,
134 MLX5_CMD_OP_DEALLOC_SF = 0x114,
135 MLX5_CMD_OP_SUSPEND_VHCA = 0x115,
136 MLX5_CMD_OP_RESUME_VHCA = 0x116,
137 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117,
138 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118,
139 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119,
140 MLX5_CMD_OP_CREATE_MKEY = 0x200,
141 MLX5_CMD_OP_QUERY_MKEY = 0x201,
142 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
143 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
144 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
145 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
146 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
147 MLX5_CMD_OP_MODIFY_MEMIC = 0x207,
148 MLX5_CMD_OP_CREATE_EQ = 0x301,
149 MLX5_CMD_OP_DESTROY_EQ = 0x302,
150 MLX5_CMD_OP_QUERY_EQ = 0x303,
151 MLX5_CMD_OP_GEN_EQE = 0x304,
152 MLX5_CMD_OP_CREATE_CQ = 0x400,
153 MLX5_CMD_OP_DESTROY_CQ = 0x401,
154 MLX5_CMD_OP_QUERY_CQ = 0x402,
155 MLX5_CMD_OP_MODIFY_CQ = 0x403,
156 MLX5_CMD_OP_CREATE_QP = 0x500,
157 MLX5_CMD_OP_DESTROY_QP = 0x501,
158 MLX5_CMD_OP_RST2INIT_QP = 0x502,
159 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
160 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
161 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
162 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
163 MLX5_CMD_OP_2ERR_QP = 0x507,
164 MLX5_CMD_OP_2RST_QP = 0x50a,
165 MLX5_CMD_OP_QUERY_QP = 0x50b,
166 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
167 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
168 MLX5_CMD_OP_CREATE_PSV = 0x600,
169 MLX5_CMD_OP_DESTROY_PSV = 0x601,
170 MLX5_CMD_OP_CREATE_SRQ = 0x700,
171 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
172 MLX5_CMD_OP_QUERY_SRQ = 0x702,
173 MLX5_CMD_OP_ARM_RQ = 0x703,
174 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
175 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
176 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
177 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
178 MLX5_CMD_OP_CREATE_DCT = 0x710,
179 MLX5_CMD_OP_DESTROY_DCT = 0x711,
180 MLX5_CMD_OP_DRAIN_DCT = 0x712,
181 MLX5_CMD_OP_QUERY_DCT = 0x713,
182 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
183 MLX5_CMD_OP_CREATE_XRQ = 0x717,
184 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
185 MLX5_CMD_OP_QUERY_XRQ = 0x719,
186 MLX5_CMD_OP_ARM_XRQ = 0x71a,
187 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
188 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
189 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
190 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
191 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
192 MLX5_CMD_OPCODE_QUERY_DELEGATED_VHCA = 0x732,
193 MLX5_CMD_OPCODE_CREATE_ESW_VPORT = 0x733,
194 MLX5_CMD_OPCODE_DESTROY_ESW_VPORT = 0x734,
195 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
196 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
197 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
198 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
199 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
200 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
201 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
202 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
203 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
204 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
205 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
206 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
207 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
208 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
209 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
210 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
211 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
212 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
213 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
214 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
215 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
216 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
217 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
218 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
219 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
220 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
221 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
222 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
223 MLX5_CMD_OP_ALLOC_PD = 0x800,
224 MLX5_CMD_OP_DEALLOC_PD = 0x801,
225 MLX5_CMD_OP_ALLOC_UAR = 0x802,
226 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
227 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
228 MLX5_CMD_OP_ACCESS_REG = 0x805,
229 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
230 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
231 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
232 MLX5_CMD_OP_MAD_IFC = 0x50d,
233 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
234 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
235 MLX5_CMD_OP_NOP = 0x80d,
236 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
237 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
238 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
239 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
240 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
241 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
242 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
243 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
244 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
245 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
246 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
247 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
248 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
249 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
250 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
251 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
252 MLX5_CMD_OP_CREATE_LAG = 0x840,
253 MLX5_CMD_OP_MODIFY_LAG = 0x841,
254 MLX5_CMD_OP_QUERY_LAG = 0x842,
255 MLX5_CMD_OP_DESTROY_LAG = 0x843,
256 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
257 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
258 MLX5_CMD_OP_CREATE_TIR = 0x900,
259 MLX5_CMD_OP_MODIFY_TIR = 0x901,
260 MLX5_CMD_OP_DESTROY_TIR = 0x902,
261 MLX5_CMD_OP_QUERY_TIR = 0x903,
262 MLX5_CMD_OP_CREATE_SQ = 0x904,
263 MLX5_CMD_OP_MODIFY_SQ = 0x905,
264 MLX5_CMD_OP_DESTROY_SQ = 0x906,
265 MLX5_CMD_OP_QUERY_SQ = 0x907,
266 MLX5_CMD_OP_CREATE_RQ = 0x908,
267 MLX5_CMD_OP_MODIFY_RQ = 0x909,
268 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
269 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
270 MLX5_CMD_OP_QUERY_RQ = 0x90b,
271 MLX5_CMD_OP_CREATE_RMP = 0x90c,
272 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
273 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
274 MLX5_CMD_OP_QUERY_RMP = 0x90f,
275 MLX5_CMD_OP_CREATE_TIS = 0x912,
276 MLX5_CMD_OP_MODIFY_TIS = 0x913,
277 MLX5_CMD_OP_DESTROY_TIS = 0x914,
278 MLX5_CMD_OP_QUERY_TIS = 0x915,
279 MLX5_CMD_OP_CREATE_RQT = 0x916,
280 MLX5_CMD_OP_MODIFY_RQT = 0x917,
281 MLX5_CMD_OP_DESTROY_RQT = 0x918,
282 MLX5_CMD_OP_QUERY_RQT = 0x919,
283 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
284 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
285 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
286 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
287 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
288 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
289 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
290 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
291 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
292 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
293 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
294 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
295 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
296 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
297 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
298 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
299 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
300 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
301 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
302 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
303 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
304 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
305 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
306 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
307 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
308 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
309 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
310 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
311 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
312 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
313 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
314 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
316 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
317 MLX5_CMD_OP_PSP_GEN_SPI = 0xb10,
318 MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11,
319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d,
320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e,
321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12,
322 MLX5_CMD_OP_ALLOW_OTHER_VHCA_ACCESS = 0xb16,
323 MLX5_CMD_OP_GENERATE_WQE = 0xb17,
324 MLX5_CMD_OPCODE_QUERY_VUID = 0xb22,
325 MLX5_CMD_OP_MAX
326};
327
328/* Valid range for general commands that don't work over an object */
329enum {
330 MLX5_CMD_OP_GENERAL_START = 0xb00,
331 MLX5_CMD_OP_GENERAL_END = 0xd00,
332};
333
334enum {
335 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
336 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
337};
338
339enum {
340 MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
341};
342
343struct mlx5_ifc_flow_table_fields_supported_bits {
344 u8 outer_dmac[0x1];
345 u8 outer_smac[0x1];
346 u8 outer_ether_type[0x1];
347 u8 outer_ip_version[0x1];
348 u8 outer_first_prio[0x1];
349 u8 outer_first_cfi[0x1];
350 u8 outer_first_vid[0x1];
351 u8 outer_ipv4_ttl[0x1];
352 u8 outer_second_prio[0x1];
353 u8 outer_second_cfi[0x1];
354 u8 outer_second_vid[0x1];
355 u8 reserved_at_b[0x1];
356 u8 outer_sip[0x1];
357 u8 outer_dip[0x1];
358 u8 outer_frag[0x1];
359 u8 outer_ip_protocol[0x1];
360 u8 outer_ip_ecn[0x1];
361 u8 outer_ip_dscp[0x1];
362 u8 outer_udp_sport[0x1];
363 u8 outer_udp_dport[0x1];
364 u8 outer_tcp_sport[0x1];
365 u8 outer_tcp_dport[0x1];
366 u8 outer_tcp_flags[0x1];
367 u8 outer_gre_protocol[0x1];
368 u8 outer_gre_key[0x1];
369 u8 outer_vxlan_vni[0x1];
370 u8 outer_geneve_vni[0x1];
371 u8 outer_geneve_oam[0x1];
372 u8 outer_geneve_protocol_type[0x1];
373 u8 outer_geneve_opt_len[0x1];
374 u8 source_vhca_port[0x1];
375 u8 source_eswitch_port[0x1];
376
377 u8 inner_dmac[0x1];
378 u8 inner_smac[0x1];
379 u8 inner_ether_type[0x1];
380 u8 inner_ip_version[0x1];
381 u8 inner_first_prio[0x1];
382 u8 inner_first_cfi[0x1];
383 u8 inner_first_vid[0x1];
384 u8 reserved_at_27[0x1];
385 u8 inner_second_prio[0x1];
386 u8 inner_second_cfi[0x1];
387 u8 inner_second_vid[0x1];
388 u8 reserved_at_2b[0x1];
389 u8 inner_sip[0x1];
390 u8 inner_dip[0x1];
391 u8 inner_frag[0x1];
392 u8 inner_ip_protocol[0x1];
393 u8 inner_ip_ecn[0x1];
394 u8 inner_ip_dscp[0x1];
395 u8 inner_udp_sport[0x1];
396 u8 inner_udp_dport[0x1];
397 u8 inner_tcp_sport[0x1];
398 u8 inner_tcp_dport[0x1];
399 u8 inner_tcp_flags[0x1];
400 u8 reserved_at_37[0x9];
401
402 u8 geneve_tlv_option_0_data[0x1];
403 u8 geneve_tlv_option_0_exist[0x1];
404 u8 reserved_at_42[0x3];
405 u8 outer_first_mpls_over_udp[0x4];
406 u8 outer_first_mpls_over_gre[0x4];
407 u8 inner_first_mpls[0x4];
408 u8 outer_first_mpls[0x4];
409 u8 reserved_at_55[0x2];
410 u8 outer_esp_spi[0x1];
411 u8 reserved_at_58[0x2];
412 u8 bth_dst_qp[0x1];
413 u8 reserved_at_5b[0x5];
414
415 u8 reserved_at_60[0x18];
416 u8 metadata_reg_c_7[0x1];
417 u8 metadata_reg_c_6[0x1];
418 u8 metadata_reg_c_5[0x1];
419 u8 metadata_reg_c_4[0x1];
420 u8 metadata_reg_c_3[0x1];
421 u8 metadata_reg_c_2[0x1];
422 u8 metadata_reg_c_1[0x1];
423 u8 metadata_reg_c_0[0x1];
424};
425
426/* Table 2170 - Flow Table Fields Supported 2 Format */
427struct mlx5_ifc_flow_table_fields_supported_2_bits {
428 u8 inner_l4_type_ext[0x1];
429 u8 outer_l4_type_ext[0x1];
430 u8 inner_l4_type[0x1];
431 u8 outer_l4_type[0x1];
432 u8 reserved_at_4[0xa];
433 u8 bth_opcode[0x1];
434 u8 reserved_at_f[0x1];
435 u8 tunnel_header_0_1[0x1];
436 u8 reserved_at_11[0xf];
437
438 u8 reserved_at_20[0xf];
439 u8 ipsec_next_header[0x1];
440 u8 reserved_at_30[0x10];
441
442 u8 reserved_at_40[0x40];
443};
444
445struct mlx5_ifc_flow_table_prop_layout_bits {
446 u8 ft_support[0x1];
447 u8 reserved_at_1[0x1];
448 u8 flow_counter[0x1];
449 u8 flow_modify_en[0x1];
450 u8 modify_root[0x1];
451 u8 identified_miss_table_mode[0x1];
452 u8 flow_table_modify[0x1];
453 u8 reformat[0x1];
454 u8 decap[0x1];
455 u8 reset_root_to_default[0x1];
456 u8 pop_vlan[0x1];
457 u8 push_vlan[0x1];
458 u8 reserved_at_c[0x1];
459 u8 pop_vlan_2[0x1];
460 u8 push_vlan_2[0x1];
461 u8 reformat_and_vlan_action[0x1];
462 u8 reserved_at_10[0x1];
463 u8 sw_owner[0x1];
464 u8 reformat_l3_tunnel_to_l2[0x1];
465 u8 reformat_l2_to_l3_tunnel[0x1];
466 u8 reformat_and_modify_action[0x1];
467 u8 ignore_flow_level[0x1];
468 u8 reserved_at_16[0x1];
469 u8 table_miss_action_domain[0x1];
470 u8 termination_table[0x1];
471 u8 reformat_and_fwd_to_table[0x1];
472 u8 reserved_at_1a[0x2];
473 u8 ipsec_encrypt[0x1];
474 u8 ipsec_decrypt[0x1];
475 u8 sw_owner_v2[0x1];
476 u8 reserved_at_1f[0x1];
477
478 u8 termination_table_raw_traffic[0x1];
479 u8 reserved_at_21[0x1];
480 u8 log_max_ft_size[0x6];
481 u8 log_max_modify_header_context[0x8];
482 u8 max_modify_header_actions[0x8];
483 u8 max_ft_level[0x8];
484
485 u8 reformat_add_esp_trasport[0x1];
486 u8 reformat_l2_to_l3_esp_tunnel[0x1];
487 u8 reformat_add_esp_transport_over_udp[0x1];
488 u8 reformat_del_esp_trasport[0x1];
489 u8 reformat_l3_esp_tunnel_to_l2[0x1];
490 u8 reformat_del_esp_transport_over_udp[0x1];
491 u8 execute_aso[0x1];
492 u8 reserved_at_47[0x19];
493
494 u8 reformat_l2_to_l3_psp_tunnel[0x1];
495 u8 reformat_l3_psp_tunnel_to_l2[0x1];
496 u8 reformat_insert[0x1];
497 u8 reformat_remove[0x1];
498 u8 macsec_encrypt[0x1];
499 u8 macsec_decrypt[0x1];
500 u8 psp_encrypt[0x1];
501 u8 psp_decrypt[0x1];
502 u8 reformat_add_macsec[0x1];
503 u8 reformat_remove_macsec[0x1];
504 u8 reparse[0x1];
505 u8 reserved_at_6b[0x1];
506 u8 cross_vhca_object[0x1];
507 u8 reformat_l2_to_l3_audp_tunnel[0x1];
508 u8 reformat_l3_audp_tunnel_to_l2[0x1];
509 u8 ignore_flow_level_rtc_valid[0x1];
510 u8 reserved_at_70[0x8];
511 u8 log_max_ft_num[0x8];
512
513 u8 reserved_at_80[0x10];
514 u8 log_max_flow_counter[0x8];
515 u8 log_max_destination[0x8];
516
517 u8 reserved_at_a0[0x18];
518 u8 log_max_flow[0x8];
519
520 u8 reserved_at_c0[0x40];
521
522 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
523
524 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
525};
526
527struct mlx5_ifc_odp_per_transport_service_cap_bits {
528 u8 send[0x1];
529 u8 receive[0x1];
530 u8 write[0x1];
531 u8 read[0x1];
532 u8 atomic[0x1];
533 u8 srq_receive[0x1];
534 u8 reserved_at_6[0x1a];
535};
536
537struct mlx5_ifc_ipv4_layout_bits {
538 u8 reserved_at_0[0x60];
539
540 u8 ipv4[0x20];
541};
542
543struct mlx5_ifc_ipv6_layout_bits {
544 u8 ipv6[16][0x8];
545};
546
547struct mlx5_ifc_ipv6_simple_layout_bits {
548 u8 ipv6_127_96[0x20];
549 u8 ipv6_95_64[0x20];
550 u8 ipv6_63_32[0x20];
551 u8 ipv6_31_0[0x20];
552};
553
554union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
555 struct mlx5_ifc_ipv6_simple_layout_bits ipv6_simple_layout;
556 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
557 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
558 u8 reserved_at_0[0x80];
559};
560
561enum {
562 MLX5_PACKET_L4_TYPE_NONE,
563 MLX5_PACKET_L4_TYPE_TCP,
564 MLX5_PACKET_L4_TYPE_UDP,
565};
566
567enum {
568 MLX5_PACKET_L4_TYPE_EXT_NONE,
569 MLX5_PACKET_L4_TYPE_EXT_TCP,
570 MLX5_PACKET_L4_TYPE_EXT_UDP,
571 MLX5_PACKET_L4_TYPE_EXT_ICMP,
572};
573
574struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
575 u8 smac_47_16[0x20];
576
577 u8 smac_15_0[0x10];
578 u8 ethertype[0x10];
579
580 u8 dmac_47_16[0x20];
581
582 u8 dmac_15_0[0x10];
583 u8 first_prio[0x3];
584 u8 first_cfi[0x1];
585 u8 first_vid[0xc];
586
587 u8 ip_protocol[0x8];
588 u8 ip_dscp[0x6];
589 u8 ip_ecn[0x2];
590 u8 cvlan_tag[0x1];
591 u8 svlan_tag[0x1];
592 u8 frag[0x1];
593 u8 ip_version[0x4];
594 u8 tcp_flags[0x9];
595
596 u8 tcp_sport[0x10];
597 u8 tcp_dport[0x10];
598
599 u8 l4_type[0x2];
600 u8 l4_type_ext[0x4];
601 u8 reserved_at_c6[0xa];
602 u8 ipv4_ihl[0x4];
603 u8 reserved_at_d4[0x4];
604 u8 ttl_hoplimit[0x8];
605
606 u8 udp_sport[0x10];
607 u8 udp_dport[0x10];
608
609 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
610
611 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
612};
613
614struct mlx5_ifc_nvgre_key_bits {
615 u8 hi[0x18];
616 u8 lo[0x8];
617};
618
619union mlx5_ifc_gre_key_bits {
620 struct mlx5_ifc_nvgre_key_bits nvgre;
621 u8 key[0x20];
622};
623
624struct mlx5_ifc_fte_match_set_misc_bits {
625 u8 gre_c_present[0x1];
626 u8 reserved_at_1[0x1];
627 u8 gre_k_present[0x1];
628 u8 gre_s_present[0x1];
629 u8 source_vhca_port[0x4];
630 u8 source_sqn[0x18];
631
632 u8 source_eswitch_owner_vhca_id[0x10];
633 u8 source_port[0x10];
634
635 u8 outer_second_prio[0x3];
636 u8 outer_second_cfi[0x1];
637 u8 outer_second_vid[0xc];
638 u8 inner_second_prio[0x3];
639 u8 inner_second_cfi[0x1];
640 u8 inner_second_vid[0xc];
641
642 u8 outer_second_cvlan_tag[0x1];
643 u8 inner_second_cvlan_tag[0x1];
644 u8 outer_second_svlan_tag[0x1];
645 u8 inner_second_svlan_tag[0x1];
646 u8 reserved_at_64[0xc];
647 u8 gre_protocol[0x10];
648
649 union mlx5_ifc_gre_key_bits gre_key;
650
651 u8 vxlan_vni[0x18];
652 u8 bth_opcode[0x8];
653
654 u8 geneve_vni[0x18];
655 u8 reserved_at_d8[0x6];
656 u8 geneve_tlv_option_0_exist[0x1];
657 u8 geneve_oam[0x1];
658
659 u8 reserved_at_e0[0xc];
660 u8 outer_ipv6_flow_label[0x14];
661
662 u8 reserved_at_100[0xc];
663 u8 inner_ipv6_flow_label[0x14];
664
665 u8 reserved_at_120[0xa];
666 u8 geneve_opt_len[0x6];
667 u8 geneve_protocol_type[0x10];
668
669 u8 reserved_at_140[0x8];
670 u8 bth_dst_qp[0x18];
671 u8 inner_esp_spi[0x20];
672 u8 outer_esp_spi[0x20];
673 u8 reserved_at_1a0[0x60];
674};
675
676struct mlx5_ifc_fte_match_mpls_bits {
677 u8 mpls_label[0x14];
678 u8 mpls_exp[0x3];
679 u8 mpls_s_bos[0x1];
680 u8 mpls_ttl[0x8];
681};
682
683struct mlx5_ifc_fte_match_set_misc2_bits {
684 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
685
686 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
687
688 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
689
690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
691
692 u8 metadata_reg_c_7[0x20];
693
694 u8 metadata_reg_c_6[0x20];
695
696 u8 metadata_reg_c_5[0x20];
697
698 u8 metadata_reg_c_4[0x20];
699
700 u8 metadata_reg_c_3[0x20];
701
702 u8 metadata_reg_c_2[0x20];
703
704 u8 metadata_reg_c_1[0x20];
705
706 u8 metadata_reg_c_0[0x20];
707
708 u8 metadata_reg_a[0x20];
709
710 u8 psp_syndrome[0x8];
711 u8 macsec_syndrome[0x8];
712 u8 ipsec_syndrome[0x8];
713 u8 ipsec_next_header[0x8];
714
715 u8 reserved_at_1c0[0x40];
716};
717
718struct mlx5_ifc_fte_match_set_misc3_bits {
719 u8 inner_tcp_seq_num[0x20];
720
721 u8 outer_tcp_seq_num[0x20];
722
723 u8 inner_tcp_ack_num[0x20];
724
725 u8 outer_tcp_ack_num[0x20];
726
727 u8 reserved_at_80[0x8];
728 u8 outer_vxlan_gpe_vni[0x18];
729
730 u8 outer_vxlan_gpe_next_protocol[0x8];
731 u8 outer_vxlan_gpe_flags[0x8];
732 u8 reserved_at_b0[0x10];
733
734 u8 icmp_header_data[0x20];
735
736 u8 icmpv6_header_data[0x20];
737
738 u8 icmp_type[0x8];
739 u8 icmp_code[0x8];
740 u8 icmpv6_type[0x8];
741 u8 icmpv6_code[0x8];
742
743 u8 geneve_tlv_option_0_data[0x20];
744
745 u8 gtpu_teid[0x20];
746
747 u8 gtpu_msg_type[0x8];
748 u8 gtpu_msg_flags[0x8];
749 u8 reserved_at_170[0x10];
750
751 u8 gtpu_dw_2[0x20];
752
753 u8 gtpu_first_ext_dw_0[0x20];
754
755 u8 gtpu_dw_0[0x20];
756
757 u8 reserved_at_1e0[0x20];
758};
759
760struct mlx5_ifc_fte_match_set_misc4_bits {
761 u8 prog_sample_field_value_0[0x20];
762
763 u8 prog_sample_field_id_0[0x20];
764
765 u8 prog_sample_field_value_1[0x20];
766
767 u8 prog_sample_field_id_1[0x20];
768
769 u8 prog_sample_field_value_2[0x20];
770
771 u8 prog_sample_field_id_2[0x20];
772
773 u8 prog_sample_field_value_3[0x20];
774
775 u8 prog_sample_field_id_3[0x20];
776
777 u8 reserved_at_100[0x100];
778};
779
780struct mlx5_ifc_fte_match_set_misc5_bits {
781 u8 macsec_tag_0[0x20];
782
783 u8 macsec_tag_1[0x20];
784
785 u8 macsec_tag_2[0x20];
786
787 u8 macsec_tag_3[0x20];
788
789 u8 tunnel_header_0[0x20];
790
791 u8 tunnel_header_1[0x20];
792
793 u8 tunnel_header_2[0x20];
794
795 u8 tunnel_header_3[0x20];
796
797 u8 reserved_at_100[0x100];
798};
799
800struct mlx5_ifc_cmd_pas_bits {
801 u8 pa_h[0x20];
802
803 u8 pa_l[0x14];
804 u8 reserved_at_34[0xc];
805};
806
807struct mlx5_ifc_uint64_bits {
808 u8 hi[0x20];
809
810 u8 lo[0x20];
811};
812
813enum {
814 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
815 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
816 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
817 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
818 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
819 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
820 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
821 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
822 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
823 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
824};
825
826struct mlx5_ifc_ads_bits {
827 u8 fl[0x1];
828 u8 free_ar[0x1];
829 u8 reserved_at_2[0xe];
830 u8 pkey_index[0x10];
831
832 u8 plane_index[0x8];
833 u8 grh[0x1];
834 u8 mlid[0x7];
835 u8 rlid[0x10];
836
837 u8 ack_timeout[0x5];
838 u8 reserved_at_45[0x3];
839 u8 src_addr_index[0x8];
840 u8 reserved_at_50[0x4];
841 u8 stat_rate[0x4];
842 u8 hop_limit[0x8];
843
844 u8 reserved_at_60[0x4];
845 u8 tclass[0x8];
846 u8 flow_label[0x14];
847
848 u8 rgid_rip[16][0x8];
849
850 u8 reserved_at_100[0x4];
851 u8 f_dscp[0x1];
852 u8 f_ecn[0x1];
853 u8 reserved_at_106[0x1];
854 u8 f_eth_prio[0x1];
855 u8 ecn[0x2];
856 u8 dscp[0x6];
857 u8 udp_sport[0x10];
858
859 u8 dei_cfi[0x1];
860 u8 eth_prio[0x3];
861 u8 sl[0x4];
862 u8 vhca_port_num[0x8];
863 u8 rmac_47_32[0x10];
864
865 u8 rmac_31_0[0x20];
866};
867
868struct mlx5_ifc_flow_table_nic_cap_bits {
869 u8 nic_rx_multi_path_tirs[0x1];
870 u8 nic_rx_multi_path_tirs_fts[0x1];
871 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
872 u8 reserved_at_3[0x4];
873 u8 sw_owner_reformat_supported[0x1];
874 u8 reserved_at_8[0x18];
875
876 u8 encap_general_header[0x1];
877 u8 reserved_at_21[0xa];
878 u8 log_max_packet_reformat_context[0x5];
879 u8 reserved_at_30[0x6];
880 u8 max_encap_header_size[0xa];
881 u8 reserved_at_40[0x1c0];
882
883 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
884
885 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
886
887 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
888
889 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
890
891 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
892
893 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
894
895 u8 reserved_at_e00[0x600];
896
897 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive;
898
899 u8 reserved_at_1480[0x80];
900
901 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
902
903 u8 reserved_at_1580[0x280];
904
905 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
906
907 u8 reserved_at_1880[0x780];
908
909 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
910
911 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
912
913 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
914
915 u8 reserved_at_20c0[0x5f40];
916};
917
918struct mlx5_ifc_port_selection_cap_bits {
919 u8 reserved_at_0[0x10];
920 u8 port_select_flow_table[0x1];
921 u8 reserved_at_11[0x1];
922 u8 port_select_flow_table_bypass[0x1];
923 u8 reserved_at_13[0xd];
924
925 u8 reserved_at_20[0x1e0];
926
927 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
928
929 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_port_selection;
930
931 u8 reserved_at_480[0x7b80];
932};
933
934enum {
935 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
936 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
937 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
938 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
939 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
940 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
941 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
942 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
943};
944
945struct mlx5_ifc_flow_table_eswitch_cap_bits {
946 u8 fdb_to_vport_reg_c_id[0x8];
947 u8 reserved_at_8[0x5];
948 u8 fdb_uplink_hairpin[0x1];
949 u8 fdb_multi_path_any_table_limit_regc[0x1];
950 u8 reserved_at_f[0x1];
951 u8 fdb_dynamic_tunnel[0x1];
952 u8 reserved_at_11[0x1];
953 u8 fdb_multi_path_any_table[0x1];
954 u8 reserved_at_13[0x2];
955 u8 fdb_modify_header_fwd_to_table[0x1];
956 u8 fdb_ipv4_ttl_modify[0x1];
957 u8 flow_source[0x1];
958 u8 reserved_at_18[0x2];
959 u8 multi_fdb_encap[0x1];
960 u8 egress_acl_forward_to_vport[0x1];
961 u8 fdb_multi_path_to_table[0x1];
962 u8 reserved_at_1d[0x3];
963
964 u8 reserved_at_20[0x1e0];
965
966 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
967
968 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
969
970 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
971
972 u8 reserved_at_800[0xC00];
973
974 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
975
976 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
977
978 u8 reserved_at_1500[0x300];
979
980 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
981
982 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
983
984 u8 sw_steering_uplink_icm_address_rx[0x40];
985
986 u8 sw_steering_uplink_icm_address_tx[0x40];
987
988 u8 reserved_at_1900[0x6700];
989};
990
991struct mlx5_ifc_wqe_based_flow_table_cap_bits {
992 u8 reserved_at_0[0x3];
993 u8 log_max_num_ste[0x5];
994 u8 reserved_at_8[0x3];
995 u8 log_max_num_stc[0x5];
996 u8 reserved_at_10[0x3];
997 u8 log_max_num_rtc[0x5];
998 u8 reserved_at_18[0x3];
999 u8 log_max_num_header_modify_pattern[0x5];
1000
1001 u8 rtc_hash_split_table[0x1];
1002 u8 rtc_linear_lookup_table[0x1];
1003 u8 reserved_at_22[0x1];
1004 u8 stc_alloc_log_granularity[0x5];
1005 u8 reserved_at_28[0x3];
1006 u8 stc_alloc_log_max[0x5];
1007 u8 reserved_at_30[0x3];
1008 u8 ste_alloc_log_granularity[0x5];
1009 u8 reserved_at_38[0x3];
1010 u8 ste_alloc_log_max[0x5];
1011
1012 u8 reserved_at_40[0xb];
1013 u8 rtc_reparse_mode[0x5];
1014 u8 reserved_at_50[0x3];
1015 u8 rtc_index_mode[0x5];
1016 u8 reserved_at_58[0x3];
1017 u8 rtc_log_depth_max[0x5];
1018
1019 u8 reserved_at_60[0x10];
1020 u8 ste_format[0x10];
1021
1022 u8 stc_action_type[0x80];
1023
1024 u8 header_insert_type[0x10];
1025 u8 header_remove_type[0x10];
1026
1027 u8 trivial_match_definer[0x20];
1028
1029 u8 reserved_at_140[0x1b];
1030 u8 rtc_max_num_hash_definer_gen_wqe[0x5];
1031
1032 u8 reserved_at_160[0x18];
1033 u8 access_index_mode[0x8];
1034
1035 u8 reserved_at_180[0x10];
1036 u8 ste_format_gen_wqe[0x10];
1037
1038 u8 linear_match_definer_reg_c3[0x20];
1039
1040 u8 fdb_jump_to_tir_stc[0x1];
1041 u8 reserved_at_1c1[0x1f];
1042};
1043
1044struct mlx5_ifc_esw_cap_bits {
1045 u8 reserved_at_0[0x1d];
1046 u8 merged_eswitch[0x1];
1047 u8 reserved_at_1e[0x2];
1048
1049 u8 reserved_at_20[0x40];
1050
1051 u8 esw_manager_vport_number_valid[0x1];
1052 u8 reserved_at_61[0xf];
1053 u8 esw_manager_vport_number[0x10];
1054
1055 u8 reserved_at_80[0x780];
1056};
1057
1058enum {
1059 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
1060 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
1061};
1062
1063struct mlx5_ifc_e_switch_cap_bits {
1064 u8 vport_svlan_strip[0x1];
1065 u8 vport_cvlan_strip[0x1];
1066 u8 vport_svlan_insert[0x1];
1067 u8 vport_cvlan_insert_if_not_exist[0x1];
1068 u8 vport_cvlan_insert_overwrite[0x1];
1069 u8 reserved_at_5[0x1];
1070 u8 vport_cvlan_insert_always[0x1];
1071 u8 esw_shared_ingress_acl[0x1];
1072 u8 esw_uplink_ingress_acl[0x1];
1073 u8 root_ft_on_other_esw[0x1];
1074 u8 reserved_at_a[0xf];
1075 u8 esw_functions_changed[0x1];
1076 u8 reserved_at_1a[0x1];
1077 u8 ecpf_vport_exists[0x1];
1078 u8 counter_eswitch_affinity[0x1];
1079 u8 merged_eswitch[0x1];
1080 u8 nic_vport_node_guid_modify[0x1];
1081 u8 nic_vport_port_guid_modify[0x1];
1082
1083 u8 vxlan_encap_decap[0x1];
1084 u8 nvgre_encap_decap[0x1];
1085 u8 reserved_at_22[0x1];
1086 u8 log_max_fdb_encap_uplink[0x5];
1087 u8 reserved_at_21[0x3];
1088 u8 log_max_packet_reformat_context[0x5];
1089 u8 reserved_2b[0x6];
1090 u8 max_encap_header_size[0xa];
1091
1092 u8 reserved_at_40[0xb];
1093 u8 log_max_esw_sf[0x5];
1094 u8 esw_sf_base_id[0x10];
1095
1096 u8 reserved_at_60[0x7a0];
1097
1098};
1099
1100struct mlx5_ifc_qos_cap_bits {
1101 u8 packet_pacing[0x1];
1102 u8 esw_scheduling[0x1];
1103 u8 esw_bw_share[0x1];
1104 u8 esw_rate_limit[0x1];
1105 u8 reserved_at_4[0x1];
1106 u8 packet_pacing_burst_bound[0x1];
1107 u8 packet_pacing_typical_size[0x1];
1108 u8 reserved_at_7[0x1];
1109 u8 nic_sq_scheduling[0x1];
1110 u8 nic_bw_share[0x1];
1111 u8 nic_rate_limit[0x1];
1112 u8 packet_pacing_uid[0x1];
1113 u8 log_esw_max_sched_depth[0x4];
1114 u8 reserved_at_10[0x10];
1115
1116 u8 reserved_at_20[0x9];
1117 u8 esw_cross_esw_sched[0x1];
1118 u8 reserved_at_2a[0x1];
1119 u8 log_max_qos_nic_queue_group[0x5];
1120 u8 reserved_at_30[0x10];
1121
1122 u8 packet_pacing_max_rate[0x20];
1123
1124 u8 packet_pacing_min_rate[0x20];
1125
1126 u8 reserved_at_80[0xb];
1127 u8 log_esw_max_rate_limit[0x5];
1128 u8 packet_pacing_rate_table_size[0x10];
1129
1130 u8 esw_element_type[0x10];
1131 u8 esw_tsar_type[0x10];
1132
1133 u8 reserved_at_c0[0x10];
1134 u8 max_qos_para_vport[0x10];
1135
1136 u8 max_tsar_bw_share[0x20];
1137
1138 u8 nic_element_type[0x10];
1139 u8 nic_tsar_type[0x10];
1140
1141 u8 reserved_at_120[0x3];
1142 u8 log_meter_aso_granularity[0x5];
1143 u8 reserved_at_128[0x3];
1144 u8 log_meter_aso_max_alloc[0x5];
1145 u8 reserved_at_130[0x3];
1146 u8 log_max_num_meter_aso[0x5];
1147 u8 reserved_at_138[0x8];
1148
1149 u8 reserved_at_140[0x6c0];
1150};
1151
1152struct mlx5_ifc_debug_cap_bits {
1153 u8 core_dump_general[0x1];
1154 u8 core_dump_qp[0x1];
1155 u8 reserved_at_2[0x7];
1156 u8 resource_dump[0x1];
1157 u8 reserved_at_a[0x16];
1158
1159 u8 reserved_at_20[0x2];
1160 u8 stall_detect[0x1];
1161 u8 reserved_at_23[0x1d];
1162
1163 u8 reserved_at_40[0x7c0];
1164};
1165
1166struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1167 u8 csum_cap[0x1];
1168 u8 vlan_cap[0x1];
1169 u8 lro_cap[0x1];
1170 u8 lro_psh_flag[0x1];
1171 u8 lro_time_stamp[0x1];
1172 u8 reserved_at_5[0x2];
1173 u8 wqe_vlan_insert[0x1];
1174 u8 self_lb_en_modifiable[0x1];
1175 u8 reserved_at_9[0x2];
1176 u8 max_lso_cap[0x5];
1177 u8 multi_pkt_send_wqe[0x2];
1178 u8 wqe_inline_mode[0x2];
1179 u8 rss_ind_tbl_cap[0x4];
1180 u8 reg_umr_sq[0x1];
1181 u8 scatter_fcs[0x1];
1182 u8 enhanced_multi_pkt_send_wqe[0x1];
1183 u8 tunnel_lso_const_out_ip_id[0x1];
1184 u8 tunnel_lro_gre[0x1];
1185 u8 tunnel_lro_vxlan[0x1];
1186 u8 tunnel_stateless_gre[0x1];
1187 u8 tunnel_stateless_vxlan[0x1];
1188
1189 u8 swp[0x1];
1190 u8 swp_csum[0x1];
1191 u8 swp_lso[0x1];
1192 u8 cqe_checksum_full[0x1];
1193 u8 tunnel_stateless_geneve_tx[0x1];
1194 u8 tunnel_stateless_mpls_over_udp[0x1];
1195 u8 tunnel_stateless_mpls_over_gre[0x1];
1196 u8 tunnel_stateless_vxlan_gpe[0x1];
1197 u8 tunnel_stateless_ipv4_over_vxlan[0x1];
1198 u8 tunnel_stateless_ip_over_ip[0x1];
1199 u8 insert_trailer[0x1];
1200 u8 reserved_at_2b[0x1];
1201 u8 tunnel_stateless_ip_over_ip_rx[0x1];
1202 u8 tunnel_stateless_ip_over_ip_tx[0x1];
1203 u8 reserved_at_2e[0x2];
1204 u8 max_vxlan_udp_ports[0x8];
1205 u8 swp_csum_l4_partial[0x1];
1206 u8 reserved_at_39[0x5];
1207 u8 max_geneve_opt_len[0x1];
1208 u8 tunnel_stateless_geneve_rx[0x1];
1209
1210 u8 reserved_at_40[0x10];
1211 u8 lro_min_mss_size[0x10];
1212
1213 u8 reserved_at_60[0x120];
1214
1215 u8 lro_timer_supported_periods[4][0x20];
1216
1217 u8 reserved_at_200[0x600];
1218};
1219
1220enum {
1221 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1222 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1223 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1224};
1225
1226struct mlx5_ifc_roce_cap_bits {
1227 u8 roce_apm[0x1];
1228 u8 reserved_at_1[0x3];
1229 u8 sw_r_roce_src_udp_port[0x1];
1230 u8 fl_rc_qp_when_roce_disabled[0x1];
1231 u8 fl_rc_qp_when_roce_enabled[0x1];
1232 u8 roce_cc_general[0x1];
1233 u8 qp_ooo_transmit_default[0x1];
1234 u8 reserved_at_9[0x15];
1235 u8 qp_ts_format[0x2];
1236
1237 u8 reserved_at_20[0x60];
1238
1239 u8 reserved_at_80[0xc];
1240 u8 l3_type[0x4];
1241 u8 reserved_at_90[0x8];
1242 u8 roce_version[0x8];
1243
1244 u8 reserved_at_a0[0x10];
1245 u8 r_roce_dest_udp_port[0x10];
1246
1247 u8 r_roce_max_src_udp_port[0x10];
1248 u8 r_roce_min_src_udp_port[0x10];
1249
1250 u8 reserved_at_e0[0x10];
1251 u8 roce_address_table_size[0x10];
1252
1253 u8 reserved_at_100[0x700];
1254};
1255
1256struct mlx5_ifc_sync_steering_in_bits {
1257 u8 opcode[0x10];
1258 u8 uid[0x10];
1259
1260 u8 reserved_at_20[0x10];
1261 u8 op_mod[0x10];
1262
1263 u8 reserved_at_40[0xc0];
1264};
1265
1266struct mlx5_ifc_sync_steering_out_bits {
1267 u8 status[0x8];
1268 u8 reserved_at_8[0x18];
1269
1270 u8 syndrome[0x20];
1271
1272 u8 reserved_at_40[0x40];
1273};
1274
1275struct mlx5_ifc_sync_crypto_in_bits {
1276 u8 opcode[0x10];
1277 u8 uid[0x10];
1278
1279 u8 reserved_at_20[0x10];
1280 u8 op_mod[0x10];
1281
1282 u8 reserved_at_40[0x20];
1283
1284 u8 reserved_at_60[0x10];
1285 u8 crypto_type[0x10];
1286
1287 u8 reserved_at_80[0x80];
1288};
1289
1290struct mlx5_ifc_sync_crypto_out_bits {
1291 u8 status[0x8];
1292 u8 reserved_at_8[0x18];
1293
1294 u8 syndrome[0x20];
1295
1296 u8 reserved_at_40[0x40];
1297};
1298
1299struct mlx5_ifc_device_mem_cap_bits {
1300 u8 memic[0x1];
1301 u8 reserved_at_1[0x1f];
1302
1303 u8 reserved_at_20[0xb];
1304 u8 log_min_memic_alloc_size[0x5];
1305 u8 reserved_at_30[0x8];
1306 u8 log_max_memic_addr_alignment[0x8];
1307
1308 u8 memic_bar_start_addr[0x40];
1309
1310 u8 memic_bar_size[0x20];
1311
1312 u8 max_memic_size[0x20];
1313
1314 u8 steering_sw_icm_start_address[0x40];
1315
1316 u8 reserved_at_100[0x8];
1317 u8 log_header_modify_sw_icm_size[0x8];
1318 u8 reserved_at_110[0x2];
1319 u8 log_sw_icm_alloc_granularity[0x6];
1320 u8 log_steering_sw_icm_size[0x8];
1321
1322 u8 log_indirect_encap_sw_icm_size[0x8];
1323 u8 reserved_at_128[0x10];
1324 u8 log_header_modify_pattern_sw_icm_size[0x8];
1325
1326 u8 header_modify_sw_icm_start_address[0x40];
1327
1328 u8 reserved_at_180[0x40];
1329
1330 u8 header_modify_pattern_sw_icm_start_address[0x40];
1331
1332 u8 memic_operations[0x20];
1333
1334 u8 reserved_at_220[0x20];
1335
1336 u8 indirect_encap_sw_icm_start_address[0x40];
1337
1338 u8 reserved_at_280[0x580];
1339};
1340
1341struct mlx5_ifc_device_event_cap_bits {
1342 u8 user_affiliated_events[4][0x40];
1343
1344 u8 user_unaffiliated_events[4][0x40];
1345};
1346
1347struct mlx5_ifc_virtio_emulation_cap_bits {
1348 u8 desc_tunnel_offload_type[0x1];
1349 u8 eth_frame_offload_type[0x1];
1350 u8 virtio_version_1_0[0x1];
1351 u8 device_features_bits_mask[0xd];
1352 u8 event_mode[0x8];
1353 u8 virtio_queue_type[0x8];
1354
1355 u8 max_tunnel_desc[0x10];
1356 u8 reserved_at_30[0x3];
1357 u8 log_doorbell_stride[0x5];
1358 u8 reserved_at_38[0x3];
1359 u8 log_doorbell_bar_size[0x5];
1360
1361 u8 doorbell_bar_offset[0x40];
1362
1363 u8 max_emulated_devices[0x8];
1364 u8 max_num_virtio_queues[0x18];
1365
1366 u8 reserved_at_a0[0x20];
1367
1368 u8 reserved_at_c0[0x13];
1369 u8 desc_group_mkey_supported[0x1];
1370 u8 freeze_to_rdy_supported[0x1];
1371 u8 reserved_at_d5[0xb];
1372
1373 u8 reserved_at_e0[0x20];
1374
1375 u8 umem_1_buffer_param_a[0x20];
1376
1377 u8 umem_1_buffer_param_b[0x20];
1378
1379 u8 umem_2_buffer_param_a[0x20];
1380
1381 u8 umem_2_buffer_param_b[0x20];
1382
1383 u8 umem_3_buffer_param_a[0x20];
1384
1385 u8 umem_3_buffer_param_b[0x20];
1386
1387 u8 reserved_at_1c0[0x640];
1388};
1389
1390enum {
1391 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
1392 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1393 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1394 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1395 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1396 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1397 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1398 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1399 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1400};
1401
1402enum {
1403 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1404 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1405 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1406 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1407 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1408 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1409 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1410 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1411 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1412};
1413
1414struct mlx5_ifc_atomic_caps_bits {
1415 u8 reserved_at_0[0x40];
1416
1417 u8 atomic_req_8B_endianness_mode[0x2];
1418 u8 reserved_at_42[0x4];
1419 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1420
1421 u8 reserved_at_47[0x19];
1422
1423 u8 reserved_at_60[0x20];
1424
1425 u8 reserved_at_80[0x10];
1426 u8 atomic_operations[0x10];
1427
1428 u8 reserved_at_a0[0x10];
1429 u8 atomic_size_qp[0x10];
1430
1431 u8 reserved_at_c0[0x10];
1432 u8 atomic_size_dc[0x10];
1433
1434 u8 reserved_at_e0[0x720];
1435};
1436
1437struct mlx5_ifc_odp_scheme_cap_bits {
1438 u8 reserved_at_0[0x40];
1439
1440 u8 sig[0x1];
1441 u8 reserved_at_41[0x4];
1442 u8 page_prefetch[0x1];
1443 u8 reserved_at_46[0x1a];
1444
1445 u8 reserved_at_60[0x20];
1446
1447 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1448
1449 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1450
1451 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1452
1453 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1454
1455 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1456
1457 u8 reserved_at_120[0xe0];
1458};
1459
1460struct mlx5_ifc_odp_cap_bits {
1461 struct mlx5_ifc_odp_scheme_cap_bits transport_page_fault_scheme_cap;
1462
1463 struct mlx5_ifc_odp_scheme_cap_bits memory_page_fault_scheme_cap;
1464
1465 u8 reserved_at_400[0x200];
1466
1467 u8 mem_page_fault[0x1];
1468 u8 reserved_at_601[0x1f];
1469
1470 u8 reserved_at_620[0x1e0];
1471};
1472
1473struct mlx5_ifc_tls_cap_bits {
1474 u8 tls_1_2_aes_gcm_128[0x1];
1475 u8 tls_1_3_aes_gcm_128[0x1];
1476 u8 tls_1_2_aes_gcm_256[0x1];
1477 u8 tls_1_3_aes_gcm_256[0x1];
1478 u8 reserved_at_4[0x1c];
1479
1480 u8 reserved_at_20[0x7e0];
1481};
1482
1483struct mlx5_ifc_ipsec_cap_bits {
1484 u8 ipsec_full_offload[0x1];
1485 u8 ipsec_crypto_offload[0x1];
1486 u8 ipsec_esn[0x1];
1487 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1488 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1489 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1490 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1491 u8 reserved_at_7[0x4];
1492 u8 log_max_ipsec_offload[0x5];
1493 u8 reserved_at_10[0x10];
1494
1495 u8 min_log_ipsec_full_replay_window[0x8];
1496 u8 max_log_ipsec_full_replay_window[0x8];
1497 u8 reserved_at_30[0x7d0];
1498};
1499
1500struct mlx5_ifc_macsec_cap_bits {
1501 u8 macsec_epn[0x1];
1502 u8 reserved_at_1[0x2];
1503 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1504 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1505 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1506 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1507 u8 reserved_at_7[0x4];
1508 u8 log_max_macsec_offload[0x5];
1509 u8 reserved_at_10[0x10];
1510
1511 u8 min_log_macsec_full_replay_window[0x8];
1512 u8 max_log_macsec_full_replay_window[0x8];
1513 u8 reserved_at_30[0x10];
1514
1515 u8 reserved_at_40[0x7c0];
1516};
1517
1518struct mlx5_ifc_psp_cap_bits {
1519 u8 reserved_at_0[0x1];
1520 u8 psp_crypto_offload[0x1];
1521 u8 reserved_at_2[0x1];
1522 u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1];
1523 u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1];
1524 u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1];
1525 u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1];
1526 u8 reserved_at_7[0x4];
1527 u8 log_max_num_of_psp_spi[0x5];
1528 u8 reserved_at_10[0x10];
1529
1530 u8 reserved_at_20[0x7e0];
1531};
1532
1533enum {
1534 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1535 MLX5_WQ_TYPE_CYCLIC = 0x1,
1536 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1537 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1538};
1539
1540enum {
1541 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1542 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1543};
1544
1545enum {
1546 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1547 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1548 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1549 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1550 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1551};
1552
1553enum {
1554 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1555 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1556 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1557 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1558 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1559 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1560};
1561
1562enum {
1563 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1564 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1565};
1566
1567enum {
1568 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1569 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1570 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1571};
1572
1573enum {
1574 MLX5_CAP_PORT_TYPE_IB = 0x0,
1575 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1576};
1577
1578enum {
1579 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1580 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1581 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1582};
1583
1584enum {
1585 MLX5_FLEX_IPV4_OVER_VXLAN_ENABLED = 1 << 0,
1586 MLX5_FLEX_IPV6_OVER_VXLAN_ENABLED = 1 << 1,
1587 MLX5_FLEX_IPV6_OVER_IP_ENABLED = 1 << 2,
1588 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1589 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4,
1590 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5,
1591 MLX5_FLEX_P_BIT_VXLAN_GPE_ENABLED = 1 << 6,
1592 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1593 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1594 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1595 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1596 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11,
1597 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16,
1598 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1599 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18,
1600 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19,
1601};
1602
1603enum {
1604 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1605 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1606 MLX5_UCTX_CAP_RDMA_CTRL = 1UL << 3,
1607 MLX5_UCTX_CAP_RDMA_CTRL_OTHER_VHCA = 1UL << 4,
1608};
1609
1610#define MLX5_FC_BULK_SIZE_FACTOR 128
1611
1612enum mlx5_fc_bulk_alloc_bitmask {
1613 MLX5_FC_BULK_128 = (1 << 0),
1614 MLX5_FC_BULK_256 = (1 << 1),
1615 MLX5_FC_BULK_512 = (1 << 2),
1616 MLX5_FC_BULK_1024 = (1 << 3),
1617 MLX5_FC_BULK_2048 = (1 << 4),
1618 MLX5_FC_BULK_4096 = (1 << 5),
1619 MLX5_FC_BULK_8192 = (1 << 6),
1620 MLX5_FC_BULK_16384 = (1 << 7),
1621};
1622
1623#define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1624
1625#define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1626
1627enum {
1628 MLX5_STEERING_FORMAT_CONNECTX_5 = 0,
1629 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1630 MLX5_STEERING_FORMAT_CONNECTX_7 = 2,
1631 MLX5_STEERING_FORMAT_CONNECTX_8 = 3,
1632};
1633
1634struct mlx5_ifc_cmd_hca_cap_bits {
1635 u8 reserved_at_0[0x6];
1636 u8 page_request_disable[0x1];
1637 u8 abs_native_port_num[0x1];
1638 u8 reserved_at_8[0x8];
1639 u8 shared_object_to_user_object_allowed[0x1];
1640 u8 reserved_at_13[0xe];
1641 u8 vhca_resource_manager[0x1];
1642
1643 u8 hca_cap_2[0x1];
1644 u8 create_lag_when_not_master_up[0x1];
1645 u8 dtor[0x1];
1646 u8 event_on_vhca_state_teardown_request[0x1];
1647 u8 event_on_vhca_state_in_use[0x1];
1648 u8 event_on_vhca_state_active[0x1];
1649 u8 event_on_vhca_state_allocated[0x1];
1650 u8 event_on_vhca_state_invalid[0x1];
1651 u8 reserved_at_28[0x8];
1652 u8 vhca_id[0x10];
1653
1654 u8 reserved_at_40[0x40];
1655
1656 u8 log_max_srq_sz[0x8];
1657 u8 log_max_qp_sz[0x8];
1658 u8 event_cap[0x1];
1659 u8 reserved_at_91[0x2];
1660 u8 isolate_vl_tc_new[0x1];
1661 u8 reserved_at_94[0x4];
1662 u8 prio_tag_required[0x1];
1663 u8 reserved_at_99[0x2];
1664 u8 log_max_qp[0x5];
1665
1666 u8 reserved_at_a0[0x3];
1667 u8 ece_support[0x1];
1668 u8 reserved_at_a4[0x5];
1669 u8 reg_c_preserve[0x1];
1670 u8 reserved_at_aa[0x1];
1671 u8 log_max_srq[0x5];
1672 u8 reserved_at_b0[0x1];
1673 u8 uplink_follow[0x1];
1674 u8 ts_cqe_to_dest_cqn[0x1];
1675 u8 reserved_at_b3[0x6];
1676 u8 go_back_n[0x1];
1677 u8 reserved_at_ba[0x6];
1678
1679 u8 max_sgl_for_optimized_performance[0x8];
1680 u8 log_max_cq_sz[0x8];
1681 u8 relaxed_ordering_write_umr[0x1];
1682 u8 relaxed_ordering_read_umr[0x1];
1683 u8 reserved_at_d2[0x7];
1684 u8 virtio_net_device_emualtion_manager[0x1];
1685 u8 virtio_blk_device_emualtion_manager[0x1];
1686 u8 log_max_cq[0x5];
1687
1688 u8 log_max_eq_sz[0x8];
1689 u8 relaxed_ordering_write[0x1];
1690 u8 relaxed_ordering_read_pci_enabled[0x1];
1691 u8 log_max_mkey[0x6];
1692 u8 reserved_at_f0[0x6];
1693 u8 terminate_scatter_list_mkey[0x1];
1694 u8 repeated_mkey[0x1];
1695 u8 dump_fill_mkey[0x1];
1696 u8 reserved_at_f9[0x2];
1697 u8 fast_teardown[0x1];
1698 u8 log_max_eq[0x4];
1699
1700 u8 max_indirection[0x8];
1701 u8 fixed_buffer_size[0x1];
1702 u8 log_max_mrw_sz[0x7];
1703 u8 force_teardown[0x1];
1704 u8 reserved_at_111[0x1];
1705 u8 log_max_bsf_list_size[0x6];
1706 u8 umr_extended_translation_offset[0x1];
1707 u8 null_mkey[0x1];
1708 u8 log_max_klm_list_size[0x6];
1709
1710 u8 reserved_at_120[0x2];
1711 u8 qpc_extension[0x1];
1712 u8 reserved_at_123[0x7];
1713 u8 log_max_ra_req_dc[0x6];
1714 u8 reserved_at_130[0x2];
1715 u8 eth_wqe_too_small[0x1];
1716 u8 reserved_at_133[0x6];
1717 u8 vnic_env_cq_overrun[0x1];
1718 u8 log_max_ra_res_dc[0x6];
1719
1720 u8 reserved_at_140[0x5];
1721 u8 release_all_pages[0x1];
1722 u8 must_not_use[0x1];
1723 u8 reserved_at_147[0x2];
1724 u8 roce_accl[0x1];
1725 u8 log_max_ra_req_qp[0x6];
1726 u8 reserved_at_150[0xa];
1727 u8 log_max_ra_res_qp[0x6];
1728
1729 u8 end_pad[0x1];
1730 u8 cc_query_allowed[0x1];
1731 u8 cc_modify_allowed[0x1];
1732 u8 start_pad[0x1];
1733 u8 cache_line_128byte[0x1];
1734 u8 reserved_at_165[0x4];
1735 u8 rts2rts_qp_counters_set_id[0x1];
1736 u8 reserved_at_16a[0x2];
1737 u8 vnic_env_int_rq_oob[0x1];
1738 u8 sbcam_reg[0x1];
1739 u8 reserved_at_16e[0x1];
1740 u8 qcam_reg[0x1];
1741 u8 gid_table_size[0x10];
1742
1743 u8 out_of_seq_cnt[0x1];
1744 u8 vport_counters[0x1];
1745 u8 retransmission_q_counters[0x1];
1746 u8 debug[0x1];
1747 u8 modify_rq_counter_set_id[0x1];
1748 u8 rq_delay_drop[0x1];
1749 u8 max_qp_cnt[0xa];
1750 u8 pkey_table_size[0x10];
1751
1752 u8 vport_group_manager[0x1];
1753 u8 vhca_group_manager[0x1];
1754 u8 ib_virt[0x1];
1755 u8 eth_virt[0x1];
1756 u8 vnic_env_queue_counters[0x1];
1757 u8 ets[0x1];
1758 u8 nic_flow_table[0x1];
1759 u8 eswitch_manager[0x1];
1760 u8 device_memory[0x1];
1761 u8 mcam_reg[0x1];
1762 u8 pcam_reg[0x1];
1763 u8 local_ca_ack_delay[0x5];
1764 u8 port_module_event[0x1];
1765 u8 enhanced_error_q_counters[0x1];
1766 u8 ports_check[0x1];
1767 u8 reserved_at_1b3[0x1];
1768 u8 disable_link_up[0x1];
1769 u8 beacon_led[0x1];
1770 u8 port_type[0x2];
1771 u8 num_ports[0x8];
1772
1773 u8 reserved_at_1c0[0x1];
1774 u8 pps[0x1];
1775 u8 pps_modify[0x1];
1776 u8 log_max_msg[0x5];
1777 u8 reserved_at_1c8[0x4];
1778 u8 max_tc[0x4];
1779 u8 temp_warn_event[0x1];
1780 u8 dcbx[0x1];
1781 u8 general_notification_event[0x1];
1782 u8 reserved_at_1d3[0x2];
1783 u8 fpga[0x1];
1784 u8 rol_s[0x1];
1785 u8 rol_g[0x1];
1786 u8 reserved_at_1d8[0x1];
1787 u8 wol_s[0x1];
1788 u8 wol_g[0x1];
1789 u8 wol_a[0x1];
1790 u8 wol_b[0x1];
1791 u8 wol_m[0x1];
1792 u8 wol_u[0x1];
1793 u8 wol_p[0x1];
1794
1795 u8 stat_rate_support[0x10];
1796 u8 reserved_at_1f0[0x1];
1797 u8 pci_sync_for_fw_update_event[0x1];
1798 u8 reserved_at_1f2[0x6];
1799 u8 init2_lag_tx_port_affinity[0x1];
1800 u8 reserved_at_1fa[0x2];
1801 u8 wqe_based_flow_table_update_cap[0x1];
1802 u8 cqe_version[0x4];
1803
1804 u8 compact_address_vector[0x1];
1805 u8 striding_rq[0x1];
1806 u8 reserved_at_202[0x1];
1807 u8 ipoib_enhanced_offloads[0x1];
1808 u8 ipoib_basic_offloads[0x1];
1809 u8 reserved_at_205[0x1];
1810 u8 repeated_block_disabled[0x1];
1811 u8 umr_modify_entity_size_disabled[0x1];
1812 u8 umr_modify_atomic_disabled[0x1];
1813 u8 umr_indirect_mkey_disabled[0x1];
1814 u8 umr_fence[0x2];
1815 u8 dc_req_scat_data_cqe[0x1];
1816 u8 reserved_at_20d[0x2];
1817 u8 drain_sigerr[0x1];
1818 u8 cmdif_checksum[0x2];
1819 u8 sigerr_cqe[0x1];
1820 u8 reserved_at_213[0x1];
1821 u8 wq_signature[0x1];
1822 u8 sctr_data_cqe[0x1];
1823 u8 reserved_at_216[0x1];
1824 u8 sho[0x1];
1825 u8 tph[0x1];
1826 u8 rf[0x1];
1827 u8 dct[0x1];
1828 u8 qos[0x1];
1829 u8 eth_net_offloads[0x1];
1830 u8 roce[0x1];
1831 u8 atomic[0x1];
1832 u8 reserved_at_21f[0x1];
1833
1834 u8 cq_oi[0x1];
1835 u8 cq_resize[0x1];
1836 u8 cq_moderation[0x1];
1837 u8 cq_period_mode_modify[0x1];
1838 u8 reserved_at_224[0x2];
1839 u8 cq_eq_remap[0x1];
1840 u8 pg[0x1];
1841 u8 block_lb_mc[0x1];
1842 u8 reserved_at_229[0x1];
1843 u8 scqe_break_moderation[0x1];
1844 u8 cq_period_start_from_cqe[0x1];
1845 u8 cd[0x1];
1846 u8 reserved_at_22d[0x1];
1847 u8 apm[0x1];
1848 u8 vector_calc[0x1];
1849 u8 umr_ptr_rlky[0x1];
1850 u8 imaicl[0x1];
1851 u8 qp_packet_based[0x1];
1852 u8 reserved_at_233[0x3];
1853 u8 qkv[0x1];
1854 u8 pkv[0x1];
1855 u8 set_deth_sqpn[0x1];
1856 u8 reserved_at_239[0x3];
1857 u8 xrc[0x1];
1858 u8 ud[0x1];
1859 u8 uc[0x1];
1860 u8 rc[0x1];
1861
1862 u8 uar_4k[0x1];
1863 u8 reserved_at_241[0x7];
1864 u8 fl_rc_qp_when_roce_disabled[0x1];
1865 u8 regexp_params[0x1];
1866 u8 uar_sz[0x6];
1867 u8 port_selection_cap[0x1];
1868 u8 nic_cap_reg[0x1];
1869 u8 umem_uid_0[0x1];
1870 u8 reserved_at_253[0x5];
1871 u8 log_pg_sz[0x8];
1872
1873 u8 bf[0x1];
1874 u8 driver_version[0x1];
1875 u8 pad_tx_eth_packet[0x1];
1876 u8 reserved_at_263[0x3];
1877 u8 mkey_by_name[0x1];
1878 u8 reserved_at_267[0x4];
1879
1880 u8 log_bf_reg_size[0x5];
1881
1882 u8 disciplined_fr_counter[0x1];
1883 u8 reserved_at_271[0x2];
1884 u8 qp_error_syndrome[0x1];
1885 u8 reserved_at_274[0x2];
1886 u8 lag_dct[0x2];
1887 u8 lag_tx_port_affinity[0x1];
1888 u8 lag_native_fdb_selection[0x1];
1889 u8 reserved_at_27a[0x1];
1890 u8 lag_master[0x1];
1891 u8 num_lag_ports[0x4];
1892
1893 u8 reserved_at_280[0x10];
1894 u8 max_wqe_sz_sq[0x10];
1895
1896 u8 reserved_at_2a0[0x7];
1897 u8 mkey_pcie_tph[0x1];
1898 u8 reserved_at_2a8[0x1];
1899 u8 tis_tir_td_order[0x1];
1900
1901 u8 psp[0x1];
1902 u8 shampo[0x1];
1903 u8 reserved_at_2ac[0x4];
1904 u8 max_wqe_sz_rq[0x10];
1905
1906 u8 max_flow_counter_31_16[0x10];
1907 u8 max_wqe_sz_sq_dc[0x10];
1908
1909 u8 reserved_at_2e0[0x7];
1910 u8 max_qp_mcg[0x19];
1911
1912 u8 reserved_at_300[0x10];
1913 u8 flow_counter_bulk_alloc[0x8];
1914 u8 log_max_mcg[0x8];
1915
1916 u8 reserved_at_320[0x3];
1917 u8 log_max_transport_domain[0x5];
1918 u8 reserved_at_328[0x2];
1919 u8 relaxed_ordering_read[0x1];
1920 u8 log_max_pd[0x5];
1921 u8 dp_ordering_ooo_all_ud[0x1];
1922 u8 dp_ordering_ooo_all_uc[0x1];
1923 u8 dp_ordering_ooo_all_xrc[0x1];
1924 u8 dp_ordering_ooo_all_dc[0x1];
1925 u8 dp_ordering_ooo_all_rc[0x1];
1926 u8 pcie_reset_using_hotreset_method[0x1];
1927 u8 pci_sync_for_fw_update_with_driver_unload[0x1];
1928 u8 vnic_env_cnt_steering_fail[0x1];
1929 u8 vport_counter_local_loopback[0x1];
1930 u8 q_counter_aggregation[0x1];
1931 u8 q_counter_other_vport[0x1];
1932 u8 log_max_xrcd[0x5];
1933
1934 u8 nic_receive_steering_discard[0x1];
1935 u8 receive_discard_vport_down[0x1];
1936 u8 transmit_discard_vport_down[0x1];
1937 u8 eq_overrun_count[0x1];
1938 u8 reserved_at_344[0x1];
1939 u8 invalid_command_count[0x1];
1940 u8 quota_exceeded_count[0x1];
1941 u8 reserved_at_347[0x1];
1942 u8 log_max_flow_counter_bulk[0x8];
1943 u8 max_flow_counter_15_0[0x10];
1944
1945
1946 u8 reserved_at_360[0x3];
1947 u8 log_max_rq[0x5];
1948 u8 reserved_at_368[0x3];
1949 u8 log_max_sq[0x5];
1950 u8 reserved_at_370[0x3];
1951 u8 log_max_tir[0x5];
1952 u8 reserved_at_378[0x3];
1953 u8 log_max_tis[0x5];
1954
1955 u8 basic_cyclic_rcv_wqe[0x1];
1956 u8 reserved_at_381[0x2];
1957 u8 log_max_rmp[0x5];
1958 u8 reserved_at_388[0x3];
1959 u8 log_max_rqt[0x5];
1960 u8 reserved_at_390[0x3];
1961 u8 log_max_rqt_size[0x5];
1962 u8 reserved_at_398[0x1];
1963 u8 vnic_env_cnt_bar_uar_access[0x1];
1964 u8 vnic_env_cnt_odp_page_fault[0x1];
1965 u8 log_max_tis_per_sq[0x5];
1966
1967 u8 ext_stride_num_range[0x1];
1968 u8 roce_rw_supported[0x1];
1969 u8 log_max_current_uc_list_wr_supported[0x1];
1970 u8 log_max_stride_sz_rq[0x5];
1971 u8 reserved_at_3a8[0x3];
1972 u8 log_min_stride_sz_rq[0x5];
1973 u8 reserved_at_3b0[0x3];
1974 u8 log_max_stride_sz_sq[0x5];
1975 u8 reserved_at_3b8[0x3];
1976 u8 log_min_stride_sz_sq[0x5];
1977
1978 u8 hairpin[0x1];
1979 u8 reserved_at_3c1[0x2];
1980 u8 log_max_hairpin_queues[0x5];
1981 u8 reserved_at_3c8[0x3];
1982 u8 log_max_hairpin_wq_data_sz[0x5];
1983 u8 reserved_at_3d0[0x3];
1984 u8 log_max_hairpin_num_packets[0x5];
1985 u8 reserved_at_3d8[0x3];
1986 u8 log_max_wq_sz[0x5];
1987
1988 u8 nic_vport_change_event[0x1];
1989 u8 disable_local_lb_uc[0x1];
1990 u8 disable_local_lb_mc[0x1];
1991 u8 log_min_hairpin_wq_data_sz[0x5];
1992 u8 reserved_at_3e8[0x1];
1993 u8 silent_mode[0x1];
1994 u8 vhca_state[0x1];
1995 u8 log_max_vlan_list[0x5];
1996 u8 reserved_at_3f0[0x3];
1997 u8 log_max_current_mc_list[0x5];
1998 u8 reserved_at_3f8[0x3];
1999 u8 log_max_current_uc_list[0x5];
2000
2001 u8 general_obj_types[0x40];
2002
2003 u8 sq_ts_format[0x2];
2004 u8 rq_ts_format[0x2];
2005 u8 steering_format_version[0x4];
2006 u8 create_qp_start_hint[0x18];
2007
2008 u8 reserved_at_460[0x1];
2009 u8 ats[0x1];
2010 u8 cross_vhca_rqt[0x1];
2011 u8 log_max_uctx[0x5];
2012 u8 reserved_at_468[0x1];
2013 u8 crypto[0x1];
2014 u8 ipsec_offload[0x1];
2015 u8 log_max_umem[0x5];
2016 u8 max_num_eqs[0x10];
2017
2018 u8 reserved_at_480[0x1];
2019 u8 tls_tx[0x1];
2020 u8 tls_rx[0x1];
2021 u8 log_max_l2_table[0x5];
2022 u8 reserved_at_488[0x8];
2023 u8 log_uar_page_sz[0x10];
2024
2025 u8 reserved_at_4a0[0x20];
2026 u8 device_frequency_mhz[0x20];
2027 u8 device_frequency_khz[0x20];
2028
2029 u8 reserved_at_500[0x20];
2030 u8 num_of_uars_per_page[0x20];
2031
2032 u8 flex_parser_protocols[0x20];
2033
2034 u8 max_geneve_tlv_options[0x8];
2035 u8 reserved_at_568[0x3];
2036 u8 max_geneve_tlv_option_data_len[0x5];
2037 u8 reserved_at_570[0x1];
2038 u8 adv_rdma[0x1];
2039 u8 reserved_at_572[0x7];
2040 u8 adv_virtualization[0x1];
2041 u8 reserved_at_57a[0x6];
2042
2043 u8 reserved_at_580[0xb];
2044 u8 log_max_dci_stream_channels[0x5];
2045 u8 reserved_at_590[0x3];
2046 u8 log_max_dci_errored_streams[0x5];
2047 u8 reserved_at_598[0x8];
2048
2049 u8 reserved_at_5a0[0x10];
2050 u8 enhanced_cqe_compression[0x1];
2051 u8 reserved_at_5b1[0x1];
2052 u8 crossing_vhca_mkey[0x1];
2053 u8 log_max_dek[0x5];
2054 u8 reserved_at_5b8[0x4];
2055 u8 mini_cqe_resp_stride_index[0x1];
2056 u8 cqe_128_always[0x1];
2057 u8 cqe_compression_128[0x1];
2058 u8 cqe_compression[0x1];
2059
2060 u8 cqe_compression_timeout[0x10];
2061 u8 cqe_compression_max_num[0x10];
2062
2063 u8 reserved_at_5e0[0x8];
2064 u8 flex_parser_id_gtpu_dw_0[0x4];
2065 u8 reserved_at_5ec[0x4];
2066 u8 tag_matching[0x1];
2067 u8 rndv_offload_rc[0x1];
2068 u8 rndv_offload_dc[0x1];
2069 u8 log_tag_matching_list_sz[0x5];
2070 u8 reserved_at_5f8[0x3];
2071 u8 log_max_xrq[0x5];
2072
2073 u8 affiliate_nic_vport_criteria[0x8];
2074 u8 native_port_num[0x8];
2075 u8 num_vhca_ports[0x8];
2076 u8 flex_parser_id_gtpu_teid[0x4];
2077 u8 reserved_at_61c[0x2];
2078 u8 sw_owner_id[0x1];
2079 u8 reserved_at_61f[0x1];
2080
2081 u8 max_num_of_monitor_counters[0x10];
2082 u8 num_ppcnt_monitor_counters[0x10];
2083
2084 u8 max_num_sf[0x10];
2085 u8 num_q_monitor_counters[0x10];
2086
2087 u8 reserved_at_660[0x20];
2088
2089 u8 sf[0x1];
2090 u8 sf_set_partition[0x1];
2091 u8 reserved_at_682[0x1];
2092 u8 log_max_sf[0x5];
2093 u8 apu[0x1];
2094 u8 reserved_at_689[0x4];
2095 u8 migration[0x1];
2096 u8 reserved_at_68e[0x2];
2097 u8 log_min_sf_size[0x8];
2098 u8 max_num_sf_partitions[0x8];
2099
2100 u8 uctx_cap[0x20];
2101
2102 u8 reserved_at_6c0[0x4];
2103 u8 flex_parser_id_geneve_tlv_option_0[0x4];
2104 u8 flex_parser_id_icmp_dw1[0x4];
2105 u8 flex_parser_id_icmp_dw0[0x4];
2106 u8 flex_parser_id_icmpv6_dw1[0x4];
2107 u8 flex_parser_id_icmpv6_dw0[0x4];
2108 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
2109 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
2110
2111 u8 max_num_match_definer[0x10];
2112 u8 sf_base_id[0x10];
2113
2114 u8 flex_parser_id_gtpu_dw_2[0x4];
2115 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4];
2116 u8 num_total_dynamic_vf_msix[0x18];
2117 u8 reserved_at_720[0x14];
2118 u8 dynamic_msix_table_size[0xc];
2119 u8 reserved_at_740[0xc];
2120 u8 min_dynamic_vf_msix_table_size[0x4];
2121 u8 reserved_at_750[0x2];
2122 u8 data_direct[0x1];
2123 u8 reserved_at_753[0x1];
2124 u8 max_dynamic_vf_msix_table_size[0xc];
2125
2126 u8 reserved_at_760[0x3];
2127 u8 log_max_num_header_modify_argument[0x5];
2128 u8 log_header_modify_argument_granularity_offset[0x4];
2129 u8 log_header_modify_argument_granularity[0x4];
2130 u8 reserved_at_770[0x3];
2131 u8 log_header_modify_argument_max_alloc[0x5];
2132 u8 reserved_at_778[0x8];
2133
2134 u8 vhca_tunnel_commands[0x40];
2135 u8 match_definer_format_supported[0x40];
2136};
2137
2138enum {
2139 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_TO_REMOTE_FLOW_TABLE_MISS = 0x80000,
2140 MLX5_CROSS_VHCA_OBJ_TO_OBJ_SUPPORTED_LOCAL_FLOW_TABLE_ROOT_TO_REMOTE_FLOW_TABLE = (1ULL << 20),
2141};
2142
2143enum {
2144 MLX5_ALLOWED_OBJ_FOR_OTHER_VHCA_ACCESS_FLOW_TABLE = 0x200,
2145};
2146
2147struct mlx5_ifc_cmd_hca_cap_2_bits {
2148 u8 reserved_at_0[0x80];
2149
2150 u8 migratable[0x1];
2151 u8 reserved_at_81[0x7];
2152 u8 dp_ordering_force[0x1];
2153 u8 reserved_at_89[0x9];
2154 u8 query_vuid[0x1];
2155 u8 reserved_at_93[0x5];
2156 u8 umr_log_entity_size_5[0x1];
2157 u8 reserved_at_99[0x7];
2158
2159 u8 max_reformat_insert_size[0x8];
2160 u8 max_reformat_insert_offset[0x8];
2161 u8 max_reformat_remove_size[0x8];
2162 u8 max_reformat_remove_offset[0x8];
2163
2164 u8 reserved_at_c0[0x8];
2165 u8 migration_multi_load[0x1];
2166 u8 migration_tracking_state[0x1];
2167 u8 multiplane_qp_ud[0x1];
2168 u8 reserved_at_cb[0x5];
2169 u8 migration_in_chunks[0x1];
2170 u8 reserved_at_d1[0x1];
2171 u8 sf_eq_usage[0x1];
2172 u8 reserved_at_d3[0x5];
2173 u8 multiplane[0x1];
2174 u8 reserved_at_d9[0x7];
2175
2176 u8 cross_vhca_object_to_object_supported[0x20];
2177
2178 u8 allowed_object_for_other_vhca_access[0x40];
2179
2180 u8 reserved_at_140[0x60];
2181
2182 u8 flow_table_type_2_type[0x8];
2183 u8 reserved_at_1a8[0x2];
2184 u8 format_select_dw_8_6_ext[0x1];
2185 u8 log_min_mkey_entity_size[0x5];
2186 u8 reserved_at_1b0[0x10];
2187
2188 u8 general_obj_types_127_64[0x40];
2189 u8 reserved_at_200[0x20];
2190
2191 u8 reserved_at_220[0x1];
2192 u8 sw_vhca_id_valid[0x1];
2193 u8 sw_vhca_id[0xe];
2194 u8 reserved_at_230[0x10];
2195
2196 u8 reserved_at_240[0xb];
2197 u8 ts_cqe_metadata_size2wqe_counter[0x5];
2198 u8 reserved_at_250[0x10];
2199
2200 u8 reserved_at_260[0x20];
2201
2202 u8 format_select_dw_gtpu_dw_0[0x8];
2203 u8 format_select_dw_gtpu_dw_1[0x8];
2204 u8 format_select_dw_gtpu_dw_2[0x8];
2205 u8 format_select_dw_gtpu_first_ext_dw_0[0x8];
2206
2207 u8 generate_wqe_type[0x20];
2208
2209 u8 reserved_at_2c0[0xc0];
2210
2211 u8 reserved_at_380[0xb];
2212 u8 min_mkey_log_entity_size_fixed_buffer[0x5];
2213 u8 ec_vf_vport_base[0x10];
2214
2215 u8 reserved_at_3a0[0x2];
2216 u8 max_mkey_log_entity_size_fixed_buffer[0x6];
2217 u8 reserved_at_3a8[0x2];
2218 u8 max_mkey_log_entity_size_mtt[0x6];
2219 u8 max_rqt_vhca_id[0x10];
2220
2221 u8 reserved_at_3c0[0x20];
2222
2223 u8 reserved_at_3e0[0x10];
2224 u8 pcc_ifa2[0x1];
2225 u8 reserved_at_3f1[0xf];
2226
2227 u8 reserved_at_400[0x1];
2228 u8 min_mkey_log_entity_size_fixed_buffer_valid[0x1];
2229 u8 reserved_at_402[0xe];
2230 u8 return_reg_id[0x10];
2231
2232 u8 reserved_at_420[0x1c];
2233 u8 flow_table_hash_type[0x4];
2234
2235 u8 reserved_at_440[0x8];
2236 u8 max_num_eqs_24b[0x18];
2237
2238 u8 reserved_at_460[0x144];
2239 u8 load_balance_id[0x4];
2240 u8 reserved_at_5a8[0x18];
2241
2242 u8 query_adjacent_functions_id[0x1];
2243 u8 ingress_egress_esw_vport_connect[0x1];
2244 u8 function_id_type_vhca_id[0x1];
2245 u8 reserved_at_5c3[0x1];
2246 u8 lag_per_mp_group[0x1];
2247 u8 reserved_at_5c5[0xb];
2248 u8 delegate_vhca_management_profiles[0x10];
2249
2250 u8 delegated_vhca_max[0x10];
2251 u8 delegate_vhca_max[0x10];
2252
2253 u8 reserved_at_600[0x200];
2254};
2255
2256enum mlx5_ifc_flow_destination_type {
2257 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
2258 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
2259 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
2260 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
2261 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
2262 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
2263};
2264
2265enum mlx5_flow_table_miss_action {
2266 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
2267 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
2268 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
2269};
2270
2271struct mlx5_ifc_dest_format_struct_bits {
2272 u8 destination_type[0x8];
2273 u8 destination_id[0x18];
2274
2275 u8 destination_eswitch_owner_vhca_id_valid[0x1];
2276 u8 packet_reformat[0x1];
2277 u8 reserved_at_22[0x6];
2278 u8 destination_table_type[0x8];
2279 u8 destination_eswitch_owner_vhca_id[0x10];
2280};
2281
2282struct mlx5_ifc_flow_counter_list_bits {
2283 u8 flow_counter_id[0x20];
2284
2285 u8 reserved_at_20[0x20];
2286};
2287
2288struct mlx5_ifc_extended_dest_format_bits {
2289 struct mlx5_ifc_dest_format_struct_bits destination_entry;
2290
2291 u8 packet_reformat_id[0x20];
2292
2293 u8 reserved_at_60[0x20];
2294};
2295
2296union mlx5_ifc_dest_format_flow_counter_list_auto_bits {
2297 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2298 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2299};
2300
2301struct mlx5_ifc_fte_match_param_bits {
2302 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2303
2304 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2305
2306 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2307
2308 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2309
2310 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2311
2312 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2313
2314 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2315
2316 u8 reserved_at_e00[0x200];
2317};
2318
2319enum {
2320 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2321 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2322 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2323 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2324 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2325};
2326
2327struct mlx5_ifc_rx_hash_field_select_bits {
2328 u8 l3_prot_type[0x1];
2329 u8 l4_prot_type[0x1];
2330 u8 selected_fields[0x1e];
2331};
2332
2333enum {
2334 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
2335 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
2336};
2337
2338enum {
2339 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
2340 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
2341};
2342
2343struct mlx5_ifc_wq_bits {
2344 u8 wq_type[0x4];
2345 u8 wq_signature[0x1];
2346 u8 end_padding_mode[0x2];
2347 u8 cd_slave[0x1];
2348 u8 reserved_at_8[0x18];
2349
2350 u8 hds_skip_first_sge[0x1];
2351 u8 log2_hds_buf_size[0x3];
2352 u8 reserved_at_24[0x7];
2353 u8 page_offset[0x5];
2354 u8 lwm[0x10];
2355
2356 u8 reserved_at_40[0x8];
2357 u8 pd[0x18];
2358
2359 u8 reserved_at_60[0x8];
2360 u8 uar_page[0x18];
2361
2362 u8 dbr_addr[0x40];
2363
2364 u8 hw_counter[0x20];
2365
2366 u8 sw_counter[0x20];
2367
2368 u8 reserved_at_100[0xc];
2369 u8 log_wq_stride[0x4];
2370 u8 reserved_at_110[0x3];
2371 u8 log_wq_pg_sz[0x5];
2372 u8 reserved_at_118[0x3];
2373 u8 log_wq_sz[0x5];
2374
2375 u8 dbr_umem_valid[0x1];
2376 u8 wq_umem_valid[0x1];
2377 u8 reserved_at_122[0x1];
2378 u8 log_hairpin_num_packets[0x5];
2379 u8 reserved_at_128[0x3];
2380 u8 log_hairpin_data_sz[0x5];
2381
2382 u8 reserved_at_130[0x4];
2383 u8 log_wqe_num_of_strides[0x4];
2384 u8 two_byte_shift_en[0x1];
2385 u8 reserved_at_139[0x4];
2386 u8 log_wqe_stride_size[0x3];
2387
2388 u8 dbr_umem_id[0x20];
2389 u8 wq_umem_id[0x20];
2390
2391 u8 wq_umem_offset[0x40];
2392
2393 u8 headers_mkey[0x20];
2394
2395 u8 shampo_enable[0x1];
2396 u8 reserved_at_1e1[0x1];
2397 u8 shampo_mode[0x2];
2398 u8 reserved_at_1e4[0x1];
2399 u8 log_reservation_size[0x3];
2400 u8 reserved_at_1e8[0x5];
2401 u8 log_max_num_of_packets_per_reservation[0x3];
2402 u8 reserved_at_1f0[0x6];
2403 u8 log_headers_entry_size[0x2];
2404 u8 reserved_at_1f8[0x4];
2405 u8 log_headers_buffer_entry_num[0x4];
2406
2407 u8 reserved_at_200[0x400];
2408
2409 struct mlx5_ifc_cmd_pas_bits pas[];
2410};
2411
2412struct mlx5_ifc_rq_num_bits {
2413 u8 reserved_at_0[0x8];
2414 u8 rq_num[0x18];
2415};
2416
2417struct mlx5_ifc_rq_vhca_bits {
2418 u8 reserved_at_0[0x8];
2419 u8 rq_num[0x18];
2420 u8 reserved_at_20[0x10];
2421 u8 rq_vhca_id[0x10];
2422};
2423
2424struct mlx5_ifc_mac_address_layout_bits {
2425 u8 reserved_at_0[0x10];
2426 u8 mac_addr_47_32[0x10];
2427
2428 u8 mac_addr_31_0[0x20];
2429};
2430
2431struct mlx5_ifc_vlan_layout_bits {
2432 u8 reserved_at_0[0x14];
2433 u8 vlan[0x0c];
2434
2435 u8 reserved_at_20[0x20];
2436};
2437
2438struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2439 u8 reserved_at_0[0xa0];
2440
2441 u8 min_time_between_cnps[0x20];
2442
2443 u8 reserved_at_c0[0x12];
2444 u8 cnp_dscp[0x6];
2445 u8 reserved_at_d8[0x4];
2446 u8 cnp_prio_mode[0x1];
2447 u8 cnp_802p_prio[0x3];
2448
2449 u8 reserved_at_e0[0x720];
2450};
2451
2452struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2453 u8 reserved_at_0[0x60];
2454
2455 u8 reserved_at_60[0x4];
2456 u8 clamp_tgt_rate[0x1];
2457 u8 reserved_at_65[0x3];
2458 u8 clamp_tgt_rate_after_time_inc[0x1];
2459 u8 reserved_at_69[0x17];
2460
2461 u8 reserved_at_80[0x20];
2462
2463 u8 rpg_time_reset[0x20];
2464
2465 u8 rpg_byte_reset[0x20];
2466
2467 u8 rpg_threshold[0x20];
2468
2469 u8 rpg_max_rate[0x20];
2470
2471 u8 rpg_ai_rate[0x20];
2472
2473 u8 rpg_hai_rate[0x20];
2474
2475 u8 rpg_gd[0x20];
2476
2477 u8 rpg_min_dec_fac[0x20];
2478
2479 u8 rpg_min_rate[0x20];
2480
2481 u8 reserved_at_1c0[0xe0];
2482
2483 u8 rate_to_set_on_first_cnp[0x20];
2484
2485 u8 dce_tcp_g[0x20];
2486
2487 u8 dce_tcp_rtt[0x20];
2488
2489 u8 rate_reduce_monitor_period[0x20];
2490
2491 u8 reserved_at_320[0x20];
2492
2493 u8 initial_alpha_value[0x20];
2494
2495 u8 reserved_at_360[0x4a0];
2496};
2497
2498struct mlx5_ifc_cong_control_r_roce_general_bits {
2499 u8 reserved_at_0[0x80];
2500
2501 u8 reserved_at_80[0x10];
2502 u8 rtt_resp_dscp_valid[0x1];
2503 u8 reserved_at_91[0x9];
2504 u8 rtt_resp_dscp[0x6];
2505
2506 u8 reserved_at_a0[0x760];
2507};
2508
2509struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2510 u8 reserved_at_0[0x80];
2511
2512 u8 rppp_max_rps[0x20];
2513
2514 u8 rpg_time_reset[0x20];
2515
2516 u8 rpg_byte_reset[0x20];
2517
2518 u8 rpg_threshold[0x20];
2519
2520 u8 rpg_max_rate[0x20];
2521
2522 u8 rpg_ai_rate[0x20];
2523
2524 u8 rpg_hai_rate[0x20];
2525
2526 u8 rpg_gd[0x20];
2527
2528 u8 rpg_min_dec_fac[0x20];
2529
2530 u8 rpg_min_rate[0x20];
2531
2532 u8 reserved_at_1c0[0x640];
2533};
2534
2535enum {
2536 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
2537 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
2538 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
2539};
2540
2541struct mlx5_ifc_resize_field_select_bits {
2542 u8 resize_field_select[0x20];
2543};
2544
2545struct mlx5_ifc_resource_dump_bits {
2546 u8 more_dump[0x1];
2547 u8 inline_dump[0x1];
2548 u8 reserved_at_2[0xa];
2549 u8 seq_num[0x4];
2550 u8 segment_type[0x10];
2551
2552 u8 reserved_at_20[0x10];
2553 u8 vhca_id[0x10];
2554
2555 u8 index1[0x20];
2556
2557 u8 index2[0x20];
2558
2559 u8 num_of_obj1[0x10];
2560 u8 num_of_obj2[0x10];
2561
2562 u8 reserved_at_a0[0x20];
2563
2564 u8 device_opaque[0x40];
2565
2566 u8 mkey[0x20];
2567
2568 u8 size[0x20];
2569
2570 u8 address[0x40];
2571
2572 u8 inline_data[52][0x20];
2573};
2574
2575struct mlx5_ifc_resource_dump_menu_record_bits {
2576 u8 reserved_at_0[0x4];
2577 u8 num_of_obj2_supports_active[0x1];
2578 u8 num_of_obj2_supports_all[0x1];
2579 u8 must_have_num_of_obj2[0x1];
2580 u8 support_num_of_obj2[0x1];
2581 u8 num_of_obj1_supports_active[0x1];
2582 u8 num_of_obj1_supports_all[0x1];
2583 u8 must_have_num_of_obj1[0x1];
2584 u8 support_num_of_obj1[0x1];
2585 u8 must_have_index2[0x1];
2586 u8 support_index2[0x1];
2587 u8 must_have_index1[0x1];
2588 u8 support_index1[0x1];
2589 u8 segment_type[0x10];
2590
2591 u8 segment_name[4][0x20];
2592
2593 u8 index1_name[4][0x20];
2594
2595 u8 index2_name[4][0x20];
2596};
2597
2598struct mlx5_ifc_resource_dump_segment_header_bits {
2599 u8 length_dw[0x10];
2600 u8 segment_type[0x10];
2601};
2602
2603struct mlx5_ifc_resource_dump_command_segment_bits {
2604 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2605
2606 u8 segment_called[0x10];
2607 u8 vhca_id[0x10];
2608
2609 u8 index1[0x20];
2610
2611 u8 index2[0x20];
2612
2613 u8 num_of_obj1[0x10];
2614 u8 num_of_obj2[0x10];
2615};
2616
2617struct mlx5_ifc_resource_dump_error_segment_bits {
2618 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2619
2620 u8 reserved_at_20[0x10];
2621 u8 syndrome_id[0x10];
2622
2623 u8 reserved_at_40[0x40];
2624
2625 u8 error[8][0x20];
2626};
2627
2628struct mlx5_ifc_resource_dump_info_segment_bits {
2629 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2630
2631 u8 reserved_at_20[0x18];
2632 u8 dump_version[0x8];
2633
2634 u8 hw_version[0x20];
2635
2636 u8 fw_version[0x20];
2637};
2638
2639struct mlx5_ifc_resource_dump_menu_segment_bits {
2640 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2641
2642 u8 reserved_at_20[0x10];
2643 u8 num_of_records[0x10];
2644
2645 struct mlx5_ifc_resource_dump_menu_record_bits record[];
2646};
2647
2648struct mlx5_ifc_resource_dump_resource_segment_bits {
2649 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2650
2651 u8 reserved_at_20[0x20];
2652
2653 u8 index1[0x20];
2654
2655 u8 index2[0x20];
2656
2657 u8 payload[][0x20];
2658};
2659
2660struct mlx5_ifc_resource_dump_terminate_segment_bits {
2661 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2662};
2663
2664struct mlx5_ifc_menu_resource_dump_response_bits {
2665 struct mlx5_ifc_resource_dump_info_segment_bits info;
2666 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2667 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2668 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2669};
2670
2671enum {
2672 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
2673 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
2674 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
2675 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
2676};
2677
2678struct mlx5_ifc_modify_field_select_bits {
2679 u8 modify_field_select[0x20];
2680};
2681
2682struct mlx5_ifc_field_select_r_roce_np_bits {
2683 u8 field_select_r_roce_np[0x20];
2684};
2685
2686struct mlx5_ifc_field_select_r_roce_rp_bits {
2687 u8 field_select_r_roce_rp[0x20];
2688};
2689
2690enum {
2691 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
2692 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
2693 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
2694 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
2695 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
2696 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
2697 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
2698 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
2699 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
2700 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
2701};
2702
2703struct mlx5_ifc_field_select_802_1qau_rp_bits {
2704 u8 field_select_8021qaurp[0x20];
2705};
2706
2707struct mlx5_ifc_phys_layer_recovery_cntrs_bits {
2708 u8 total_successful_recovery_events[0x20];
2709
2710 u8 reserved_at_20[0x7a0];
2711};
2712
2713struct mlx5_ifc_phys_layer_cntrs_bits {
2714 u8 time_since_last_clear_high[0x20];
2715
2716 u8 time_since_last_clear_low[0x20];
2717
2718 u8 symbol_errors_high[0x20];
2719
2720 u8 symbol_errors_low[0x20];
2721
2722 u8 sync_headers_errors_high[0x20];
2723
2724 u8 sync_headers_errors_low[0x20];
2725
2726 u8 edpl_bip_errors_lane0_high[0x20];
2727
2728 u8 edpl_bip_errors_lane0_low[0x20];
2729
2730 u8 edpl_bip_errors_lane1_high[0x20];
2731
2732 u8 edpl_bip_errors_lane1_low[0x20];
2733
2734 u8 edpl_bip_errors_lane2_high[0x20];
2735
2736 u8 edpl_bip_errors_lane2_low[0x20];
2737
2738 u8 edpl_bip_errors_lane3_high[0x20];
2739
2740 u8 edpl_bip_errors_lane3_low[0x20];
2741
2742 u8 fc_fec_corrected_blocks_lane0_high[0x20];
2743
2744 u8 fc_fec_corrected_blocks_lane0_low[0x20];
2745
2746 u8 fc_fec_corrected_blocks_lane1_high[0x20];
2747
2748 u8 fc_fec_corrected_blocks_lane1_low[0x20];
2749
2750 u8 fc_fec_corrected_blocks_lane2_high[0x20];
2751
2752 u8 fc_fec_corrected_blocks_lane2_low[0x20];
2753
2754 u8 fc_fec_corrected_blocks_lane3_high[0x20];
2755
2756 u8 fc_fec_corrected_blocks_lane3_low[0x20];
2757
2758 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
2759
2760 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2761
2762 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2763
2764 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2765
2766 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2767
2768 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2769
2770 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2771
2772 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2773
2774 u8 rs_fec_corrected_blocks_high[0x20];
2775
2776 u8 rs_fec_corrected_blocks_low[0x20];
2777
2778 u8 rs_fec_uncorrectable_blocks_high[0x20];
2779
2780 u8 rs_fec_uncorrectable_blocks_low[0x20];
2781
2782 u8 rs_fec_no_errors_blocks_high[0x20];
2783
2784 u8 rs_fec_no_errors_blocks_low[0x20];
2785
2786 u8 rs_fec_single_error_blocks_high[0x20];
2787
2788 u8 rs_fec_single_error_blocks_low[0x20];
2789
2790 u8 rs_fec_corrected_symbols_total_high[0x20];
2791
2792 u8 rs_fec_corrected_symbols_total_low[0x20];
2793
2794 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2795
2796 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2797
2798 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2799
2800 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2801
2802 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2803
2804 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2805
2806 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2807
2808 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2809
2810 u8 link_down_events[0x20];
2811
2812 u8 successful_recovery_events[0x20];
2813
2814 u8 reserved_at_640[0x180];
2815};
2816
2817struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2818 u8 time_since_last_clear_high[0x20];
2819
2820 u8 time_since_last_clear_low[0x20];
2821
2822 u8 phy_received_bits_high[0x20];
2823
2824 u8 phy_received_bits_low[0x20];
2825
2826 u8 phy_symbol_errors_high[0x20];
2827
2828 u8 phy_symbol_errors_low[0x20];
2829
2830 u8 phy_corrected_bits_high[0x20];
2831
2832 u8 phy_corrected_bits_low[0x20];
2833
2834 u8 phy_corrected_bits_lane0_high[0x20];
2835
2836 u8 phy_corrected_bits_lane0_low[0x20];
2837
2838 u8 phy_corrected_bits_lane1_high[0x20];
2839
2840 u8 phy_corrected_bits_lane1_low[0x20];
2841
2842 u8 phy_corrected_bits_lane2_high[0x20];
2843
2844 u8 phy_corrected_bits_lane2_low[0x20];
2845
2846 u8 phy_corrected_bits_lane3_high[0x20];
2847
2848 u8 phy_corrected_bits_lane3_low[0x20];
2849
2850 u8 reserved_at_200[0x5c0];
2851};
2852
2853struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2854 u8 symbol_error_counter[0x10];
2855
2856 u8 link_error_recovery_counter[0x8];
2857
2858 u8 link_downed_counter[0x8];
2859
2860 u8 port_rcv_errors[0x10];
2861
2862 u8 port_rcv_remote_physical_errors[0x10];
2863
2864 u8 port_rcv_switch_relay_errors[0x10];
2865
2866 u8 port_xmit_discards[0x10];
2867
2868 u8 port_xmit_constraint_errors[0x8];
2869
2870 u8 port_rcv_constraint_errors[0x8];
2871
2872 u8 reserved_at_70[0x8];
2873
2874 u8 link_overrun_errors[0x8];
2875
2876 u8 reserved_at_80[0x10];
2877
2878 u8 vl_15_dropped[0x10];
2879
2880 u8 reserved_at_a0[0x80];
2881
2882 u8 port_xmit_wait[0x20];
2883};
2884
2885struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits {
2886 u8 reserved_at_0[0x300];
2887
2888 u8 port_xmit_data_high[0x20];
2889
2890 u8 port_xmit_data_low[0x20];
2891
2892 u8 port_rcv_data_high[0x20];
2893
2894 u8 port_rcv_data_low[0x20];
2895
2896 u8 port_xmit_pkts_high[0x20];
2897
2898 u8 port_xmit_pkts_low[0x20];
2899
2900 u8 port_rcv_pkts_high[0x20];
2901
2902 u8 port_rcv_pkts_low[0x20];
2903
2904 u8 reserved_at_400[0x80];
2905
2906 u8 port_unicast_xmit_pkts_high[0x20];
2907
2908 u8 port_unicast_xmit_pkts_low[0x20];
2909
2910 u8 port_multicast_xmit_pkts_high[0x20];
2911
2912 u8 port_multicast_xmit_pkts_low[0x20];
2913
2914 u8 port_unicast_rcv_pkts_high[0x20];
2915
2916 u8 port_unicast_rcv_pkts_low[0x20];
2917
2918 u8 port_multicast_rcv_pkts_high[0x20];
2919
2920 u8 port_multicast_rcv_pkts_low[0x20];
2921
2922 u8 reserved_at_580[0x240];
2923};
2924
2925struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2926 u8 transmit_queue_high[0x20];
2927
2928 u8 transmit_queue_low[0x20];
2929
2930 u8 no_buffer_discard_uc_high[0x20];
2931
2932 u8 no_buffer_discard_uc_low[0x20];
2933
2934 u8 reserved_at_80[0x740];
2935};
2936
2937struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2938 u8 wred_discard_high[0x20];
2939
2940 u8 wred_discard_low[0x20];
2941
2942 u8 ecn_marked_tc_high[0x20];
2943
2944 u8 ecn_marked_tc_low[0x20];
2945
2946 u8 reserved_at_80[0x740];
2947};
2948
2949struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2950 u8 rx_octets_high[0x20];
2951
2952 u8 rx_octets_low[0x20];
2953
2954 u8 reserved_at_40[0xc0];
2955
2956 u8 rx_frames_high[0x20];
2957
2958 u8 rx_frames_low[0x20];
2959
2960 u8 tx_octets_high[0x20];
2961
2962 u8 tx_octets_low[0x20];
2963
2964 u8 reserved_at_180[0xc0];
2965
2966 u8 tx_frames_high[0x20];
2967
2968 u8 tx_frames_low[0x20];
2969
2970 u8 rx_pause_high[0x20];
2971
2972 u8 rx_pause_low[0x20];
2973
2974 u8 rx_pause_duration_high[0x20];
2975
2976 u8 rx_pause_duration_low[0x20];
2977
2978 u8 tx_pause_high[0x20];
2979
2980 u8 tx_pause_low[0x20];
2981
2982 u8 tx_pause_duration_high[0x20];
2983
2984 u8 tx_pause_duration_low[0x20];
2985
2986 u8 rx_pause_transition_high[0x20];
2987
2988 u8 rx_pause_transition_low[0x20];
2989
2990 u8 rx_discards_high[0x20];
2991
2992 u8 rx_discards_low[0x20];
2993
2994 u8 device_stall_minor_watermark_cnt_high[0x20];
2995
2996 u8 device_stall_minor_watermark_cnt_low[0x20];
2997
2998 u8 device_stall_critical_watermark_cnt_high[0x20];
2999
3000 u8 device_stall_critical_watermark_cnt_low[0x20];
3001
3002 u8 reserved_at_480[0x340];
3003};
3004
3005struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
3006 u8 port_transmit_wait_high[0x20];
3007
3008 u8 port_transmit_wait_low[0x20];
3009
3010 u8 reserved_at_40[0x100];
3011
3012 u8 rx_buffer_almost_full_high[0x20];
3013
3014 u8 rx_buffer_almost_full_low[0x20];
3015
3016 u8 rx_buffer_full_high[0x20];
3017
3018 u8 rx_buffer_full_low[0x20];
3019
3020 u8 rx_icrc_encapsulated_high[0x20];
3021
3022 u8 rx_icrc_encapsulated_low[0x20];
3023
3024 u8 reserved_at_200[0x5c0];
3025};
3026
3027struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
3028 u8 dot3stats_alignment_errors_high[0x20];
3029
3030 u8 dot3stats_alignment_errors_low[0x20];
3031
3032 u8 dot3stats_fcs_errors_high[0x20];
3033
3034 u8 dot3stats_fcs_errors_low[0x20];
3035
3036 u8 dot3stats_single_collision_frames_high[0x20];
3037
3038 u8 dot3stats_single_collision_frames_low[0x20];
3039
3040 u8 dot3stats_multiple_collision_frames_high[0x20];
3041
3042 u8 dot3stats_multiple_collision_frames_low[0x20];
3043
3044 u8 dot3stats_sqe_test_errors_high[0x20];
3045
3046 u8 dot3stats_sqe_test_errors_low[0x20];
3047
3048 u8 dot3stats_deferred_transmissions_high[0x20];
3049
3050 u8 dot3stats_deferred_transmissions_low[0x20];
3051
3052 u8 dot3stats_late_collisions_high[0x20];
3053
3054 u8 dot3stats_late_collisions_low[0x20];
3055
3056 u8 dot3stats_excessive_collisions_high[0x20];
3057
3058 u8 dot3stats_excessive_collisions_low[0x20];
3059
3060 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
3061
3062 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
3063
3064 u8 dot3stats_carrier_sense_errors_high[0x20];
3065
3066 u8 dot3stats_carrier_sense_errors_low[0x20];
3067
3068 u8 dot3stats_frame_too_longs_high[0x20];
3069
3070 u8 dot3stats_frame_too_longs_low[0x20];
3071
3072 u8 dot3stats_internal_mac_receive_errors_high[0x20];
3073
3074 u8 dot3stats_internal_mac_receive_errors_low[0x20];
3075
3076 u8 dot3stats_symbol_errors_high[0x20];
3077
3078 u8 dot3stats_symbol_errors_low[0x20];
3079
3080 u8 dot3control_in_unknown_opcodes_high[0x20];
3081
3082 u8 dot3control_in_unknown_opcodes_low[0x20];
3083
3084 u8 dot3in_pause_frames_high[0x20];
3085
3086 u8 dot3in_pause_frames_low[0x20];
3087
3088 u8 dot3out_pause_frames_high[0x20];
3089
3090 u8 dot3out_pause_frames_low[0x20];
3091
3092 u8 reserved_at_400[0x3c0];
3093};
3094
3095struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
3096 u8 ether_stats_drop_events_high[0x20];
3097
3098 u8 ether_stats_drop_events_low[0x20];
3099
3100 u8 ether_stats_octets_high[0x20];
3101
3102 u8 ether_stats_octets_low[0x20];
3103
3104 u8 ether_stats_pkts_high[0x20];
3105
3106 u8 ether_stats_pkts_low[0x20];
3107
3108 u8 ether_stats_broadcast_pkts_high[0x20];
3109
3110 u8 ether_stats_broadcast_pkts_low[0x20];
3111
3112 u8 ether_stats_multicast_pkts_high[0x20];
3113
3114 u8 ether_stats_multicast_pkts_low[0x20];
3115
3116 u8 ether_stats_crc_align_errors_high[0x20];
3117
3118 u8 ether_stats_crc_align_errors_low[0x20];
3119
3120 u8 ether_stats_undersize_pkts_high[0x20];
3121
3122 u8 ether_stats_undersize_pkts_low[0x20];
3123
3124 u8 ether_stats_oversize_pkts_high[0x20];
3125
3126 u8 ether_stats_oversize_pkts_low[0x20];
3127
3128 u8 ether_stats_fragments_high[0x20];
3129
3130 u8 ether_stats_fragments_low[0x20];
3131
3132 u8 ether_stats_jabbers_high[0x20];
3133
3134 u8 ether_stats_jabbers_low[0x20];
3135
3136 u8 ether_stats_collisions_high[0x20];
3137
3138 u8 ether_stats_collisions_low[0x20];
3139
3140 u8 ether_stats_pkts64octets_high[0x20];
3141
3142 u8 ether_stats_pkts64octets_low[0x20];
3143
3144 u8 ether_stats_pkts65to127octets_high[0x20];
3145
3146 u8 ether_stats_pkts65to127octets_low[0x20];
3147
3148 u8 ether_stats_pkts128to255octets_high[0x20];
3149
3150 u8 ether_stats_pkts128to255octets_low[0x20];
3151
3152 u8 ether_stats_pkts256to511octets_high[0x20];
3153
3154 u8 ether_stats_pkts256to511octets_low[0x20];
3155
3156 u8 ether_stats_pkts512to1023octets_high[0x20];
3157
3158 u8 ether_stats_pkts512to1023octets_low[0x20];
3159
3160 u8 ether_stats_pkts1024to1518octets_high[0x20];
3161
3162 u8 ether_stats_pkts1024to1518octets_low[0x20];
3163
3164 u8 ether_stats_pkts1519to2047octets_high[0x20];
3165
3166 u8 ether_stats_pkts1519to2047octets_low[0x20];
3167
3168 u8 ether_stats_pkts2048to4095octets_high[0x20];
3169
3170 u8 ether_stats_pkts2048to4095octets_low[0x20];
3171
3172 u8 ether_stats_pkts4096to8191octets_high[0x20];
3173
3174 u8 ether_stats_pkts4096to8191octets_low[0x20];
3175
3176 u8 ether_stats_pkts8192to10239octets_high[0x20];
3177
3178 u8 ether_stats_pkts8192to10239octets_low[0x20];
3179
3180 u8 reserved_at_540[0x280];
3181};
3182
3183struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
3184 u8 if_in_octets_high[0x20];
3185
3186 u8 if_in_octets_low[0x20];
3187
3188 u8 if_in_ucast_pkts_high[0x20];
3189
3190 u8 if_in_ucast_pkts_low[0x20];
3191
3192 u8 if_in_discards_high[0x20];
3193
3194 u8 if_in_discards_low[0x20];
3195
3196 u8 if_in_errors_high[0x20];
3197
3198 u8 if_in_errors_low[0x20];
3199
3200 u8 if_in_unknown_protos_high[0x20];
3201
3202 u8 if_in_unknown_protos_low[0x20];
3203
3204 u8 if_out_octets_high[0x20];
3205
3206 u8 if_out_octets_low[0x20];
3207
3208 u8 if_out_ucast_pkts_high[0x20];
3209
3210 u8 if_out_ucast_pkts_low[0x20];
3211
3212 u8 if_out_discards_high[0x20];
3213
3214 u8 if_out_discards_low[0x20];
3215
3216 u8 if_out_errors_high[0x20];
3217
3218 u8 if_out_errors_low[0x20];
3219
3220 u8 if_in_multicast_pkts_high[0x20];
3221
3222 u8 if_in_multicast_pkts_low[0x20];
3223
3224 u8 if_in_broadcast_pkts_high[0x20];
3225
3226 u8 if_in_broadcast_pkts_low[0x20];
3227
3228 u8 if_out_multicast_pkts_high[0x20];
3229
3230 u8 if_out_multicast_pkts_low[0x20];
3231
3232 u8 if_out_broadcast_pkts_high[0x20];
3233
3234 u8 if_out_broadcast_pkts_low[0x20];
3235
3236 u8 reserved_at_340[0x480];
3237};
3238
3239struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
3240 u8 a_frames_transmitted_ok_high[0x20];
3241
3242 u8 a_frames_transmitted_ok_low[0x20];
3243
3244 u8 a_frames_received_ok_high[0x20];
3245
3246 u8 a_frames_received_ok_low[0x20];
3247
3248 u8 a_frame_check_sequence_errors_high[0x20];
3249
3250 u8 a_frame_check_sequence_errors_low[0x20];
3251
3252 u8 a_alignment_errors_high[0x20];
3253
3254 u8 a_alignment_errors_low[0x20];
3255
3256 u8 a_octets_transmitted_ok_high[0x20];
3257
3258 u8 a_octets_transmitted_ok_low[0x20];
3259
3260 u8 a_octets_received_ok_high[0x20];
3261
3262 u8 a_octets_received_ok_low[0x20];
3263
3264 u8 a_multicast_frames_xmitted_ok_high[0x20];
3265
3266 u8 a_multicast_frames_xmitted_ok_low[0x20];
3267
3268 u8 a_broadcast_frames_xmitted_ok_high[0x20];
3269
3270 u8 a_broadcast_frames_xmitted_ok_low[0x20];
3271
3272 u8 a_multicast_frames_received_ok_high[0x20];
3273
3274 u8 a_multicast_frames_received_ok_low[0x20];
3275
3276 u8 a_broadcast_frames_received_ok_high[0x20];
3277
3278 u8 a_broadcast_frames_received_ok_low[0x20];
3279
3280 u8 a_in_range_length_errors_high[0x20];
3281
3282 u8 a_in_range_length_errors_low[0x20];
3283
3284 u8 a_out_of_range_length_field_high[0x20];
3285
3286 u8 a_out_of_range_length_field_low[0x20];
3287
3288 u8 a_frame_too_long_errors_high[0x20];
3289
3290 u8 a_frame_too_long_errors_low[0x20];
3291
3292 u8 a_symbol_error_during_carrier_high[0x20];
3293
3294 u8 a_symbol_error_during_carrier_low[0x20];
3295
3296 u8 a_mac_control_frames_transmitted_high[0x20];
3297
3298 u8 a_mac_control_frames_transmitted_low[0x20];
3299
3300 u8 a_mac_control_frames_received_high[0x20];
3301
3302 u8 a_mac_control_frames_received_low[0x20];
3303
3304 u8 a_unsupported_opcodes_received_high[0x20];
3305
3306 u8 a_unsupported_opcodes_received_low[0x20];
3307
3308 u8 a_pause_mac_ctrl_frames_received_high[0x20];
3309
3310 u8 a_pause_mac_ctrl_frames_received_low[0x20];
3311
3312 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
3313
3314 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
3315
3316 u8 reserved_at_4c0[0x300];
3317};
3318
3319struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
3320 u8 life_time_counter_high[0x20];
3321
3322 u8 life_time_counter_low[0x20];
3323
3324 u8 rx_errors[0x20];
3325
3326 u8 tx_errors[0x20];
3327
3328 u8 l0_to_recovery_eieos[0x20];
3329
3330 u8 l0_to_recovery_ts[0x20];
3331
3332 u8 l0_to_recovery_framing[0x20];
3333
3334 u8 l0_to_recovery_retrain[0x20];
3335
3336 u8 crc_error_dllp[0x20];
3337
3338 u8 crc_error_tlp[0x20];
3339
3340 u8 tx_overflow_buffer_pkt_high[0x20];
3341
3342 u8 tx_overflow_buffer_pkt_low[0x20];
3343
3344 u8 outbound_stalled_reads[0x20];
3345
3346 u8 outbound_stalled_writes[0x20];
3347
3348 u8 outbound_stalled_reads_events[0x20];
3349
3350 u8 outbound_stalled_writes_events[0x20];
3351
3352 u8 reserved_at_200[0x5c0];
3353};
3354
3355struct mlx5_ifc_cmd_inter_comp_event_bits {
3356 u8 command_completion_vector[0x20];
3357
3358 u8 reserved_at_20[0xc0];
3359};
3360
3361struct mlx5_ifc_stall_vl_event_bits {
3362 u8 reserved_at_0[0x18];
3363 u8 port_num[0x1];
3364 u8 reserved_at_19[0x3];
3365 u8 vl[0x4];
3366
3367 u8 reserved_at_20[0xa0];
3368};
3369
3370struct mlx5_ifc_db_bf_congestion_event_bits {
3371 u8 event_subtype[0x8];
3372 u8 reserved_at_8[0x8];
3373 u8 congestion_level[0x8];
3374 u8 reserved_at_18[0x8];
3375
3376 u8 reserved_at_20[0xa0];
3377};
3378
3379struct mlx5_ifc_gpio_event_bits {
3380 u8 reserved_at_0[0x60];
3381
3382 u8 gpio_event_hi[0x20];
3383
3384 u8 gpio_event_lo[0x20];
3385
3386 u8 reserved_at_a0[0x40];
3387};
3388
3389struct mlx5_ifc_port_state_change_event_bits {
3390 u8 reserved_at_0[0x40];
3391
3392 u8 port_num[0x4];
3393 u8 reserved_at_44[0x1c];
3394
3395 u8 reserved_at_60[0x80];
3396};
3397
3398struct mlx5_ifc_dropped_packet_logged_bits {
3399 u8 reserved_at_0[0xe0];
3400};
3401
3402struct mlx5_ifc_nic_cap_reg_bits {
3403 u8 reserved_at_0[0x1a];
3404 u8 vhca_icm_ctrl[0x1];
3405 u8 reserved_at_1b[0x5];
3406
3407 u8 reserved_at_20[0x60];
3408};
3409
3410struct mlx5_ifc_default_timeout_bits {
3411 u8 to_multiplier[0x3];
3412 u8 reserved_at_3[0x9];
3413 u8 to_value[0x14];
3414};
3415
3416struct mlx5_ifc_dtor_reg_bits {
3417 u8 reserved_at_0[0x20];
3418
3419 struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3420
3421 u8 reserved_at_40[0x60];
3422
3423 struct mlx5_ifc_default_timeout_bits health_poll_to;
3424
3425 struct mlx5_ifc_default_timeout_bits full_crdump_to;
3426
3427 struct mlx5_ifc_default_timeout_bits fw_reset_to;
3428
3429 struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3430
3431 struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3432
3433 struct mlx5_ifc_default_timeout_bits tear_down_to;
3434
3435 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3436
3437 struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3438
3439 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3440
3441 struct mlx5_ifc_default_timeout_bits reset_unload_to;
3442
3443 u8 reserved_at_1c0[0x20];
3444};
3445
3446struct mlx5_ifc_vhca_icm_ctrl_reg_bits {
3447 u8 vhca_id_valid[0x1];
3448 u8 reserved_at_1[0xf];
3449 u8 vhca_id[0x10];
3450
3451 u8 reserved_at_20[0xa0];
3452
3453 u8 cur_alloc_icm[0x20];
3454
3455 u8 reserved_at_e0[0x120];
3456};
3457
3458enum {
3459 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
3460 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
3461};
3462
3463struct mlx5_ifc_cq_error_bits {
3464 u8 reserved_at_0[0x8];
3465 u8 cqn[0x18];
3466
3467 u8 reserved_at_20[0x20];
3468
3469 u8 reserved_at_40[0x18];
3470 u8 syndrome[0x8];
3471
3472 u8 reserved_at_60[0x80];
3473};
3474
3475struct mlx5_ifc_rdma_page_fault_event_bits {
3476 u8 bytes_committed[0x20];
3477
3478 u8 r_key[0x20];
3479
3480 u8 reserved_at_40[0x10];
3481 u8 packet_len[0x10];
3482
3483 u8 rdma_op_len[0x20];
3484
3485 u8 rdma_va[0x40];
3486
3487 u8 reserved_at_c0[0x5];
3488 u8 rdma[0x1];
3489 u8 write[0x1];
3490 u8 requestor[0x1];
3491 u8 qp_number[0x18];
3492};
3493
3494struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3495 u8 bytes_committed[0x20];
3496
3497 u8 reserved_at_20[0x10];
3498 u8 wqe_index[0x10];
3499
3500 u8 reserved_at_40[0x10];
3501 u8 len[0x10];
3502
3503 u8 reserved_at_60[0x60];
3504
3505 u8 reserved_at_c0[0x5];
3506 u8 rdma[0x1];
3507 u8 write_read[0x1];
3508 u8 requestor[0x1];
3509 u8 qpn[0x18];
3510};
3511
3512struct mlx5_ifc_qp_events_bits {
3513 u8 reserved_at_0[0xa0];
3514
3515 u8 type[0x8];
3516 u8 reserved_at_a8[0x18];
3517
3518 u8 reserved_at_c0[0x8];
3519 u8 qpn_rqn_sqn[0x18];
3520};
3521
3522struct mlx5_ifc_dct_events_bits {
3523 u8 reserved_at_0[0xc0];
3524
3525 u8 reserved_at_c0[0x8];
3526 u8 dct_number[0x18];
3527};
3528
3529struct mlx5_ifc_comp_event_bits {
3530 u8 reserved_at_0[0xc0];
3531
3532 u8 reserved_at_c0[0x8];
3533 u8 cq_number[0x18];
3534};
3535
3536enum {
3537 MLX5_QPC_STATE_RST = 0x0,
3538 MLX5_QPC_STATE_INIT = 0x1,
3539 MLX5_QPC_STATE_RTR = 0x2,
3540 MLX5_QPC_STATE_RTS = 0x3,
3541 MLX5_QPC_STATE_SQER = 0x4,
3542 MLX5_QPC_STATE_ERR = 0x6,
3543 MLX5_QPC_STATE_SQD = 0x7,
3544 MLX5_QPC_STATE_SUSPENDED = 0x9,
3545};
3546
3547enum {
3548 MLX5_QPC_ST_RC = 0x0,
3549 MLX5_QPC_ST_UC = 0x1,
3550 MLX5_QPC_ST_UD = 0x2,
3551 MLX5_QPC_ST_XRC = 0x3,
3552 MLX5_QPC_ST_DCI = 0x5,
3553 MLX5_QPC_ST_QP0 = 0x7,
3554 MLX5_QPC_ST_QP1 = 0x8,
3555 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
3556 MLX5_QPC_ST_REG_UMR = 0xc,
3557};
3558
3559enum {
3560 MLX5_QPC_PM_STATE_ARMED = 0x0,
3561 MLX5_QPC_PM_STATE_REARM = 0x1,
3562 MLX5_QPC_PM_STATE_RESERVED = 0x2,
3563 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
3564};
3565
3566enum {
3567 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
3568};
3569
3570enum {
3571 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
3572 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
3573};
3574
3575enum {
3576 MLX5_QPC_MTU_256_BYTES = 0x1,
3577 MLX5_QPC_MTU_512_BYTES = 0x2,
3578 MLX5_QPC_MTU_1K_BYTES = 0x3,
3579 MLX5_QPC_MTU_2K_BYTES = 0x4,
3580 MLX5_QPC_MTU_4K_BYTES = 0x5,
3581 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
3582};
3583
3584enum {
3585 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
3586 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
3587 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
3588 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
3589 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
3590 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
3591 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
3592 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
3593};
3594
3595enum {
3596 MLX5_QPC_CS_REQ_DISABLE = 0x0,
3597 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
3598 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
3599};
3600
3601enum {
3602 MLX5_QPC_CS_RES_DISABLE = 0x0,
3603 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
3604 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
3605};
3606
3607enum {
3608 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3609 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1,
3610 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
3611};
3612
3613struct mlx5_ifc_qpc_bits {
3614 u8 state[0x4];
3615 u8 lag_tx_port_affinity[0x4];
3616 u8 st[0x8];
3617 u8 reserved_at_10[0x2];
3618 u8 isolate_vl_tc[0x1];
3619 u8 pm_state[0x2];
3620 u8 reserved_at_15[0x1];
3621 u8 req_e2e_credit_mode[0x2];
3622 u8 offload_type[0x4];
3623 u8 end_padding_mode[0x2];
3624 u8 reserved_at_1e[0x2];
3625
3626 u8 wq_signature[0x1];
3627 u8 block_lb_mc[0x1];
3628 u8 atomic_like_write_en[0x1];
3629 u8 latency_sensitive[0x1];
3630 u8 reserved_at_24[0x1];
3631 u8 drain_sigerr[0x1];
3632 u8 reserved_at_26[0x1];
3633 u8 dp_ordering_force[0x1];
3634 u8 pd[0x18];
3635
3636 u8 mtu[0x3];
3637 u8 log_msg_max[0x5];
3638 u8 reserved_at_48[0x1];
3639 u8 log_rq_size[0x4];
3640 u8 log_rq_stride[0x3];
3641 u8 no_sq[0x1];
3642 u8 log_sq_size[0x4];
3643 u8 reserved_at_55[0x1];
3644 u8 retry_mode[0x2];
3645 u8 ts_format[0x2];
3646 u8 reserved_at_5a[0x1];
3647 u8 rlky[0x1];
3648 u8 ulp_stateless_offload_mode[0x4];
3649
3650 u8 counter_set_id[0x8];
3651 u8 uar_page[0x18];
3652
3653 u8 reserved_at_80[0x8];
3654 u8 user_index[0x18];
3655
3656 u8 reserved_at_a0[0x3];
3657 u8 log_page_size[0x5];
3658 u8 remote_qpn[0x18];
3659
3660 struct mlx5_ifc_ads_bits primary_address_path;
3661
3662 struct mlx5_ifc_ads_bits secondary_address_path;
3663
3664 u8 log_ack_req_freq[0x4];
3665 u8 reserved_at_384[0x4];
3666 u8 log_sra_max[0x3];
3667 u8 reserved_at_38b[0x2];
3668 u8 retry_count[0x3];
3669 u8 rnr_retry[0x3];
3670 u8 reserved_at_393[0x1];
3671 u8 fre[0x1];
3672 u8 cur_rnr_retry[0x3];
3673 u8 cur_retry_count[0x3];
3674 u8 reserved_at_39b[0x5];
3675
3676 u8 reserved_at_3a0[0x20];
3677
3678 u8 reserved_at_3c0[0x8];
3679 u8 next_send_psn[0x18];
3680
3681 u8 reserved_at_3e0[0x3];
3682 u8 log_num_dci_stream_channels[0x5];
3683 u8 cqn_snd[0x18];
3684
3685 u8 reserved_at_400[0x3];
3686 u8 log_num_dci_errored_streams[0x5];
3687 u8 deth_sqpn[0x18];
3688
3689 u8 reserved_at_420[0x20];
3690
3691 u8 reserved_at_440[0x8];
3692 u8 last_acked_psn[0x18];
3693
3694 u8 reserved_at_460[0x8];
3695 u8 ssn[0x18];
3696
3697 u8 reserved_at_480[0x8];
3698 u8 log_rra_max[0x3];
3699 u8 reserved_at_48b[0x1];
3700 u8 atomic_mode[0x4];
3701 u8 rre[0x1];
3702 u8 rwe[0x1];
3703 u8 rae[0x1];
3704 u8 reserved_at_493[0x1];
3705 u8 page_offset[0x6];
3706 u8 reserved_at_49a[0x2];
3707 u8 dp_ordering_1[0x1];
3708 u8 cd_slave_receive[0x1];
3709 u8 cd_slave_send[0x1];
3710 u8 cd_master[0x1];
3711
3712 u8 reserved_at_4a0[0x3];
3713 u8 min_rnr_nak[0x5];
3714 u8 next_rcv_psn[0x18];
3715
3716 u8 reserved_at_4c0[0x8];
3717 u8 xrcd[0x18];
3718
3719 u8 reserved_at_4e0[0x8];
3720 u8 cqn_rcv[0x18];
3721
3722 u8 dbr_addr[0x40];
3723
3724 u8 q_key[0x20];
3725
3726 u8 reserved_at_560[0x5];
3727 u8 rq_type[0x3];
3728 u8 srqn_rmpn_xrqn[0x18];
3729
3730 u8 reserved_at_580[0x8];
3731 u8 rmsn[0x18];
3732
3733 u8 hw_sq_wqebb_counter[0x10];
3734 u8 sw_sq_wqebb_counter[0x10];
3735
3736 u8 hw_rq_counter[0x20];
3737
3738 u8 sw_rq_counter[0x20];
3739
3740 u8 reserved_at_600[0x20];
3741
3742 u8 reserved_at_620[0xf];
3743 u8 cgs[0x1];
3744 u8 cs_req[0x8];
3745 u8 cs_res[0x8];
3746
3747 u8 dc_access_key[0x40];
3748
3749 u8 reserved_at_680[0x3];
3750 u8 dbr_umem_valid[0x1];
3751
3752 u8 reserved_at_684[0xbc];
3753};
3754
3755struct mlx5_ifc_roce_addr_layout_bits {
3756 u8 source_l3_address[16][0x8];
3757
3758 u8 reserved_at_80[0x3];
3759 u8 vlan_valid[0x1];
3760 u8 vlan_id[0xc];
3761 u8 source_mac_47_32[0x10];
3762
3763 u8 source_mac_31_0[0x20];
3764
3765 u8 reserved_at_c0[0x14];
3766 u8 roce_l3_type[0x4];
3767 u8 roce_version[0x8];
3768
3769 u8 reserved_at_e0[0x20];
3770};
3771
3772struct mlx5_ifc_crypto_cap_bits {
3773 u8 reserved_at_0[0x3];
3774 u8 synchronize_dek[0x1];
3775 u8 int_kek_manual[0x1];
3776 u8 int_kek_auto[0x1];
3777 u8 reserved_at_6[0x1a];
3778
3779 u8 reserved_at_20[0x3];
3780 u8 log_dek_max_alloc[0x5];
3781 u8 reserved_at_28[0x3];
3782 u8 log_max_num_deks[0x5];
3783 u8 reserved_at_30[0x10];
3784
3785 u8 reserved_at_40[0x20];
3786
3787 u8 reserved_at_60[0x3];
3788 u8 log_dek_granularity[0x5];
3789 u8 reserved_at_68[0x3];
3790 u8 log_max_num_int_kek[0x5];
3791 u8 sw_wrapped_dek[0x10];
3792
3793 u8 reserved_at_80[0x780];
3794};
3795
3796struct mlx5_ifc_shampo_cap_bits {
3797 u8 reserved_at_0[0x3];
3798 u8 shampo_log_max_reservation_size[0x5];
3799 u8 reserved_at_8[0x3];
3800 u8 shampo_log_min_reservation_size[0x5];
3801 u8 shampo_min_mss_size[0x10];
3802
3803 u8 shampo_header_split[0x1];
3804 u8 shampo_header_split_data_merge[0x1];
3805 u8 reserved_at_22[0x1];
3806 u8 shampo_log_max_headers_entry_size[0x5];
3807 u8 reserved_at_28[0x18];
3808
3809 u8 reserved_at_40[0x7c0];
3810};
3811
3812union mlx5_ifc_hca_cap_union_bits {
3813 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3814 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3815 struct mlx5_ifc_odp_cap_bits odp_cap;
3816 struct mlx5_ifc_atomic_caps_bits atomic_caps;
3817 struct mlx5_ifc_roce_cap_bits roce_cap;
3818 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3819 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3820 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3821 struct mlx5_ifc_wqe_based_flow_table_cap_bits wqe_based_flow_table_cap;
3822 struct mlx5_ifc_esw_cap_bits esw_cap;
3823 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3824 struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3825 struct mlx5_ifc_qos_cap_bits qos_cap;
3826 struct mlx5_ifc_debug_cap_bits debug_cap;
3827 struct mlx5_ifc_fpga_cap_bits fpga_cap;
3828 struct mlx5_ifc_tls_cap_bits tls_cap;
3829 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3830 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3831 struct mlx5_ifc_macsec_cap_bits macsec_cap;
3832 struct mlx5_ifc_crypto_cap_bits crypto_cap;
3833 struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3834 struct mlx5_ifc_psp_cap_bits psp_cap;
3835 u8 reserved_at_0[0x8000];
3836};
3837
3838enum {
3839 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
3840 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
3841 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
3842 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
3843 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3844 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
3845 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
3846 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
3847 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3848 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
3849 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3850 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3851 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3852 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3853};
3854
3855enum {
3856 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
3857 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
3858 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
3859};
3860
3861enum {
3862 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
3863 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1,
3864 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2,
3865};
3866
3867struct mlx5_ifc_vlan_bits {
3868 u8 ethtype[0x10];
3869 u8 prio[0x3];
3870 u8 cfi[0x1];
3871 u8 vid[0xc];
3872};
3873
3874enum {
3875 MLX5_FLOW_METER_COLOR_RED = 0x0,
3876 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
3877 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
3878 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
3879};
3880
3881enum {
3882 MLX5_EXE_ASO_FLOW_METER = 0x2,
3883};
3884
3885struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3886 u8 return_reg_id[0x4];
3887 u8 aso_type[0x4];
3888 u8 reserved_at_8[0x14];
3889 u8 action[0x1];
3890 u8 init_color[0x2];
3891 u8 meter_id[0x1];
3892};
3893
3894union mlx5_ifc_exe_aso_ctrl {
3895 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3896};
3897
3898struct mlx5_ifc_execute_aso_bits {
3899 u8 valid[0x1];
3900 u8 reserved_at_1[0x7];
3901 u8 aso_object_id[0x18];
3902
3903 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3904};
3905
3906struct mlx5_ifc_flow_context_bits {
3907 struct mlx5_ifc_vlan_bits push_vlan;
3908
3909 u8 group_id[0x20];
3910
3911 u8 reserved_at_40[0x8];
3912 u8 flow_tag[0x18];
3913
3914 u8 reserved_at_60[0x10];
3915 u8 action[0x10];
3916
3917 u8 extended_destination[0x1];
3918 u8 uplink_hairpin_en[0x1];
3919 u8 flow_source[0x2];
3920 u8 encrypt_decrypt_type[0x4];
3921 u8 destination_list_size[0x18];
3922
3923 u8 reserved_at_a0[0x8];
3924 u8 flow_counter_list_size[0x18];
3925
3926 u8 packet_reformat_id[0x20];
3927
3928 u8 modify_header_id[0x20];
3929
3930 struct mlx5_ifc_vlan_bits push_vlan_2;
3931
3932 u8 encrypt_decrypt_obj_id[0x20];
3933 u8 reserved_at_140[0xc0];
3934
3935 struct mlx5_ifc_fte_match_param_bits match_value;
3936
3937 struct mlx5_ifc_execute_aso_bits execute_aso[4];
3938
3939 u8 reserved_at_1300[0x500];
3940
3941 union mlx5_ifc_dest_format_flow_counter_list_auto_bits destination[];
3942};
3943
3944enum {
3945 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
3946 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
3947};
3948
3949struct mlx5_ifc_xrc_srqc_bits {
3950 u8 state[0x4];
3951 u8 log_xrc_srq_size[0x4];
3952 u8 reserved_at_8[0x18];
3953
3954 u8 wq_signature[0x1];
3955 u8 cont_srq[0x1];
3956 u8 reserved_at_22[0x1];
3957 u8 rlky[0x1];
3958 u8 basic_cyclic_rcv_wqe[0x1];
3959 u8 log_rq_stride[0x3];
3960 u8 xrcd[0x18];
3961
3962 u8 page_offset[0x6];
3963 u8 reserved_at_46[0x1];
3964 u8 dbr_umem_valid[0x1];
3965 u8 cqn[0x18];
3966
3967 u8 reserved_at_60[0x20];
3968
3969 u8 user_index_equal_xrc_srqn[0x1];
3970 u8 reserved_at_81[0x1];
3971 u8 log_page_size[0x6];
3972 u8 user_index[0x18];
3973
3974 u8 reserved_at_a0[0x20];
3975
3976 u8 reserved_at_c0[0x8];
3977 u8 pd[0x18];
3978
3979 u8 lwm[0x10];
3980 u8 wqe_cnt[0x10];
3981
3982 u8 reserved_at_100[0x40];
3983
3984 u8 db_record_addr_h[0x20];
3985
3986 u8 db_record_addr_l[0x1e];
3987 u8 reserved_at_17e[0x2];
3988
3989 u8 reserved_at_180[0x80];
3990};
3991
3992struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3993 u8 counter_error_queues[0x20];
3994
3995 u8 total_error_queues[0x20];
3996
3997 u8 send_queue_priority_update_flow[0x20];
3998
3999 u8 reserved_at_60[0x20];
4000
4001 u8 nic_receive_steering_discard[0x40];
4002
4003 u8 receive_discard_vport_down[0x40];
4004
4005 u8 transmit_discard_vport_down[0x40];
4006
4007 u8 async_eq_overrun[0x20];
4008
4009 u8 comp_eq_overrun[0x20];
4010
4011 u8 reserved_at_180[0x20];
4012
4013 u8 invalid_command[0x20];
4014
4015 u8 quota_exceeded_command[0x20];
4016
4017 u8 internal_rq_out_of_buffer[0x20];
4018
4019 u8 cq_overrun[0x20];
4020
4021 u8 eth_wqe_too_small[0x20];
4022
4023 u8 reserved_at_220[0xc0];
4024
4025 u8 generated_pkt_steering_fail[0x40];
4026
4027 u8 handled_pkt_steering_fail[0x40];
4028
4029 u8 bar_uar_access[0x20];
4030
4031 u8 odp_local_triggered_page_fault[0x20];
4032
4033 u8 odp_remote_triggered_page_fault[0x20];
4034
4035 u8 reserved_at_3c0[0xc20];
4036};
4037
4038struct mlx5_ifc_traffic_counter_bits {
4039 u8 packets[0x40];
4040
4041 u8 octets[0x40];
4042};
4043
4044struct mlx5_ifc_tisc_bits {
4045 u8 strict_lag_tx_port_affinity[0x1];
4046 u8 tls_en[0x1];
4047 u8 reserved_at_2[0x2];
4048 u8 lag_tx_port_affinity[0x04];
4049
4050 u8 reserved_at_8[0x4];
4051 u8 prio[0x4];
4052 u8 reserved_at_10[0x10];
4053
4054 u8 reserved_at_20[0x100];
4055
4056 u8 reserved_at_120[0x8];
4057 u8 transport_domain[0x18];
4058
4059 u8 reserved_at_140[0x8];
4060 u8 underlay_qpn[0x18];
4061
4062 u8 reserved_at_160[0x8];
4063 u8 pd[0x18];
4064
4065 u8 reserved_at_180[0x380];
4066};
4067
4068enum {
4069 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
4070 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
4071};
4072
4073enum {
4074 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0),
4075 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1),
4076};
4077
4078enum {
4079 MLX5_RX_HASH_FN_NONE = 0x0,
4080 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
4081 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
4082};
4083
4084enum {
4085 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
4086 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
4087};
4088
4089struct mlx5_ifc_tirc_bits {
4090 u8 reserved_at_0[0x20];
4091
4092 u8 disp_type[0x4];
4093 u8 tls_en[0x1];
4094 u8 reserved_at_25[0x1b];
4095
4096 u8 reserved_at_40[0x40];
4097
4098 u8 reserved_at_80[0x4];
4099 u8 lro_timeout_period_usecs[0x10];
4100 u8 packet_merge_mask[0x4];
4101 u8 lro_max_ip_payload_size[0x8];
4102
4103 u8 reserved_at_a0[0x40];
4104
4105 u8 reserved_at_e0[0x8];
4106 u8 inline_rqn[0x18];
4107
4108 u8 rx_hash_symmetric[0x1];
4109 u8 reserved_at_101[0x1];
4110 u8 tunneled_offload_en[0x1];
4111 u8 reserved_at_103[0x5];
4112 u8 indirect_table[0x18];
4113
4114 u8 rx_hash_fn[0x4];
4115 u8 reserved_at_124[0x2];
4116 u8 self_lb_block[0x2];
4117 u8 transport_domain[0x18];
4118
4119 u8 rx_hash_toeplitz_key[10][0x20];
4120
4121 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
4122
4123 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
4124
4125 u8 reserved_at_2c0[0x4c0];
4126};
4127
4128enum {
4129 MLX5_SRQC_STATE_GOOD = 0x0,
4130 MLX5_SRQC_STATE_ERROR = 0x1,
4131};
4132
4133struct mlx5_ifc_srqc_bits {
4134 u8 state[0x4];
4135 u8 log_srq_size[0x4];
4136 u8 reserved_at_8[0x18];
4137
4138 u8 wq_signature[0x1];
4139 u8 cont_srq[0x1];
4140 u8 reserved_at_22[0x1];
4141 u8 rlky[0x1];
4142 u8 reserved_at_24[0x1];
4143 u8 log_rq_stride[0x3];
4144 u8 xrcd[0x18];
4145
4146 u8 page_offset[0x6];
4147 u8 reserved_at_46[0x2];
4148 u8 cqn[0x18];
4149
4150 u8 reserved_at_60[0x20];
4151
4152 u8 reserved_at_80[0x2];
4153 u8 log_page_size[0x6];
4154 u8 reserved_at_88[0x18];
4155
4156 u8 reserved_at_a0[0x20];
4157
4158 u8 reserved_at_c0[0x8];
4159 u8 pd[0x18];
4160
4161 u8 lwm[0x10];
4162 u8 wqe_cnt[0x10];
4163
4164 u8 reserved_at_100[0x40];
4165
4166 u8 dbr_addr[0x40];
4167
4168 u8 reserved_at_180[0x80];
4169};
4170
4171enum {
4172 MLX5_SQC_STATE_RST = 0x0,
4173 MLX5_SQC_STATE_RDY = 0x1,
4174 MLX5_SQC_STATE_ERR = 0x3,
4175};
4176
4177struct mlx5_ifc_sqc_bits {
4178 u8 rlky[0x1];
4179 u8 cd_master[0x1];
4180 u8 fre[0x1];
4181 u8 flush_in_error_en[0x1];
4182 u8 allow_multi_pkt_send_wqe[0x1];
4183 u8 min_wqe_inline_mode[0x3];
4184 u8 state[0x4];
4185 u8 reg_umr[0x1];
4186 u8 allow_swp[0x1];
4187 u8 hairpin[0x1];
4188 u8 non_wire[0x1];
4189 u8 reserved_at_10[0xa];
4190 u8 ts_format[0x2];
4191 u8 reserved_at_1c[0x4];
4192
4193 u8 reserved_at_20[0x8];
4194 u8 user_index[0x18];
4195
4196 u8 reserved_at_40[0x8];
4197 u8 cqn[0x18];
4198
4199 u8 reserved_at_60[0x8];
4200 u8 hairpin_peer_rq[0x18];
4201
4202 u8 reserved_at_80[0x10];
4203 u8 hairpin_peer_vhca[0x10];
4204
4205 u8 reserved_at_a0[0x20];
4206
4207 u8 reserved_at_c0[0x8];
4208 u8 ts_cqe_to_dest_cqn[0x18];
4209
4210 u8 reserved_at_e0[0x10];
4211 u8 packet_pacing_rate_limit_index[0x10];
4212 u8 tis_lst_sz[0x10];
4213 u8 qos_queue_group_id[0x10];
4214
4215 u8 reserved_at_120[0x40];
4216
4217 u8 reserved_at_160[0x8];
4218 u8 tis_num_0[0x18];
4219
4220 struct mlx5_ifc_wq_bits wq;
4221};
4222
4223enum {
4224 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
4225 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
4226 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
4227 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
4228 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
4229 SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5,
4230};
4231
4232enum {
4233 ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0,
4234 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
4235 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
4236 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
4237 ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4,
4238 ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5,
4239};
4240
4241enum {
4242 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4243 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4244 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4245 TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3,
4246};
4247
4248enum {
4249 TSAR_TYPE_CAP_MASK_DWRR = 1 << 0,
4250 TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1,
4251 TSAR_TYPE_CAP_MASK_ETS = 1 << 2,
4252 TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3,
4253};
4254
4255struct mlx5_ifc_tsar_element_bits {
4256 u8 traffic_class[0x4];
4257 u8 reserved_at_4[0x4];
4258 u8 tsar_type[0x8];
4259 u8 reserved_at_10[0x10];
4260};
4261
4262struct mlx5_ifc_vport_element_bits {
4263 u8 reserved_at_0[0x4];
4264 u8 eswitch_owner_vhca_id_valid[0x1];
4265 u8 eswitch_owner_vhca_id[0xb];
4266 u8 vport_number[0x10];
4267};
4268
4269struct mlx5_ifc_vport_tc_element_bits {
4270 u8 traffic_class[0x4];
4271 u8 eswitch_owner_vhca_id_valid[0x1];
4272 u8 eswitch_owner_vhca_id[0xb];
4273 u8 vport_number[0x10];
4274};
4275
4276union mlx5_ifc_element_attributes_bits {
4277 struct mlx5_ifc_tsar_element_bits tsar;
4278 struct mlx5_ifc_vport_element_bits vport;
4279 struct mlx5_ifc_vport_tc_element_bits vport_tc;
4280 u8 reserved_at_0[0x20];
4281};
4282
4283struct mlx5_ifc_scheduling_context_bits {
4284 u8 element_type[0x8];
4285 u8 reserved_at_8[0x18];
4286
4287 union mlx5_ifc_element_attributes_bits element_attributes;
4288
4289 u8 parent_element_id[0x20];
4290
4291 u8 reserved_at_60[0x40];
4292
4293 u8 bw_share[0x20];
4294
4295 u8 max_average_bw[0x20];
4296
4297 u8 max_bw_obj_id[0x20];
4298
4299 u8 reserved_at_100[0x100];
4300};
4301
4302struct mlx5_ifc_rqtc_bits {
4303 u8 reserved_at_0[0xa0];
4304
4305 u8 reserved_at_a0[0x5];
4306 u8 list_q_type[0x3];
4307 u8 reserved_at_a8[0x8];
4308 u8 rqt_max_size[0x10];
4309
4310 u8 rq_vhca_id_format[0x1];
4311 u8 reserved_at_c1[0xf];
4312 u8 rqt_actual_size[0x10];
4313
4314 u8 reserved_at_e0[0x6a0];
4315
4316 union {
4317 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_num_bits, rq_num);
4318 DECLARE_FLEX_ARRAY(struct mlx5_ifc_rq_vhca_bits, rq_vhca);
4319 };
4320};
4321
4322enum {
4323 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
4324 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
4325};
4326
4327enum {
4328 MLX5_RQC_STATE_RST = 0x0,
4329 MLX5_RQC_STATE_RDY = 0x1,
4330 MLX5_RQC_STATE_ERR = 0x3,
4331};
4332
4333enum {
4334 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0,
4335 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1,
4336 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2,
4337};
4338
4339enum {
4340 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0,
4341 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1,
4342 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2,
4343};
4344
4345struct mlx5_ifc_rqc_bits {
4346 u8 rlky[0x1];
4347 u8 delay_drop_en[0x1];
4348 u8 scatter_fcs[0x1];
4349 u8 vsd[0x1];
4350 u8 mem_rq_type[0x4];
4351 u8 state[0x4];
4352 u8 reserved_at_c[0x1];
4353 u8 flush_in_error_en[0x1];
4354 u8 hairpin[0x1];
4355 u8 reserved_at_f[0xb];
4356 u8 ts_format[0x2];
4357 u8 reserved_at_1c[0x4];
4358
4359 u8 reserved_at_20[0x8];
4360 u8 user_index[0x18];
4361
4362 u8 reserved_at_40[0x8];
4363 u8 cqn[0x18];
4364
4365 u8 counter_set_id[0x8];
4366 u8 reserved_at_68[0x18];
4367
4368 u8 reserved_at_80[0x8];
4369 u8 rmpn[0x18];
4370
4371 u8 reserved_at_a0[0x8];
4372 u8 hairpin_peer_sq[0x18];
4373
4374 u8 reserved_at_c0[0x10];
4375 u8 hairpin_peer_vhca[0x10];
4376
4377 u8 reserved_at_e0[0x46];
4378 u8 shampo_no_match_alignment_granularity[0x2];
4379 u8 reserved_at_128[0x6];
4380 u8 shampo_match_criteria_type[0x2];
4381 u8 reservation_timeout[0x10];
4382
4383 u8 reserved_at_140[0x40];
4384
4385 struct mlx5_ifc_wq_bits wq;
4386};
4387
4388enum {
4389 MLX5_RMPC_STATE_RDY = 0x1,
4390 MLX5_RMPC_STATE_ERR = 0x3,
4391};
4392
4393struct mlx5_ifc_rmpc_bits {
4394 u8 reserved_at_0[0x8];
4395 u8 state[0x4];
4396 u8 reserved_at_c[0x14];
4397
4398 u8 basic_cyclic_rcv_wqe[0x1];
4399 u8 reserved_at_21[0x1f];
4400
4401 u8 reserved_at_40[0x140];
4402
4403 struct mlx5_ifc_wq_bits wq;
4404};
4405
4406enum {
4407 VHCA_ID_TYPE_HW = 0,
4408 VHCA_ID_TYPE_SW = 1,
4409};
4410
4411struct mlx5_ifc_nic_vport_context_bits {
4412 u8 reserved_at_0[0x5];
4413 u8 min_wqe_inline_mode[0x3];
4414 u8 reserved_at_8[0x15];
4415 u8 disable_mc_local_lb[0x1];
4416 u8 disable_uc_local_lb[0x1];
4417 u8 roce_en[0x1];
4418
4419 u8 arm_change_event[0x1];
4420 u8 reserved_at_21[0x1a];
4421 u8 event_on_mtu[0x1];
4422 u8 event_on_promisc_change[0x1];
4423 u8 event_on_vlan_change[0x1];
4424 u8 event_on_mc_address_change[0x1];
4425 u8 event_on_uc_address_change[0x1];
4426
4427 u8 vhca_id_type[0x1];
4428 u8 reserved_at_41[0xb];
4429 u8 affiliation_criteria[0x4];
4430 u8 affiliated_vhca_id[0x10];
4431
4432 u8 reserved_at_60[0xa0];
4433
4434 u8 reserved_at_100[0x1];
4435 u8 sd_group[0x3];
4436 u8 reserved_at_104[0x1c];
4437
4438 u8 reserved_at_120[0x10];
4439 u8 mtu[0x10];
4440
4441 u8 system_image_guid[0x40];
4442 u8 port_guid[0x40];
4443 u8 node_guid[0x40];
4444
4445 u8 reserved_at_200[0x140];
4446 u8 qkey_violation_counter[0x10];
4447 u8 reserved_at_350[0x430];
4448
4449 u8 promisc_uc[0x1];
4450 u8 promisc_mc[0x1];
4451 u8 promisc_all[0x1];
4452 u8 reserved_at_783[0x2];
4453 u8 allowed_list_type[0x3];
4454 u8 reserved_at_788[0xc];
4455 u8 allowed_list_size[0xc];
4456
4457 struct mlx5_ifc_mac_address_layout_bits permanent_address;
4458
4459 u8 reserved_at_7e0[0x20];
4460
4461 u8 current_uc_mac_address[][0x40];
4462};
4463
4464enum {
4465 MLX5_MKC_ACCESS_MODE_PA = 0x0,
4466 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
4467 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
4468 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
4469 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4470 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4471 MLX5_MKC_ACCESS_MODE_CROSSING = 0x6,
4472};
4473
4474enum {
4475 MLX5_MKC_PCIE_TPH_NO_STEERING_TAG_INDEX = 0,
4476};
4477
4478struct mlx5_ifc_mkc_bits {
4479 u8 reserved_at_0[0x1];
4480 u8 free[0x1];
4481 u8 reserved_at_2[0x1];
4482 u8 access_mode_4_2[0x3];
4483 u8 reserved_at_6[0x7];
4484 u8 relaxed_ordering_write[0x1];
4485 u8 reserved_at_e[0x1];
4486 u8 small_fence_on_rdma_read_response[0x1];
4487 u8 umr_en[0x1];
4488 u8 a[0x1];
4489 u8 rw[0x1];
4490 u8 rr[0x1];
4491 u8 lw[0x1];
4492 u8 lr[0x1];
4493 u8 access_mode_1_0[0x2];
4494 u8 reserved_at_18[0x2];
4495 u8 ma_translation_mode[0x2];
4496 u8 reserved_at_1c[0x4];
4497
4498 u8 qpn[0x18];
4499 u8 mkey_7_0[0x8];
4500
4501 u8 reserved_at_40[0x20];
4502
4503 u8 length64[0x1];
4504 u8 bsf_en[0x1];
4505 u8 sync_umr[0x1];
4506 u8 reserved_at_63[0x2];
4507 u8 expected_sigerr_count[0x1];
4508 u8 reserved_at_66[0x1];
4509 u8 en_rinval[0x1];
4510 u8 pd[0x18];
4511
4512 u8 start_addr[0x40];
4513
4514 u8 len[0x40];
4515
4516 u8 bsf_octword_size[0x20];
4517
4518 u8 reserved_at_120[0x60];
4519
4520 u8 crossing_target_vhca_id[0x10];
4521 u8 reserved_at_190[0x10];
4522
4523 u8 translations_octword_size[0x20];
4524
4525 u8 reserved_at_1c0[0x19];
4526 u8 relaxed_ordering_read[0x1];
4527 u8 log_page_size[0x6];
4528
4529 u8 reserved_at_1e0[0x5];
4530 u8 pcie_tph_en[0x1];
4531 u8 pcie_tph_ph[0x2];
4532 u8 pcie_tph_steering_tag_index[0x8];
4533 u8 reserved_at_1f0[0x10];
4534};
4535
4536struct mlx5_ifc_pkey_bits {
4537 u8 reserved_at_0[0x10];
4538 u8 pkey[0x10];
4539};
4540
4541struct mlx5_ifc_array128_auto_bits {
4542 u8 array128_auto[16][0x8];
4543};
4544
4545struct mlx5_ifc_hca_vport_context_bits {
4546 u8 field_select[0x20];
4547
4548 u8 reserved_at_20[0xe0];
4549
4550 u8 sm_virt_aware[0x1];
4551 u8 has_smi[0x1];
4552 u8 has_raw[0x1];
4553 u8 grh_required[0x1];
4554 u8 reserved_at_104[0x4];
4555 u8 num_port_plane[0x8];
4556 u8 port_physical_state[0x4];
4557 u8 vport_state_policy[0x4];
4558 u8 port_state[0x4];
4559 u8 vport_state[0x4];
4560
4561 u8 reserved_at_120[0x20];
4562
4563 u8 system_image_guid[0x40];
4564
4565 u8 port_guid[0x40];
4566
4567 u8 node_guid[0x40];
4568
4569 u8 cap_mask1[0x20];
4570
4571 u8 cap_mask1_field_select[0x20];
4572
4573 u8 cap_mask2[0x20];
4574
4575 u8 cap_mask2_field_select[0x20];
4576
4577 u8 reserved_at_280[0x80];
4578
4579 u8 lid[0x10];
4580 u8 reserved_at_310[0x4];
4581 u8 init_type_reply[0x4];
4582 u8 lmc[0x3];
4583 u8 subnet_timeout[0x5];
4584
4585 u8 sm_lid[0x10];
4586 u8 sm_sl[0x4];
4587 u8 reserved_at_334[0xc];
4588
4589 u8 qkey_violation_counter[0x10];
4590 u8 pkey_violation_counter[0x10];
4591
4592 u8 reserved_at_360[0xca0];
4593};
4594
4595struct mlx5_ifc_esw_vport_context_bits {
4596 u8 fdb_to_vport_reg_c[0x1];
4597 u8 reserved_at_1[0x2];
4598 u8 vport_svlan_strip[0x1];
4599 u8 vport_cvlan_strip[0x1];
4600 u8 vport_svlan_insert[0x1];
4601 u8 vport_cvlan_insert[0x2];
4602 u8 fdb_to_vport_reg_c_id[0x8];
4603 u8 reserved_at_10[0x10];
4604
4605 u8 reserved_at_20[0x20];
4606
4607 u8 svlan_cfi[0x1];
4608 u8 svlan_pcp[0x3];
4609 u8 svlan_id[0xc];
4610 u8 cvlan_cfi[0x1];
4611 u8 cvlan_pcp[0x3];
4612 u8 cvlan_id[0xc];
4613
4614 u8 reserved_at_60[0x720];
4615
4616 u8 sw_steering_vport_icm_address_rx[0x40];
4617
4618 u8 sw_steering_vport_icm_address_tx[0x40];
4619};
4620
4621enum {
4622 MLX5_EQC_STATUS_OK = 0x0,
4623 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
4624};
4625
4626enum {
4627 MLX5_EQC_ST_ARMED = 0x9,
4628 MLX5_EQC_ST_FIRED = 0xa,
4629};
4630
4631struct mlx5_ifc_eqc_bits {
4632 u8 status[0x4];
4633 u8 reserved_at_4[0x9];
4634 u8 ec[0x1];
4635 u8 oi[0x1];
4636 u8 reserved_at_f[0x5];
4637 u8 st[0x4];
4638 u8 reserved_at_18[0x8];
4639
4640 u8 reserved_at_20[0x20];
4641
4642 u8 reserved_at_40[0x14];
4643 u8 page_offset[0x6];
4644 u8 reserved_at_5a[0x6];
4645
4646 u8 reserved_at_60[0x3];
4647 u8 log_eq_size[0x5];
4648 u8 uar_page[0x18];
4649
4650 u8 reserved_at_80[0x20];
4651
4652 u8 reserved_at_a0[0x14];
4653 u8 intr[0xc];
4654
4655 u8 reserved_at_c0[0x3];
4656 u8 log_page_size[0x5];
4657 u8 reserved_at_c8[0x18];
4658
4659 u8 reserved_at_e0[0x60];
4660
4661 u8 reserved_at_140[0x8];
4662 u8 consumer_counter[0x18];
4663
4664 u8 reserved_at_160[0x8];
4665 u8 producer_counter[0x18];
4666
4667 u8 reserved_at_180[0x80];
4668};
4669
4670enum {
4671 MLX5_DCTC_STATE_ACTIVE = 0x0,
4672 MLX5_DCTC_STATE_DRAINING = 0x1,
4673 MLX5_DCTC_STATE_DRAINED = 0x2,
4674};
4675
4676enum {
4677 MLX5_DCTC_CS_RES_DISABLE = 0x0,
4678 MLX5_DCTC_CS_RES_NA = 0x1,
4679 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
4680};
4681
4682enum {
4683 MLX5_DCTC_MTU_256_BYTES = 0x1,
4684 MLX5_DCTC_MTU_512_BYTES = 0x2,
4685 MLX5_DCTC_MTU_1K_BYTES = 0x3,
4686 MLX5_DCTC_MTU_2K_BYTES = 0x4,
4687 MLX5_DCTC_MTU_4K_BYTES = 0x5,
4688};
4689
4690struct mlx5_ifc_dctc_bits {
4691 u8 reserved_at_0[0x4];
4692 u8 state[0x4];
4693 u8 reserved_at_8[0x18];
4694
4695 u8 reserved_at_20[0x7];
4696 u8 dp_ordering_force[0x1];
4697 u8 user_index[0x18];
4698
4699 u8 reserved_at_40[0x8];
4700 u8 cqn[0x18];
4701
4702 u8 counter_set_id[0x8];
4703 u8 atomic_mode[0x4];
4704 u8 rre[0x1];
4705 u8 rwe[0x1];
4706 u8 rae[0x1];
4707 u8 atomic_like_write_en[0x1];
4708 u8 latency_sensitive[0x1];
4709 u8 rlky[0x1];
4710 u8 free_ar[0x1];
4711 u8 reserved_at_73[0x1];
4712 u8 dp_ordering_1[0x1];
4713 u8 reserved_at_75[0xb];
4714
4715 u8 reserved_at_80[0x8];
4716 u8 cs_res[0x8];
4717 u8 reserved_at_90[0x3];
4718 u8 min_rnr_nak[0x5];
4719 u8 reserved_at_98[0x8];
4720
4721 u8 reserved_at_a0[0x8];
4722 u8 srqn_xrqn[0x18];
4723
4724 u8 reserved_at_c0[0x8];
4725 u8 pd[0x18];
4726
4727 u8 tclass[0x8];
4728 u8 reserved_at_e8[0x4];
4729 u8 flow_label[0x14];
4730
4731 u8 dc_access_key[0x40];
4732
4733 u8 reserved_at_140[0x5];
4734 u8 mtu[0x3];
4735 u8 port[0x8];
4736 u8 pkey_index[0x10];
4737
4738 u8 reserved_at_160[0x8];
4739 u8 my_addr_index[0x8];
4740 u8 reserved_at_170[0x8];
4741 u8 hop_limit[0x8];
4742
4743 u8 dc_access_key_violation_count[0x20];
4744
4745 u8 reserved_at_1a0[0x14];
4746 u8 dei_cfi[0x1];
4747 u8 eth_prio[0x3];
4748 u8 ecn[0x2];
4749 u8 dscp[0x6];
4750
4751 u8 reserved_at_1c0[0x20];
4752 u8 ece[0x20];
4753};
4754
4755enum {
4756 MLX5_CQC_STATUS_OK = 0x0,
4757 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
4758 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
4759};
4760
4761enum {
4762 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
4763 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
4764};
4765
4766enum {
4767 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
4768 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
4769 MLX5_CQC_ST_FIRED = 0xa,
4770};
4771
4772enum mlx5_cq_period_mode {
4773 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4774 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4775 MLX5_CQ_PERIOD_NUM_MODES,
4776};
4777
4778struct mlx5_ifc_cqc_bits {
4779 u8 status[0x4];
4780 u8 reserved_at_4[0x2];
4781 u8 dbr_umem_valid[0x1];
4782 u8 apu_cq[0x1];
4783 u8 cqe_sz[0x3];
4784 u8 cc[0x1];
4785 u8 reserved_at_c[0x1];
4786 u8 scqe_break_moderation_en[0x1];
4787 u8 oi[0x1];
4788 u8 cq_period_mode[0x2];
4789 u8 cqe_comp_en[0x1];
4790 u8 mini_cqe_res_format[0x2];
4791 u8 st[0x4];
4792 u8 reserved_at_18[0x6];
4793 u8 cqe_compression_layout[0x2];
4794
4795 u8 reserved_at_20[0x20];
4796
4797 u8 reserved_at_40[0x14];
4798 u8 page_offset[0x6];
4799 u8 reserved_at_5a[0x6];
4800
4801 u8 reserved_at_60[0x3];
4802 u8 log_cq_size[0x5];
4803 u8 uar_page[0x18];
4804
4805 u8 reserved_at_80[0x4];
4806 u8 cq_period[0xc];
4807 u8 cq_max_count[0x10];
4808
4809 u8 c_eqn_or_apu_element[0x20];
4810
4811 u8 reserved_at_c0[0x3];
4812 u8 log_page_size[0x5];
4813 u8 reserved_at_c8[0x18];
4814
4815 u8 reserved_at_e0[0x20];
4816
4817 u8 reserved_at_100[0x8];
4818 u8 last_notified_index[0x18];
4819
4820 u8 reserved_at_120[0x8];
4821 u8 last_solicit_index[0x18];
4822
4823 u8 reserved_at_140[0x8];
4824 u8 consumer_counter[0x18];
4825
4826 u8 reserved_at_160[0x8];
4827 u8 producer_counter[0x18];
4828
4829 u8 reserved_at_180[0x40];
4830
4831 u8 dbr_addr[0x40];
4832};
4833
4834union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4835 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4836 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4837 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4838 struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4839 u8 reserved_at_0[0x800];
4840};
4841
4842struct mlx5_ifc_query_adapter_param_block_bits {
4843 u8 reserved_at_0[0xc0];
4844
4845 u8 reserved_at_c0[0x8];
4846 u8 ieee_vendor_id[0x18];
4847
4848 u8 reserved_at_e0[0x10];
4849 u8 vsd_vendor_id[0x10];
4850
4851 u8 vsd[208][0x8];
4852
4853 u8 vsd_contd_psid[16][0x8];
4854};
4855
4856enum {
4857 MLX5_XRQC_STATE_GOOD = 0x0,
4858 MLX5_XRQC_STATE_ERROR = 0x1,
4859};
4860
4861enum {
4862 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4863 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
4864};
4865
4866enum {
4867 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4868};
4869
4870struct mlx5_ifc_tag_matching_topology_context_bits {
4871 u8 log_matching_list_sz[0x4];
4872 u8 reserved_at_4[0xc];
4873 u8 append_next_index[0x10];
4874
4875 u8 sw_phase_cnt[0x10];
4876 u8 hw_phase_cnt[0x10];
4877
4878 u8 reserved_at_40[0x40];
4879};
4880
4881struct mlx5_ifc_xrqc_bits {
4882 u8 state[0x4];
4883 u8 rlkey[0x1];
4884 u8 reserved_at_5[0xf];
4885 u8 topology[0x4];
4886 u8 reserved_at_18[0x4];
4887 u8 offload[0x4];
4888
4889 u8 reserved_at_20[0x8];
4890 u8 user_index[0x18];
4891
4892 u8 reserved_at_40[0x8];
4893 u8 cqn[0x18];
4894
4895 u8 reserved_at_60[0xa0];
4896
4897 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4898
4899 u8 reserved_at_180[0x280];
4900
4901 struct mlx5_ifc_wq_bits wq;
4902};
4903
4904union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4905 struct mlx5_ifc_modify_field_select_bits modify_field_select;
4906 struct mlx5_ifc_resize_field_select_bits resize_field_select;
4907 u8 reserved_at_0[0x20];
4908};
4909
4910union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4911 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4912 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4913 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4914 u8 reserved_at_0[0x20];
4915};
4916
4917struct mlx5_ifc_rs_histogram_cntrs_bits {
4918 u8 hist[16][0x40];
4919 u8 reserved_at_400[0x2c0];
4920};
4921
4922union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4923 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4924 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4925 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4926 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4927 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4928 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4929 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4930 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4931 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4932 struct mlx5_ifc_ib_ext_port_cntrs_grp_data_layout_bits ib_ext_port_cntrs_grp_data_layout;
4933 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4934 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4935 struct mlx5_ifc_phys_layer_recovery_cntrs_bits phys_layer_recovery_cntrs;
4936 struct mlx5_ifc_rs_histogram_cntrs_bits rs_histogram_cntrs;
4937 u8 reserved_at_0[0x7c0];
4938};
4939
4940union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4941 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4942 u8 reserved_at_0[0x7c0];
4943};
4944
4945union mlx5_ifc_event_auto_bits {
4946 struct mlx5_ifc_comp_event_bits comp_event;
4947 struct mlx5_ifc_dct_events_bits dct_events;
4948 struct mlx5_ifc_qp_events_bits qp_events;
4949 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4950 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4951 struct mlx5_ifc_cq_error_bits cq_error;
4952 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4953 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4954 struct mlx5_ifc_gpio_event_bits gpio_event;
4955 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4956 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4957 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4958 u8 reserved_at_0[0xe0];
4959};
4960
4961struct mlx5_ifc_health_buffer_bits {
4962 u8 reserved_at_0[0x100];
4963
4964 u8 assert_existptr[0x20];
4965
4966 u8 assert_callra[0x20];
4967
4968 u8 reserved_at_140[0x20];
4969
4970 u8 time[0x20];
4971
4972 u8 fw_version[0x20];
4973
4974 u8 hw_id[0x20];
4975
4976 u8 rfr[0x1];
4977 u8 reserved_at_1c1[0x3];
4978 u8 valid[0x1];
4979 u8 severity[0x3];
4980 u8 reserved_at_1c8[0x18];
4981
4982 u8 irisc_index[0x8];
4983 u8 synd[0x8];
4984 u8 ext_synd[0x10];
4985};
4986
4987struct mlx5_ifc_register_loopback_control_bits {
4988 u8 no_lb[0x1];
4989 u8 reserved_at_1[0x7];
4990 u8 port[0x8];
4991 u8 reserved_at_10[0x10];
4992
4993 u8 reserved_at_20[0x60];
4994};
4995
4996enum {
4997 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4998 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4999};
5000
5001struct mlx5_ifc_teardown_hca_out_bits {
5002 u8 status[0x8];
5003 u8 reserved_at_8[0x18];
5004
5005 u8 syndrome[0x20];
5006
5007 u8 reserved_at_40[0x3f];
5008
5009 u8 state[0x1];
5010};
5011
5012enum {
5013 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
5014 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
5015 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
5016};
5017
5018struct mlx5_ifc_teardown_hca_in_bits {
5019 u8 opcode[0x10];
5020 u8 reserved_at_10[0x10];
5021
5022 u8 reserved_at_20[0x10];
5023 u8 op_mod[0x10];
5024
5025 u8 reserved_at_40[0x10];
5026 u8 profile[0x10];
5027
5028 u8 reserved_at_60[0x20];
5029};
5030
5031struct mlx5_ifc_sqerr2rts_qp_out_bits {
5032 u8 status[0x8];
5033 u8 reserved_at_8[0x18];
5034
5035 u8 syndrome[0x20];
5036
5037 u8 reserved_at_40[0x40];
5038};
5039
5040struct mlx5_ifc_sqerr2rts_qp_in_bits {
5041 u8 opcode[0x10];
5042 u8 uid[0x10];
5043
5044 u8 reserved_at_20[0x10];
5045 u8 op_mod[0x10];
5046
5047 u8 reserved_at_40[0x8];
5048 u8 qpn[0x18];
5049
5050 u8 reserved_at_60[0x20];
5051
5052 u8 opt_param_mask[0x20];
5053
5054 u8 reserved_at_a0[0x20];
5055
5056 struct mlx5_ifc_qpc_bits qpc;
5057
5058 u8 reserved_at_800[0x80];
5059};
5060
5061struct mlx5_ifc_sqd2rts_qp_out_bits {
5062 u8 status[0x8];
5063 u8 reserved_at_8[0x18];
5064
5065 u8 syndrome[0x20];
5066
5067 u8 reserved_at_40[0x40];
5068};
5069
5070struct mlx5_ifc_sqd2rts_qp_in_bits {
5071 u8 opcode[0x10];
5072 u8 uid[0x10];
5073
5074 u8 reserved_at_20[0x10];
5075 u8 op_mod[0x10];
5076
5077 u8 reserved_at_40[0x8];
5078 u8 qpn[0x18];
5079
5080 u8 reserved_at_60[0x20];
5081
5082 u8 opt_param_mask[0x20];
5083
5084 u8 reserved_at_a0[0x20];
5085
5086 struct mlx5_ifc_qpc_bits qpc;
5087
5088 u8 reserved_at_800[0x80];
5089};
5090
5091struct mlx5_ifc_set_roce_address_out_bits {
5092 u8 status[0x8];
5093 u8 reserved_at_8[0x18];
5094
5095 u8 syndrome[0x20];
5096
5097 u8 reserved_at_40[0x40];
5098};
5099
5100struct mlx5_ifc_set_roce_address_in_bits {
5101 u8 opcode[0x10];
5102 u8 reserved_at_10[0x10];
5103
5104 u8 reserved_at_20[0x10];
5105 u8 op_mod[0x10];
5106
5107 u8 roce_address_index[0x10];
5108 u8 reserved_at_50[0xc];
5109 u8 vhca_port_num[0x4];
5110
5111 u8 reserved_at_60[0x20];
5112
5113 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5114};
5115
5116struct mlx5_ifc_set_mad_demux_out_bits {
5117 u8 status[0x8];
5118 u8 reserved_at_8[0x18];
5119
5120 u8 syndrome[0x20];
5121
5122 u8 reserved_at_40[0x40];
5123};
5124
5125enum {
5126 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
5127 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
5128};
5129
5130struct mlx5_ifc_set_mad_demux_in_bits {
5131 u8 opcode[0x10];
5132 u8 reserved_at_10[0x10];
5133
5134 u8 reserved_at_20[0x10];
5135 u8 op_mod[0x10];
5136
5137 u8 reserved_at_40[0x20];
5138
5139 u8 reserved_at_60[0x6];
5140 u8 demux_mode[0x2];
5141 u8 reserved_at_68[0x18];
5142};
5143
5144struct mlx5_ifc_set_l2_table_entry_out_bits {
5145 u8 status[0x8];
5146 u8 reserved_at_8[0x18];
5147
5148 u8 syndrome[0x20];
5149
5150 u8 reserved_at_40[0x40];
5151};
5152
5153struct mlx5_ifc_set_l2_table_entry_in_bits {
5154 u8 opcode[0x10];
5155 u8 reserved_at_10[0x10];
5156
5157 u8 reserved_at_20[0x10];
5158 u8 op_mod[0x10];
5159
5160 u8 reserved_at_40[0x60];
5161
5162 u8 reserved_at_a0[0x8];
5163 u8 table_index[0x18];
5164
5165 u8 reserved_at_c0[0x20];
5166
5167 u8 reserved_at_e0[0x10];
5168 u8 silent_mode_valid[0x1];
5169 u8 silent_mode[0x1];
5170 u8 reserved_at_f2[0x1];
5171 u8 vlan_valid[0x1];
5172 u8 vlan[0xc];
5173
5174 struct mlx5_ifc_mac_address_layout_bits mac_address;
5175
5176 u8 reserved_at_140[0xc0];
5177};
5178
5179struct mlx5_ifc_set_issi_out_bits {
5180 u8 status[0x8];
5181 u8 reserved_at_8[0x18];
5182
5183 u8 syndrome[0x20];
5184
5185 u8 reserved_at_40[0x40];
5186};
5187
5188struct mlx5_ifc_set_issi_in_bits {
5189 u8 opcode[0x10];
5190 u8 reserved_at_10[0x10];
5191
5192 u8 reserved_at_20[0x10];
5193 u8 op_mod[0x10];
5194
5195 u8 reserved_at_40[0x10];
5196 u8 current_issi[0x10];
5197
5198 u8 reserved_at_60[0x20];
5199};
5200
5201struct mlx5_ifc_set_hca_cap_out_bits {
5202 u8 status[0x8];
5203 u8 reserved_at_8[0x18];
5204
5205 u8 syndrome[0x20];
5206
5207 u8 reserved_at_40[0x40];
5208};
5209
5210struct mlx5_ifc_set_hca_cap_in_bits {
5211 u8 opcode[0x10];
5212 u8 reserved_at_10[0x10];
5213
5214 u8 reserved_at_20[0x10];
5215 u8 op_mod[0x10];
5216
5217 u8 other_function[0x1];
5218 u8 ec_vf_function[0x1];
5219 u8 reserved_at_42[0x1];
5220 u8 function_id_type[0x1];
5221 u8 reserved_at_44[0xc];
5222 u8 function_id[0x10];
5223
5224 u8 reserved_at_60[0x20];
5225
5226 union mlx5_ifc_hca_cap_union_bits capability;
5227};
5228
5229enum {
5230 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
5231 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
5232 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
5233 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3,
5234 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4
5235};
5236
5237struct mlx5_ifc_set_fte_out_bits {
5238 u8 status[0x8];
5239 u8 reserved_at_8[0x18];
5240
5241 u8 syndrome[0x20];
5242
5243 u8 reserved_at_40[0x40];
5244};
5245
5246struct mlx5_ifc_set_fte_in_bits {
5247 u8 opcode[0x10];
5248 u8 reserved_at_10[0x10];
5249
5250 u8 reserved_at_20[0x10];
5251 u8 op_mod[0x10];
5252
5253 u8 other_vport[0x1];
5254 u8 other_eswitch[0x1];
5255 u8 reserved_at_42[0xe];
5256 u8 vport_number[0x10];
5257
5258 u8 reserved_at_60[0x20];
5259
5260 u8 table_type[0x8];
5261 u8 reserved_at_88[0x8];
5262 u8 eswitch_owner_vhca_id[0x10];
5263
5264 u8 reserved_at_a0[0x8];
5265 u8 table_id[0x18];
5266
5267 u8 ignore_flow_level[0x1];
5268 u8 reserved_at_c1[0x17];
5269 u8 modify_enable_mask[0x8];
5270
5271 u8 reserved_at_e0[0x20];
5272
5273 u8 flow_index[0x20];
5274
5275 u8 reserved_at_120[0xe0];
5276
5277 struct mlx5_ifc_flow_context_bits flow_context;
5278};
5279
5280struct mlx5_ifc_dest_format_bits {
5281 u8 destination_type[0x8];
5282 u8 destination_id[0x18];
5283
5284 u8 destination_eswitch_owner_vhca_id_valid[0x1];
5285 u8 packet_reformat[0x1];
5286 u8 reserved_at_22[0xe];
5287 u8 destination_eswitch_owner_vhca_id[0x10];
5288};
5289
5290struct mlx5_ifc_rts2rts_qp_out_bits {
5291 u8 status[0x8];
5292 u8 reserved_at_8[0x18];
5293
5294 u8 syndrome[0x20];
5295
5296 u8 reserved_at_40[0x20];
5297 u8 ece[0x20];
5298};
5299
5300struct mlx5_ifc_rts2rts_qp_in_bits {
5301 u8 opcode[0x10];
5302 u8 uid[0x10];
5303
5304 u8 reserved_at_20[0x10];
5305 u8 op_mod[0x10];
5306
5307 u8 reserved_at_40[0x8];
5308 u8 qpn[0x18];
5309
5310 u8 reserved_at_60[0x20];
5311
5312 u8 opt_param_mask[0x20];
5313
5314 u8 ece[0x20];
5315
5316 struct mlx5_ifc_qpc_bits qpc;
5317
5318 u8 reserved_at_800[0x80];
5319};
5320
5321struct mlx5_ifc_rtr2rts_qp_out_bits {
5322 u8 status[0x8];
5323 u8 reserved_at_8[0x18];
5324
5325 u8 syndrome[0x20];
5326
5327 u8 reserved_at_40[0x20];
5328 u8 ece[0x20];
5329};
5330
5331struct mlx5_ifc_rtr2rts_qp_in_bits {
5332 u8 opcode[0x10];
5333 u8 uid[0x10];
5334
5335 u8 reserved_at_20[0x10];
5336 u8 op_mod[0x10];
5337
5338 u8 reserved_at_40[0x8];
5339 u8 qpn[0x18];
5340
5341 u8 reserved_at_60[0x20];
5342
5343 u8 opt_param_mask[0x20];
5344
5345 u8 ece[0x20];
5346
5347 struct mlx5_ifc_qpc_bits qpc;
5348
5349 u8 reserved_at_800[0x80];
5350};
5351
5352struct mlx5_ifc_rst2init_qp_out_bits {
5353 u8 status[0x8];
5354 u8 reserved_at_8[0x18];
5355
5356 u8 syndrome[0x20];
5357
5358 u8 reserved_at_40[0x20];
5359 u8 ece[0x20];
5360};
5361
5362struct mlx5_ifc_rst2init_qp_in_bits {
5363 u8 opcode[0x10];
5364 u8 uid[0x10];
5365
5366 u8 reserved_at_20[0x10];
5367 u8 op_mod[0x10];
5368
5369 u8 reserved_at_40[0x8];
5370 u8 qpn[0x18];
5371
5372 u8 reserved_at_60[0x20];
5373
5374 u8 opt_param_mask[0x20];
5375
5376 u8 ece[0x20];
5377
5378 struct mlx5_ifc_qpc_bits qpc;
5379
5380 u8 reserved_at_800[0x80];
5381};
5382
5383struct mlx5_ifc_query_xrq_out_bits {
5384 u8 status[0x8];
5385 u8 reserved_at_8[0x18];
5386
5387 u8 syndrome[0x20];
5388
5389 u8 reserved_at_40[0x40];
5390
5391 struct mlx5_ifc_xrqc_bits xrq_context;
5392};
5393
5394struct mlx5_ifc_query_xrq_in_bits {
5395 u8 opcode[0x10];
5396 u8 reserved_at_10[0x10];
5397
5398 u8 reserved_at_20[0x10];
5399 u8 op_mod[0x10];
5400
5401 u8 reserved_at_40[0x8];
5402 u8 xrqn[0x18];
5403
5404 u8 reserved_at_60[0x20];
5405};
5406
5407struct mlx5_ifc_query_xrc_srq_out_bits {
5408 u8 status[0x8];
5409 u8 reserved_at_8[0x18];
5410
5411 u8 syndrome[0x20];
5412
5413 u8 reserved_at_40[0x40];
5414
5415 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5416
5417 u8 reserved_at_280[0x600];
5418
5419 u8 pas[][0x40];
5420};
5421
5422struct mlx5_ifc_query_xrc_srq_in_bits {
5423 u8 opcode[0x10];
5424 u8 reserved_at_10[0x10];
5425
5426 u8 reserved_at_20[0x10];
5427 u8 op_mod[0x10];
5428
5429 u8 reserved_at_40[0x8];
5430 u8 xrc_srqn[0x18];
5431
5432 u8 reserved_at_60[0x20];
5433};
5434
5435enum {
5436 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
5437 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
5438};
5439
5440struct mlx5_ifc_query_vport_state_out_bits {
5441 u8 status[0x8];
5442 u8 reserved_at_8[0x18];
5443
5444 u8 syndrome[0x20];
5445
5446 u8 reserved_at_40[0x20];
5447
5448 u8 reserved_at_60[0x18];
5449 u8 admin_state[0x4];
5450 u8 state[0x4];
5451};
5452
5453struct mlx5_ifc_array1024_auto_bits {
5454 u8 array1024_auto[32][0x20];
5455};
5456
5457struct mlx5_ifc_query_vuid_in_bits {
5458 u8 opcode[0x10];
5459 u8 uid[0x10];
5460
5461 u8 reserved_at_20[0x40];
5462
5463 u8 query_vfs_vuid[0x1];
5464 u8 data_direct[0x1];
5465 u8 reserved_at_62[0xe];
5466 u8 vhca_id[0x10];
5467};
5468
5469struct mlx5_ifc_query_vuid_out_bits {
5470 u8 status[0x8];
5471 u8 reserved_at_8[0x18];
5472
5473 u8 syndrome[0x20];
5474
5475 u8 reserved_at_40[0x1a0];
5476
5477 u8 reserved_at_1e0[0x10];
5478 u8 num_of_entries[0x10];
5479
5480 struct mlx5_ifc_array1024_auto_bits vuid[];
5481};
5482
5483enum {
5484 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
5485 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
5486 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2,
5487};
5488
5489struct mlx5_ifc_arm_monitor_counter_in_bits {
5490 u8 opcode[0x10];
5491 u8 uid[0x10];
5492
5493 u8 reserved_at_20[0x10];
5494 u8 op_mod[0x10];
5495
5496 u8 reserved_at_40[0x20];
5497
5498 u8 reserved_at_60[0x20];
5499};
5500
5501struct mlx5_ifc_arm_monitor_counter_out_bits {
5502 u8 status[0x8];
5503 u8 reserved_at_8[0x18];
5504
5505 u8 syndrome[0x20];
5506
5507 u8 reserved_at_40[0x40];
5508};
5509
5510enum {
5511 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
5512 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5513};
5514
5515enum mlx5_monitor_counter_ppcnt {
5516 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
5517 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
5518 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
5519 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5520 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
5521 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
5522};
5523
5524enum {
5525 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
5526};
5527
5528struct mlx5_ifc_monitor_counter_output_bits {
5529 u8 reserved_at_0[0x4];
5530 u8 type[0x4];
5531 u8 reserved_at_8[0x8];
5532 u8 counter[0x10];
5533
5534 u8 counter_group_id[0x20];
5535};
5536
5537#define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5538#define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
5539#define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5540 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5541
5542struct mlx5_ifc_set_monitor_counter_in_bits {
5543 u8 opcode[0x10];
5544 u8 uid[0x10];
5545
5546 u8 reserved_at_20[0x10];
5547 u8 op_mod[0x10];
5548
5549 u8 reserved_at_40[0x10];
5550 u8 num_of_counters[0x10];
5551
5552 u8 reserved_at_60[0x20];
5553
5554 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5555};
5556
5557struct mlx5_ifc_set_monitor_counter_out_bits {
5558 u8 status[0x8];
5559 u8 reserved_at_8[0x18];
5560
5561 u8 syndrome[0x20];
5562
5563 u8 reserved_at_40[0x40];
5564};
5565
5566struct mlx5_ifc_query_vport_state_in_bits {
5567 u8 opcode[0x10];
5568 u8 reserved_at_10[0x10];
5569
5570 u8 reserved_at_20[0x10];
5571 u8 op_mod[0x10];
5572
5573 u8 other_vport[0x1];
5574 u8 reserved_at_41[0xf];
5575 u8 vport_number[0x10];
5576
5577 u8 reserved_at_60[0x20];
5578};
5579
5580struct mlx5_ifc_query_vnic_env_out_bits {
5581 u8 status[0x8];
5582 u8 reserved_at_8[0x18];
5583
5584 u8 syndrome[0x20];
5585
5586 u8 reserved_at_40[0x40];
5587
5588 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5589};
5590
5591enum {
5592 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
5593};
5594
5595struct mlx5_ifc_query_vnic_env_in_bits {
5596 u8 opcode[0x10];
5597 u8 reserved_at_10[0x10];
5598
5599 u8 reserved_at_20[0x10];
5600 u8 op_mod[0x10];
5601
5602 u8 other_vport[0x1];
5603 u8 reserved_at_41[0xf];
5604 u8 vport_number[0x10];
5605
5606 u8 reserved_at_60[0x20];
5607};
5608
5609struct mlx5_ifc_query_vport_counter_out_bits {
5610 u8 status[0x8];
5611 u8 reserved_at_8[0x18];
5612
5613 u8 syndrome[0x20];
5614
5615 u8 reserved_at_40[0x40];
5616
5617 struct mlx5_ifc_traffic_counter_bits received_errors;
5618
5619 struct mlx5_ifc_traffic_counter_bits transmit_errors;
5620
5621 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5622
5623 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5624
5625 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5626
5627 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5628
5629 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5630
5631 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5632
5633 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5634
5635 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5636
5637 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5638
5639 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5640
5641 struct mlx5_ifc_traffic_counter_bits local_loopback;
5642
5643 u8 reserved_at_700[0x980];
5644};
5645
5646enum {
5647 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
5648};
5649
5650struct mlx5_ifc_query_vport_counter_in_bits {
5651 u8 opcode[0x10];
5652 u8 reserved_at_10[0x10];
5653
5654 u8 reserved_at_20[0x10];
5655 u8 op_mod[0x10];
5656
5657 u8 other_vport[0x1];
5658 u8 reserved_at_41[0xb];
5659 u8 port_num[0x4];
5660 u8 vport_number[0x10];
5661
5662 u8 reserved_at_60[0x60];
5663
5664 u8 clear[0x1];
5665 u8 reserved_at_c1[0x1f];
5666
5667 u8 reserved_at_e0[0x20];
5668};
5669
5670struct mlx5_ifc_query_tis_out_bits {
5671 u8 status[0x8];
5672 u8 reserved_at_8[0x18];
5673
5674 u8 syndrome[0x20];
5675
5676 u8 reserved_at_40[0x40];
5677
5678 struct mlx5_ifc_tisc_bits tis_context;
5679};
5680
5681struct mlx5_ifc_query_tis_in_bits {
5682 u8 opcode[0x10];
5683 u8 reserved_at_10[0x10];
5684
5685 u8 reserved_at_20[0x10];
5686 u8 op_mod[0x10];
5687
5688 u8 reserved_at_40[0x8];
5689 u8 tisn[0x18];
5690
5691 u8 reserved_at_60[0x20];
5692};
5693
5694struct mlx5_ifc_query_tir_out_bits {
5695 u8 status[0x8];
5696 u8 reserved_at_8[0x18];
5697
5698 u8 syndrome[0x20];
5699
5700 u8 reserved_at_40[0xc0];
5701
5702 struct mlx5_ifc_tirc_bits tir_context;
5703};
5704
5705struct mlx5_ifc_query_tir_in_bits {
5706 u8 opcode[0x10];
5707 u8 reserved_at_10[0x10];
5708
5709 u8 reserved_at_20[0x10];
5710 u8 op_mod[0x10];
5711
5712 u8 reserved_at_40[0x8];
5713 u8 tirn[0x18];
5714
5715 u8 reserved_at_60[0x20];
5716};
5717
5718struct mlx5_ifc_query_srq_out_bits {
5719 u8 status[0x8];
5720 u8 reserved_at_8[0x18];
5721
5722 u8 syndrome[0x20];
5723
5724 u8 reserved_at_40[0x40];
5725
5726 struct mlx5_ifc_srqc_bits srq_context_entry;
5727
5728 u8 reserved_at_280[0x600];
5729
5730 u8 pas[][0x40];
5731};
5732
5733struct mlx5_ifc_query_srq_in_bits {
5734 u8 opcode[0x10];
5735 u8 reserved_at_10[0x10];
5736
5737 u8 reserved_at_20[0x10];
5738 u8 op_mod[0x10];
5739
5740 u8 reserved_at_40[0x8];
5741 u8 srqn[0x18];
5742
5743 u8 reserved_at_60[0x20];
5744};
5745
5746struct mlx5_ifc_query_sq_out_bits {
5747 u8 status[0x8];
5748 u8 reserved_at_8[0x18];
5749
5750 u8 syndrome[0x20];
5751
5752 u8 reserved_at_40[0xc0];
5753
5754 struct mlx5_ifc_sqc_bits sq_context;
5755};
5756
5757struct mlx5_ifc_query_sq_in_bits {
5758 u8 opcode[0x10];
5759 u8 reserved_at_10[0x10];
5760
5761 u8 reserved_at_20[0x10];
5762 u8 op_mod[0x10];
5763
5764 u8 reserved_at_40[0x8];
5765 u8 sqn[0x18];
5766
5767 u8 reserved_at_60[0x20];
5768};
5769
5770struct mlx5_ifc_query_special_contexts_out_bits {
5771 u8 status[0x8];
5772 u8 reserved_at_8[0x18];
5773
5774 u8 syndrome[0x20];
5775
5776 u8 dump_fill_mkey[0x20];
5777
5778 u8 resd_lkey[0x20];
5779
5780 u8 null_mkey[0x20];
5781
5782 u8 terminate_scatter_list_mkey[0x20];
5783
5784 u8 repeated_mkey[0x20];
5785
5786 u8 reserved_at_a0[0x20];
5787};
5788
5789struct mlx5_ifc_query_special_contexts_in_bits {
5790 u8 opcode[0x10];
5791 u8 reserved_at_10[0x10];
5792
5793 u8 reserved_at_20[0x10];
5794 u8 op_mod[0x10];
5795
5796 u8 reserved_at_40[0x40];
5797};
5798
5799struct mlx5_ifc_query_scheduling_element_out_bits {
5800 u8 opcode[0x10];
5801 u8 reserved_at_10[0x10];
5802
5803 u8 reserved_at_20[0x10];
5804 u8 op_mod[0x10];
5805
5806 u8 reserved_at_40[0xc0];
5807
5808 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5809
5810 u8 reserved_at_300[0x100];
5811};
5812
5813enum {
5814 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5815 SCHEDULING_HIERARCHY_NIC = 0x3,
5816};
5817
5818struct mlx5_ifc_query_scheduling_element_in_bits {
5819 u8 opcode[0x10];
5820 u8 reserved_at_10[0x10];
5821
5822 u8 reserved_at_20[0x10];
5823 u8 op_mod[0x10];
5824
5825 u8 scheduling_hierarchy[0x8];
5826 u8 reserved_at_48[0x18];
5827
5828 u8 scheduling_element_id[0x20];
5829
5830 u8 reserved_at_80[0x180];
5831};
5832
5833struct mlx5_ifc_query_rqt_out_bits {
5834 u8 status[0x8];
5835 u8 reserved_at_8[0x18];
5836
5837 u8 syndrome[0x20];
5838
5839 u8 reserved_at_40[0xc0];
5840
5841 struct mlx5_ifc_rqtc_bits rqt_context;
5842};
5843
5844struct mlx5_ifc_query_rqt_in_bits {
5845 u8 opcode[0x10];
5846 u8 reserved_at_10[0x10];
5847
5848 u8 reserved_at_20[0x10];
5849 u8 op_mod[0x10];
5850
5851 u8 reserved_at_40[0x8];
5852 u8 rqtn[0x18];
5853
5854 u8 reserved_at_60[0x20];
5855};
5856
5857struct mlx5_ifc_query_rq_out_bits {
5858 u8 status[0x8];
5859 u8 reserved_at_8[0x18];
5860
5861 u8 syndrome[0x20];
5862
5863 u8 reserved_at_40[0xc0];
5864
5865 struct mlx5_ifc_rqc_bits rq_context;
5866};
5867
5868struct mlx5_ifc_query_rq_in_bits {
5869 u8 opcode[0x10];
5870 u8 reserved_at_10[0x10];
5871
5872 u8 reserved_at_20[0x10];
5873 u8 op_mod[0x10];
5874
5875 u8 reserved_at_40[0x8];
5876 u8 rqn[0x18];
5877
5878 u8 reserved_at_60[0x20];
5879};
5880
5881struct mlx5_ifc_query_roce_address_out_bits {
5882 u8 status[0x8];
5883 u8 reserved_at_8[0x18];
5884
5885 u8 syndrome[0x20];
5886
5887 u8 reserved_at_40[0x40];
5888
5889 struct mlx5_ifc_roce_addr_layout_bits roce_address;
5890};
5891
5892struct mlx5_ifc_query_roce_address_in_bits {
5893 u8 opcode[0x10];
5894 u8 reserved_at_10[0x10];
5895
5896 u8 reserved_at_20[0x10];
5897 u8 op_mod[0x10];
5898
5899 u8 roce_address_index[0x10];
5900 u8 reserved_at_50[0xc];
5901 u8 vhca_port_num[0x4];
5902
5903 u8 reserved_at_60[0x20];
5904};
5905
5906struct mlx5_ifc_query_rmp_out_bits {
5907 u8 status[0x8];
5908 u8 reserved_at_8[0x18];
5909
5910 u8 syndrome[0x20];
5911
5912 u8 reserved_at_40[0xc0];
5913
5914 struct mlx5_ifc_rmpc_bits rmp_context;
5915};
5916
5917struct mlx5_ifc_query_rmp_in_bits {
5918 u8 opcode[0x10];
5919 u8 reserved_at_10[0x10];
5920
5921 u8 reserved_at_20[0x10];
5922 u8 op_mod[0x10];
5923
5924 u8 reserved_at_40[0x8];
5925 u8 rmpn[0x18];
5926
5927 u8 reserved_at_60[0x20];
5928};
5929
5930struct mlx5_ifc_cqe_error_syndrome_bits {
5931 u8 hw_error_syndrome[0x8];
5932 u8 hw_syndrome_type[0x4];
5933 u8 reserved_at_c[0x4];
5934 u8 vendor_error_syndrome[0x8];
5935 u8 syndrome[0x8];
5936};
5937
5938struct mlx5_ifc_qp_context_extension_bits {
5939 u8 reserved_at_0[0x60];
5940
5941 struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5942
5943 u8 reserved_at_80[0x580];
5944};
5945
5946struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5947 struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5948
5949 u8 pas[0][0x40];
5950};
5951
5952struct mlx5_ifc_qp_pas_list_in_bits {
5953 struct mlx5_ifc_cmd_pas_bits pas[0];
5954};
5955
5956union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5957 struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5958 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5959};
5960
5961struct mlx5_ifc_query_qp_out_bits {
5962 u8 status[0x8];
5963 u8 reserved_at_8[0x18];
5964
5965 u8 syndrome[0x20];
5966
5967 u8 reserved_at_40[0x40];
5968
5969 u8 opt_param_mask[0x20];
5970
5971 u8 ece[0x20];
5972
5973 struct mlx5_ifc_qpc_bits qpc;
5974
5975 u8 reserved_at_800[0x80];
5976
5977 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5978};
5979
5980struct mlx5_ifc_query_qp_in_bits {
5981 u8 opcode[0x10];
5982 u8 reserved_at_10[0x10];
5983
5984 u8 reserved_at_20[0x10];
5985 u8 op_mod[0x10];
5986
5987 u8 qpc_ext[0x1];
5988 u8 reserved_at_41[0x7];
5989 u8 qpn[0x18];
5990
5991 u8 reserved_at_60[0x20];
5992};
5993
5994struct mlx5_ifc_query_q_counter_out_bits {
5995 u8 status[0x8];
5996 u8 reserved_at_8[0x18];
5997
5998 u8 syndrome[0x20];
5999
6000 u8 reserved_at_40[0x40];
6001
6002 u8 rx_write_requests[0x20];
6003
6004 u8 reserved_at_a0[0x20];
6005
6006 u8 rx_read_requests[0x20];
6007
6008 u8 reserved_at_e0[0x20];
6009
6010 u8 rx_atomic_requests[0x20];
6011
6012 u8 reserved_at_120[0x20];
6013
6014 u8 rx_dct_connect[0x20];
6015
6016 u8 reserved_at_160[0x20];
6017
6018 u8 out_of_buffer[0x20];
6019
6020 u8 reserved_at_1a0[0x20];
6021
6022 u8 out_of_sequence[0x20];
6023
6024 u8 reserved_at_1e0[0x20];
6025
6026 u8 duplicate_request[0x20];
6027
6028 u8 reserved_at_220[0x20];
6029
6030 u8 rnr_nak_retry_err[0x20];
6031
6032 u8 reserved_at_260[0x20];
6033
6034 u8 packet_seq_err[0x20];
6035
6036 u8 reserved_at_2a0[0x20];
6037
6038 u8 implied_nak_seq_err[0x20];
6039
6040 u8 reserved_at_2e0[0x20];
6041
6042 u8 local_ack_timeout_err[0x20];
6043
6044 u8 reserved_at_320[0x60];
6045
6046 u8 req_rnr_retries_exceeded[0x20];
6047
6048 u8 reserved_at_3a0[0x20];
6049
6050 u8 resp_local_length_error[0x20];
6051
6052 u8 req_local_length_error[0x20];
6053
6054 u8 resp_local_qp_error[0x20];
6055
6056 u8 local_operation_error[0x20];
6057
6058 u8 resp_local_protection[0x20];
6059
6060 u8 req_local_protection[0x20];
6061
6062 u8 resp_cqe_error[0x20];
6063
6064 u8 req_cqe_error[0x20];
6065
6066 u8 req_mw_binding[0x20];
6067
6068 u8 req_bad_response[0x20];
6069
6070 u8 req_remote_invalid_request[0x20];
6071
6072 u8 resp_remote_invalid_request[0x20];
6073
6074 u8 req_remote_access_errors[0x20];
6075
6076 u8 resp_remote_access_errors[0x20];
6077
6078 u8 req_remote_operation_errors[0x20];
6079
6080 u8 req_transport_retries_exceeded[0x20];
6081
6082 u8 cq_overflow[0x20];
6083
6084 u8 resp_cqe_flush_error[0x20];
6085
6086 u8 req_cqe_flush_error[0x20];
6087
6088 u8 reserved_at_620[0x20];
6089
6090 u8 roce_adp_retrans[0x20];
6091
6092 u8 roce_adp_retrans_to[0x20];
6093
6094 u8 roce_slow_restart[0x20];
6095
6096 u8 roce_slow_restart_cnps[0x20];
6097
6098 u8 roce_slow_restart_trans[0x20];
6099
6100 u8 reserved_at_6e0[0x120];
6101};
6102
6103struct mlx5_ifc_query_q_counter_in_bits {
6104 u8 opcode[0x10];
6105 u8 reserved_at_10[0x10];
6106
6107 u8 reserved_at_20[0x10];
6108 u8 op_mod[0x10];
6109
6110 u8 other_vport[0x1];
6111 u8 reserved_at_41[0xf];
6112 u8 vport_number[0x10];
6113
6114 u8 reserved_at_60[0x60];
6115
6116 u8 clear[0x1];
6117 u8 aggregate[0x1];
6118 u8 reserved_at_c2[0x1e];
6119
6120 u8 reserved_at_e0[0x18];
6121 u8 counter_set_id[0x8];
6122};
6123
6124struct mlx5_ifc_query_pages_out_bits {
6125 u8 status[0x8];
6126 u8 reserved_at_8[0x18];
6127
6128 u8 syndrome[0x20];
6129
6130 u8 embedded_cpu_function[0x1];
6131 u8 reserved_at_41[0xf];
6132 u8 function_id[0x10];
6133
6134 u8 num_pages[0x20];
6135};
6136
6137enum {
6138 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
6139 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
6140 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
6141};
6142
6143struct mlx5_ifc_query_pages_in_bits {
6144 u8 opcode[0x10];
6145 u8 reserved_at_10[0x10];
6146
6147 u8 reserved_at_20[0x10];
6148 u8 op_mod[0x10];
6149
6150 u8 embedded_cpu_function[0x1];
6151 u8 reserved_at_41[0xf];
6152 u8 function_id[0x10];
6153
6154 u8 reserved_at_60[0x20];
6155};
6156
6157struct mlx5_ifc_query_nic_vport_context_out_bits {
6158 u8 status[0x8];
6159 u8 reserved_at_8[0x18];
6160
6161 u8 syndrome[0x20];
6162
6163 u8 reserved_at_40[0x40];
6164
6165 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6166};
6167
6168struct mlx5_ifc_query_nic_vport_context_in_bits {
6169 u8 opcode[0x10];
6170 u8 reserved_at_10[0x10];
6171
6172 u8 reserved_at_20[0x10];
6173 u8 op_mod[0x10];
6174
6175 u8 other_vport[0x1];
6176 u8 reserved_at_41[0xf];
6177 u8 vport_number[0x10];
6178
6179 u8 reserved_at_60[0x5];
6180 u8 allowed_list_type[0x3];
6181 u8 reserved_at_68[0x18];
6182};
6183
6184struct mlx5_ifc_query_mkey_out_bits {
6185 u8 status[0x8];
6186 u8 reserved_at_8[0x18];
6187
6188 u8 syndrome[0x20];
6189
6190 u8 reserved_at_40[0x40];
6191
6192 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6193
6194 u8 reserved_at_280[0x600];
6195
6196 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
6197
6198 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
6199};
6200
6201struct mlx5_ifc_query_mkey_in_bits {
6202 u8 opcode[0x10];
6203 u8 reserved_at_10[0x10];
6204
6205 u8 reserved_at_20[0x10];
6206 u8 op_mod[0x10];
6207
6208 u8 reserved_at_40[0x8];
6209 u8 mkey_index[0x18];
6210
6211 u8 pg_access[0x1];
6212 u8 reserved_at_61[0x1f];
6213};
6214
6215struct mlx5_ifc_query_mad_demux_out_bits {
6216 u8 status[0x8];
6217 u8 reserved_at_8[0x18];
6218
6219 u8 syndrome[0x20];
6220
6221 u8 reserved_at_40[0x40];
6222
6223 u8 mad_dumux_parameters_block[0x20];
6224};
6225
6226struct mlx5_ifc_query_mad_demux_in_bits {
6227 u8 opcode[0x10];
6228 u8 reserved_at_10[0x10];
6229
6230 u8 reserved_at_20[0x10];
6231 u8 op_mod[0x10];
6232
6233 u8 reserved_at_40[0x40];
6234};
6235
6236struct mlx5_ifc_query_l2_table_entry_out_bits {
6237 u8 status[0x8];
6238 u8 reserved_at_8[0x18];
6239
6240 u8 syndrome[0x20];
6241
6242 u8 reserved_at_40[0xa0];
6243
6244 u8 reserved_at_e0[0x13];
6245 u8 vlan_valid[0x1];
6246 u8 vlan[0xc];
6247
6248 struct mlx5_ifc_mac_address_layout_bits mac_address;
6249
6250 u8 reserved_at_140[0xc0];
6251};
6252
6253struct mlx5_ifc_query_l2_table_entry_in_bits {
6254 u8 opcode[0x10];
6255 u8 reserved_at_10[0x10];
6256
6257 u8 reserved_at_20[0x10];
6258 u8 op_mod[0x10];
6259
6260 u8 reserved_at_40[0x60];
6261
6262 u8 reserved_at_a0[0x8];
6263 u8 table_index[0x18];
6264
6265 u8 reserved_at_c0[0x140];
6266};
6267
6268struct mlx5_ifc_query_issi_out_bits {
6269 u8 status[0x8];
6270 u8 reserved_at_8[0x18];
6271
6272 u8 syndrome[0x20];
6273
6274 u8 reserved_at_40[0x10];
6275 u8 current_issi[0x10];
6276
6277 u8 reserved_at_60[0xa0];
6278
6279 u8 reserved_at_100[76][0x8];
6280 u8 supported_issi_dw0[0x20];
6281};
6282
6283struct mlx5_ifc_query_issi_in_bits {
6284 u8 opcode[0x10];
6285 u8 reserved_at_10[0x10];
6286
6287 u8 reserved_at_20[0x10];
6288 u8 op_mod[0x10];
6289
6290 u8 reserved_at_40[0x40];
6291};
6292
6293struct mlx5_ifc_set_driver_version_out_bits {
6294 u8 status[0x8];
6295 u8 reserved_0[0x18];
6296
6297 u8 syndrome[0x20];
6298 u8 reserved_1[0x40];
6299};
6300
6301struct mlx5_ifc_set_driver_version_in_bits {
6302 u8 opcode[0x10];
6303 u8 reserved_0[0x10];
6304
6305 u8 reserved_1[0x10];
6306 u8 op_mod[0x10];
6307
6308 u8 reserved_2[0x40];
6309 u8 driver_version[64][0x8];
6310};
6311
6312struct mlx5_ifc_query_hca_vport_pkey_out_bits {
6313 u8 status[0x8];
6314 u8 reserved_at_8[0x18];
6315
6316 u8 syndrome[0x20];
6317
6318 u8 reserved_at_40[0x40];
6319
6320 struct mlx5_ifc_pkey_bits pkey[];
6321};
6322
6323struct mlx5_ifc_query_hca_vport_pkey_in_bits {
6324 u8 opcode[0x10];
6325 u8 reserved_at_10[0x10];
6326
6327 u8 reserved_at_20[0x10];
6328 u8 op_mod[0x10];
6329
6330 u8 other_vport[0x1];
6331 u8 reserved_at_41[0xb];
6332 u8 port_num[0x4];
6333 u8 vport_number[0x10];
6334
6335 u8 reserved_at_60[0x10];
6336 u8 pkey_index[0x10];
6337};
6338
6339enum {
6340 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
6341 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
6342 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
6343};
6344
6345struct mlx5_ifc_query_hca_vport_gid_out_bits {
6346 u8 status[0x8];
6347 u8 reserved_at_8[0x18];
6348
6349 u8 syndrome[0x20];
6350
6351 u8 reserved_at_40[0x20];
6352
6353 u8 gids_num[0x10];
6354 u8 reserved_at_70[0x10];
6355
6356 struct mlx5_ifc_array128_auto_bits gid[];
6357};
6358
6359struct mlx5_ifc_query_hca_vport_gid_in_bits {
6360 u8 opcode[0x10];
6361 u8 reserved_at_10[0x10];
6362
6363 u8 reserved_at_20[0x10];
6364 u8 op_mod[0x10];
6365
6366 u8 other_vport[0x1];
6367 u8 reserved_at_41[0xb];
6368 u8 port_num[0x4];
6369 u8 vport_number[0x10];
6370
6371 u8 reserved_at_60[0x10];
6372 u8 gid_index[0x10];
6373};
6374
6375struct mlx5_ifc_query_hca_vport_context_out_bits {
6376 u8 status[0x8];
6377 u8 reserved_at_8[0x18];
6378
6379 u8 syndrome[0x20];
6380
6381 u8 reserved_at_40[0x40];
6382
6383 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6384};
6385
6386struct mlx5_ifc_query_hca_vport_context_in_bits {
6387 u8 opcode[0x10];
6388 u8 reserved_at_10[0x10];
6389
6390 u8 reserved_at_20[0x10];
6391 u8 op_mod[0x10];
6392
6393 u8 other_vport[0x1];
6394 u8 reserved_at_41[0xb];
6395 u8 port_num[0x4];
6396 u8 vport_number[0x10];
6397
6398 u8 reserved_at_60[0x20];
6399};
6400
6401struct mlx5_ifc_query_hca_cap_out_bits {
6402 u8 status[0x8];
6403 u8 reserved_at_8[0x18];
6404
6405 u8 syndrome[0x20];
6406
6407 u8 reserved_at_40[0x40];
6408
6409 union mlx5_ifc_hca_cap_union_bits capability;
6410};
6411
6412struct mlx5_ifc_query_hca_cap_in_bits {
6413 u8 opcode[0x10];
6414 u8 reserved_at_10[0x10];
6415
6416 u8 reserved_at_20[0x10];
6417 u8 op_mod[0x10];
6418
6419 u8 other_function[0x1];
6420 u8 ec_vf_function[0x1];
6421 u8 reserved_at_42[0x1];
6422 u8 function_id_type[0x1];
6423 u8 reserved_at_44[0xc];
6424 u8 function_id[0x10];
6425
6426 u8 reserved_at_60[0x20];
6427};
6428
6429struct mlx5_ifc_other_hca_cap_bits {
6430 u8 roce[0x1];
6431 u8 reserved_at_1[0x27f];
6432};
6433
6434struct mlx5_ifc_query_other_hca_cap_out_bits {
6435 u8 status[0x8];
6436 u8 reserved_at_8[0x18];
6437
6438 u8 syndrome[0x20];
6439
6440 u8 reserved_at_40[0x40];
6441
6442 struct mlx5_ifc_other_hca_cap_bits other_capability;
6443};
6444
6445struct mlx5_ifc_query_other_hca_cap_in_bits {
6446 u8 opcode[0x10];
6447 u8 reserved_at_10[0x10];
6448
6449 u8 reserved_at_20[0x10];
6450 u8 op_mod[0x10];
6451
6452 u8 reserved_at_40[0x10];
6453 u8 function_id[0x10];
6454
6455 u8 reserved_at_60[0x20];
6456};
6457
6458struct mlx5_ifc_modify_other_hca_cap_out_bits {
6459 u8 status[0x8];
6460 u8 reserved_at_8[0x18];
6461
6462 u8 syndrome[0x20];
6463
6464 u8 reserved_at_40[0x40];
6465};
6466
6467struct mlx5_ifc_modify_other_hca_cap_in_bits {
6468 u8 opcode[0x10];
6469 u8 reserved_at_10[0x10];
6470
6471 u8 reserved_at_20[0x10];
6472 u8 op_mod[0x10];
6473
6474 u8 reserved_at_40[0x10];
6475 u8 function_id[0x10];
6476 u8 field_select[0x20];
6477
6478 struct mlx5_ifc_other_hca_cap_bits other_capability;
6479};
6480
6481struct mlx5_ifc_sw_owner_icm_root_params_bits {
6482 u8 sw_owner_icm_root_1[0x40];
6483
6484 u8 sw_owner_icm_root_0[0x40];
6485};
6486
6487struct mlx5_ifc_rtc_params_bits {
6488 u8 rtc_id_0[0x20];
6489
6490 u8 rtc_id_1[0x20];
6491
6492 u8 reserved_at_40[0x40];
6493};
6494
6495struct mlx5_ifc_flow_table_context_bits {
6496 u8 reformat_en[0x1];
6497 u8 decap_en[0x1];
6498 u8 sw_owner[0x1];
6499 u8 termination_table[0x1];
6500 u8 table_miss_action[0x4];
6501 u8 level[0x8];
6502 u8 rtc_valid[0x1];
6503 u8 reserved_at_11[0x7];
6504 u8 log_size[0x8];
6505
6506 u8 reserved_at_20[0x8];
6507 u8 table_miss_id[0x18];
6508
6509 u8 reserved_at_40[0x8];
6510 u8 lag_master_next_table_id[0x18];
6511
6512 u8 reserved_at_60[0x60];
6513
6514 union {
6515 struct mlx5_ifc_sw_owner_icm_root_params_bits sws;
6516 struct mlx5_ifc_rtc_params_bits hws;
6517 };
6518};
6519
6520struct mlx5_ifc_query_flow_table_out_bits {
6521 u8 status[0x8];
6522 u8 reserved_at_8[0x18];
6523
6524 u8 syndrome[0x20];
6525
6526 u8 reserved_at_40[0x80];
6527
6528 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6529};
6530
6531struct mlx5_ifc_query_flow_table_in_bits {
6532 u8 opcode[0x10];
6533 u8 reserved_at_10[0x10];
6534
6535 u8 reserved_at_20[0x10];
6536 u8 op_mod[0x10];
6537
6538 u8 reserved_at_40[0x40];
6539
6540 u8 table_type[0x8];
6541 u8 reserved_at_88[0x18];
6542
6543 u8 reserved_at_a0[0x8];
6544 u8 table_id[0x18];
6545
6546 u8 reserved_at_c0[0x140];
6547};
6548
6549struct mlx5_ifc_query_fte_out_bits {
6550 u8 status[0x8];
6551 u8 reserved_at_8[0x18];
6552
6553 u8 syndrome[0x20];
6554
6555 u8 reserved_at_40[0x1c0];
6556
6557 struct mlx5_ifc_flow_context_bits flow_context;
6558};
6559
6560struct mlx5_ifc_query_fte_in_bits {
6561 u8 opcode[0x10];
6562 u8 reserved_at_10[0x10];
6563
6564 u8 reserved_at_20[0x10];
6565 u8 op_mod[0x10];
6566
6567 u8 reserved_at_40[0x40];
6568
6569 u8 table_type[0x8];
6570 u8 reserved_at_88[0x18];
6571
6572 u8 reserved_at_a0[0x8];
6573 u8 table_id[0x18];
6574
6575 u8 reserved_at_c0[0x40];
6576
6577 u8 flow_index[0x20];
6578
6579 u8 reserved_at_120[0xe0];
6580};
6581
6582struct mlx5_ifc_match_definer_format_0_bits {
6583 u8 reserved_at_0[0x100];
6584
6585 u8 metadata_reg_c_0[0x20];
6586
6587 u8 metadata_reg_c_1[0x20];
6588
6589 u8 outer_dmac_47_16[0x20];
6590
6591 u8 outer_dmac_15_0[0x10];
6592 u8 outer_ethertype[0x10];
6593
6594 u8 reserved_at_180[0x1];
6595 u8 sx_sniffer[0x1];
6596 u8 functional_lb[0x1];
6597 u8 outer_ip_frag[0x1];
6598 u8 outer_qp_type[0x2];
6599 u8 outer_encap_type[0x2];
6600 u8 port_number[0x2];
6601 u8 outer_l3_type[0x2];
6602 u8 outer_l4_type[0x2];
6603 u8 outer_first_vlan_type[0x2];
6604 u8 outer_first_vlan_prio[0x3];
6605 u8 outer_first_vlan_cfi[0x1];
6606 u8 outer_first_vlan_vid[0xc];
6607
6608 u8 outer_l4_type_ext[0x4];
6609 u8 reserved_at_1a4[0x2];
6610 u8 outer_ipsec_layer[0x2];
6611 u8 outer_l2_type[0x2];
6612 u8 force_lb[0x1];
6613 u8 outer_l2_ok[0x1];
6614 u8 outer_l3_ok[0x1];
6615 u8 outer_l4_ok[0x1];
6616 u8 outer_second_vlan_type[0x2];
6617 u8 outer_second_vlan_prio[0x3];
6618 u8 outer_second_vlan_cfi[0x1];
6619 u8 outer_second_vlan_vid[0xc];
6620
6621 u8 outer_smac_47_16[0x20];
6622
6623 u8 outer_smac_15_0[0x10];
6624 u8 inner_ipv4_checksum_ok[0x1];
6625 u8 inner_l4_checksum_ok[0x1];
6626 u8 outer_ipv4_checksum_ok[0x1];
6627 u8 outer_l4_checksum_ok[0x1];
6628 u8 inner_l3_ok[0x1];
6629 u8 inner_l4_ok[0x1];
6630 u8 outer_l3_ok_duplicate[0x1];
6631 u8 outer_l4_ok_duplicate[0x1];
6632 u8 outer_tcp_cwr[0x1];
6633 u8 outer_tcp_ece[0x1];
6634 u8 outer_tcp_urg[0x1];
6635 u8 outer_tcp_ack[0x1];
6636 u8 outer_tcp_psh[0x1];
6637 u8 outer_tcp_rst[0x1];
6638 u8 outer_tcp_syn[0x1];
6639 u8 outer_tcp_fin[0x1];
6640};
6641
6642struct mlx5_ifc_match_definer_format_22_bits {
6643 u8 reserved_at_0[0x100];
6644
6645 u8 outer_ip_src_addr[0x20];
6646
6647 u8 outer_ip_dest_addr[0x20];
6648
6649 u8 outer_l4_sport[0x10];
6650 u8 outer_l4_dport[0x10];
6651
6652 u8 reserved_at_160[0x1];
6653 u8 sx_sniffer[0x1];
6654 u8 functional_lb[0x1];
6655 u8 outer_ip_frag[0x1];
6656 u8 outer_qp_type[0x2];
6657 u8 outer_encap_type[0x2];
6658 u8 port_number[0x2];
6659 u8 outer_l3_type[0x2];
6660 u8 outer_l4_type[0x2];
6661 u8 outer_first_vlan_type[0x2];
6662 u8 outer_first_vlan_prio[0x3];
6663 u8 outer_first_vlan_cfi[0x1];
6664 u8 outer_first_vlan_vid[0xc];
6665
6666 u8 metadata_reg_c_0[0x20];
6667
6668 u8 outer_dmac_47_16[0x20];
6669
6670 u8 outer_smac_47_16[0x20];
6671
6672 u8 outer_smac_15_0[0x10];
6673 u8 outer_dmac_15_0[0x10];
6674};
6675
6676struct mlx5_ifc_match_definer_format_23_bits {
6677 u8 reserved_at_0[0x100];
6678
6679 u8 inner_ip_src_addr[0x20];
6680
6681 u8 inner_ip_dest_addr[0x20];
6682
6683 u8 inner_l4_sport[0x10];
6684 u8 inner_l4_dport[0x10];
6685
6686 u8 reserved_at_160[0x1];
6687 u8 sx_sniffer[0x1];
6688 u8 functional_lb[0x1];
6689 u8 inner_ip_frag[0x1];
6690 u8 inner_qp_type[0x2];
6691 u8 inner_encap_type[0x2];
6692 u8 port_number[0x2];
6693 u8 inner_l3_type[0x2];
6694 u8 inner_l4_type[0x2];
6695 u8 inner_first_vlan_type[0x2];
6696 u8 inner_first_vlan_prio[0x3];
6697 u8 inner_first_vlan_cfi[0x1];
6698 u8 inner_first_vlan_vid[0xc];
6699
6700 u8 tunnel_header_0[0x20];
6701
6702 u8 inner_dmac_47_16[0x20];
6703
6704 u8 inner_smac_47_16[0x20];
6705
6706 u8 inner_smac_15_0[0x10];
6707 u8 inner_dmac_15_0[0x10];
6708};
6709
6710struct mlx5_ifc_match_definer_format_29_bits {
6711 u8 reserved_at_0[0xc0];
6712
6713 u8 outer_ip_dest_addr[0x80];
6714
6715 u8 outer_ip_src_addr[0x80];
6716
6717 u8 outer_l4_sport[0x10];
6718 u8 outer_l4_dport[0x10];
6719
6720 u8 reserved_at_1e0[0x20];
6721};
6722
6723struct mlx5_ifc_match_definer_format_30_bits {
6724 u8 reserved_at_0[0xa0];
6725
6726 u8 outer_ip_dest_addr[0x80];
6727
6728 u8 outer_ip_src_addr[0x80];
6729
6730 u8 outer_dmac_47_16[0x20];
6731
6732 u8 outer_smac_47_16[0x20];
6733
6734 u8 outer_smac_15_0[0x10];
6735 u8 outer_dmac_15_0[0x10];
6736};
6737
6738struct mlx5_ifc_match_definer_format_31_bits {
6739 u8 reserved_at_0[0xc0];
6740
6741 u8 inner_ip_dest_addr[0x80];
6742
6743 u8 inner_ip_src_addr[0x80];
6744
6745 u8 inner_l4_sport[0x10];
6746 u8 inner_l4_dport[0x10];
6747
6748 u8 reserved_at_1e0[0x20];
6749};
6750
6751struct mlx5_ifc_match_definer_format_32_bits {
6752 u8 reserved_at_0[0xa0];
6753
6754 u8 inner_ip_dest_addr[0x80];
6755
6756 u8 inner_ip_src_addr[0x80];
6757
6758 u8 inner_dmac_47_16[0x20];
6759
6760 u8 inner_smac_47_16[0x20];
6761
6762 u8 inner_smac_15_0[0x10];
6763 u8 inner_dmac_15_0[0x10];
6764};
6765
6766enum {
6767 MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6768};
6769
6770#define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6771#define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6772#define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6773#define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6774
6775struct mlx5_ifc_match_definer_match_mask_bits {
6776 u8 reserved_at_1c0[5][0x20];
6777 u8 match_dw_8[0x20];
6778 u8 match_dw_7[0x20];
6779 u8 match_dw_6[0x20];
6780 u8 match_dw_5[0x20];
6781 u8 match_dw_4[0x20];
6782 u8 match_dw_3[0x20];
6783 u8 match_dw_2[0x20];
6784 u8 match_dw_1[0x20];
6785 u8 match_dw_0[0x20];
6786
6787 u8 match_byte_7[0x8];
6788 u8 match_byte_6[0x8];
6789 u8 match_byte_5[0x8];
6790 u8 match_byte_4[0x8];
6791
6792 u8 match_byte_3[0x8];
6793 u8 match_byte_2[0x8];
6794 u8 match_byte_1[0x8];
6795 u8 match_byte_0[0x8];
6796};
6797
6798struct mlx5_ifc_match_definer_bits {
6799 u8 modify_field_select[0x40];
6800
6801 u8 reserved_at_40[0x40];
6802
6803 u8 reserved_at_80[0x10];
6804 u8 format_id[0x10];
6805
6806 u8 reserved_at_a0[0x60];
6807
6808 u8 format_select_dw3[0x8];
6809 u8 format_select_dw2[0x8];
6810 u8 format_select_dw1[0x8];
6811 u8 format_select_dw0[0x8];
6812
6813 u8 format_select_dw7[0x8];
6814 u8 format_select_dw6[0x8];
6815 u8 format_select_dw5[0x8];
6816 u8 format_select_dw4[0x8];
6817
6818 u8 reserved_at_100[0x18];
6819 u8 format_select_dw8[0x8];
6820
6821 u8 reserved_at_120[0x20];
6822
6823 u8 format_select_byte3[0x8];
6824 u8 format_select_byte2[0x8];
6825 u8 format_select_byte1[0x8];
6826 u8 format_select_byte0[0x8];
6827
6828 u8 format_select_byte7[0x8];
6829 u8 format_select_byte6[0x8];
6830 u8 format_select_byte5[0x8];
6831 u8 format_select_byte4[0x8];
6832
6833 u8 reserved_at_180[0x40];
6834
6835 union {
6836 struct {
6837 u8 match_mask[16][0x20];
6838 };
6839 struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6840 };
6841};
6842
6843struct mlx5_ifc_general_obj_create_param_bits {
6844 u8 alias_object[0x1];
6845 u8 reserved_at_1[0x2];
6846 u8 log_obj_range[0x5];
6847 u8 reserved_at_8[0x18];
6848};
6849
6850struct mlx5_ifc_general_obj_query_param_bits {
6851 u8 alias_object[0x1];
6852 u8 obj_offset[0x1f];
6853};
6854
6855struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6856 u8 opcode[0x10];
6857 u8 uid[0x10];
6858
6859 u8 vhca_tunnel_id[0x10];
6860 u8 obj_type[0x10];
6861
6862 u8 obj_id[0x20];
6863
6864 union {
6865 struct mlx5_ifc_general_obj_create_param_bits create;
6866 struct mlx5_ifc_general_obj_query_param_bits query;
6867 } op_param;
6868};
6869
6870struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6871 u8 status[0x8];
6872 u8 reserved_at_8[0x18];
6873
6874 u8 syndrome[0x20];
6875
6876 u8 obj_id[0x20];
6877
6878 u8 reserved_at_60[0x20];
6879};
6880
6881struct mlx5_ifc_allow_other_vhca_access_in_bits {
6882 u8 opcode[0x10];
6883 u8 uid[0x10];
6884 u8 reserved_at_20[0x10];
6885 u8 op_mod[0x10];
6886 u8 reserved_at_40[0x50];
6887 u8 object_type_to_be_accessed[0x10];
6888 u8 object_id_to_be_accessed[0x20];
6889 u8 reserved_at_c0[0x40];
6890 union {
6891 u8 access_key_raw[0x100];
6892 u8 access_key[8][0x20];
6893 };
6894};
6895
6896struct mlx5_ifc_allow_other_vhca_access_out_bits {
6897 u8 status[0x8];
6898 u8 reserved_at_8[0x18];
6899 u8 syndrome[0x20];
6900 u8 reserved_at_40[0x40];
6901};
6902
6903struct mlx5_ifc_modify_header_arg_bits {
6904 u8 reserved_at_0[0x80];
6905
6906 u8 reserved_at_80[0x8];
6907 u8 access_pd[0x18];
6908};
6909
6910struct mlx5_ifc_create_modify_header_arg_in_bits {
6911 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6912 struct mlx5_ifc_modify_header_arg_bits arg;
6913};
6914
6915struct mlx5_ifc_create_match_definer_in_bits {
6916 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6917
6918 struct mlx5_ifc_match_definer_bits obj_context;
6919};
6920
6921struct mlx5_ifc_create_match_definer_out_bits {
6922 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6923};
6924
6925struct mlx5_ifc_alias_context_bits {
6926 u8 vhca_id_to_be_accessed[0x10];
6927 u8 reserved_at_10[0xd];
6928 u8 status[0x3];
6929 u8 object_id_to_be_accessed[0x20];
6930 u8 reserved_at_40[0x40];
6931 union {
6932 u8 access_key_raw[0x100];
6933 u8 access_key[8][0x20];
6934 };
6935 u8 metadata[0x80];
6936};
6937
6938struct mlx5_ifc_create_alias_obj_in_bits {
6939 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6940 struct mlx5_ifc_alias_context_bits alias_ctx;
6941};
6942
6943enum {
6944 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6945 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6946 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6947 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6948 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6949 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6950 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6951};
6952
6953struct mlx5_ifc_query_flow_group_out_bits {
6954 u8 status[0x8];
6955 u8 reserved_at_8[0x18];
6956
6957 u8 syndrome[0x20];
6958
6959 u8 reserved_at_40[0xa0];
6960
6961 u8 start_flow_index[0x20];
6962
6963 u8 reserved_at_100[0x20];
6964
6965 u8 end_flow_index[0x20];
6966
6967 u8 reserved_at_140[0xa0];
6968
6969 u8 reserved_at_1e0[0x18];
6970 u8 match_criteria_enable[0x8];
6971
6972 struct mlx5_ifc_fte_match_param_bits match_criteria;
6973
6974 u8 reserved_at_1200[0xe00];
6975};
6976
6977struct mlx5_ifc_query_flow_group_in_bits {
6978 u8 opcode[0x10];
6979 u8 reserved_at_10[0x10];
6980
6981 u8 reserved_at_20[0x10];
6982 u8 op_mod[0x10];
6983
6984 u8 reserved_at_40[0x40];
6985
6986 u8 table_type[0x8];
6987 u8 reserved_at_88[0x18];
6988
6989 u8 reserved_at_a0[0x8];
6990 u8 table_id[0x18];
6991
6992 u8 group_id[0x20];
6993
6994 u8 reserved_at_e0[0x120];
6995};
6996
6997struct mlx5_ifc_query_flow_counter_out_bits {
6998 u8 status[0x8];
6999 u8 reserved_at_8[0x18];
7000
7001 u8 syndrome[0x20];
7002
7003 u8 reserved_at_40[0x40];
7004
7005 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
7006};
7007
7008struct mlx5_ifc_query_flow_counter_in_bits {
7009 u8 opcode[0x10];
7010 u8 reserved_at_10[0x10];
7011
7012 u8 reserved_at_20[0x10];
7013 u8 op_mod[0x10];
7014
7015 u8 reserved_at_40[0x80];
7016
7017 u8 clear[0x1];
7018 u8 reserved_at_c1[0xf];
7019 u8 num_of_counters[0x10];
7020
7021 u8 flow_counter_id[0x20];
7022};
7023
7024struct mlx5_ifc_query_esw_vport_context_out_bits {
7025 u8 status[0x8];
7026 u8 reserved_at_8[0x18];
7027
7028 u8 syndrome[0x20];
7029
7030 u8 reserved_at_40[0x40];
7031
7032 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7033};
7034
7035struct mlx5_ifc_query_esw_vport_context_in_bits {
7036 u8 opcode[0x10];
7037 u8 reserved_at_10[0x10];
7038
7039 u8 reserved_at_20[0x10];
7040 u8 op_mod[0x10];
7041
7042 u8 other_vport[0x1];
7043 u8 reserved_at_41[0xf];
7044 u8 vport_number[0x10];
7045
7046 u8 reserved_at_60[0x20];
7047};
7048
7049struct mlx5_ifc_destroy_esw_vport_out_bits {
7050 u8 status[0x8];
7051 u8 reserved_at_8[0x18];
7052
7053 u8 syndrome[0x20];
7054
7055 u8 reserved_at_40[0x20];
7056};
7057
7058struct mlx5_ifc_destroy_esw_vport_in_bits {
7059 u8 opcode[0x10];
7060 u8 uid[0x10];
7061
7062 u8 reserved_at_20[0x10];
7063 u8 op_mod[0x10];
7064
7065 u8 reserved_at_40[0x10];
7066 u8 vport_num[0x10];
7067
7068 u8 reserved_at_60[0x20];
7069};
7070
7071struct mlx5_ifc_modify_esw_vport_context_out_bits {
7072 u8 status[0x8];
7073 u8 reserved_at_8[0x18];
7074
7075 u8 syndrome[0x20];
7076
7077 u8 reserved_at_40[0x40];
7078};
7079
7080struct mlx5_ifc_esw_vport_context_fields_select_bits {
7081 u8 reserved_at_0[0x1b];
7082 u8 fdb_to_vport_reg_c_id[0x1];
7083 u8 vport_cvlan_insert[0x1];
7084 u8 vport_svlan_insert[0x1];
7085 u8 vport_cvlan_strip[0x1];
7086 u8 vport_svlan_strip[0x1];
7087};
7088
7089struct mlx5_ifc_modify_esw_vport_context_in_bits {
7090 u8 opcode[0x10];
7091 u8 reserved_at_10[0x10];
7092
7093 u8 reserved_at_20[0x10];
7094 u8 op_mod[0x10];
7095
7096 u8 other_vport[0x1];
7097 u8 reserved_at_41[0xf];
7098 u8 vport_number[0x10];
7099
7100 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
7101
7102 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
7103};
7104
7105struct mlx5_ifc_query_eq_out_bits {
7106 u8 status[0x8];
7107 u8 reserved_at_8[0x18];
7108
7109 u8 syndrome[0x20];
7110
7111 u8 reserved_at_40[0x40];
7112
7113 struct mlx5_ifc_eqc_bits eq_context_entry;
7114
7115 u8 reserved_at_280[0x40];
7116
7117 u8 event_bitmask[0x40];
7118
7119 u8 reserved_at_300[0x580];
7120
7121 u8 pas[][0x40];
7122};
7123
7124struct mlx5_ifc_query_eq_in_bits {
7125 u8 opcode[0x10];
7126 u8 reserved_at_10[0x10];
7127
7128 u8 reserved_at_20[0x10];
7129 u8 op_mod[0x10];
7130
7131 u8 reserved_at_40[0x18];
7132 u8 eq_number[0x8];
7133
7134 u8 reserved_at_60[0x20];
7135};
7136
7137struct mlx5_ifc_packet_reformat_context_in_bits {
7138 u8 reformat_type[0x8];
7139 u8 reserved_at_8[0x4];
7140 u8 reformat_param_0[0x4];
7141 u8 reserved_at_10[0x6];
7142 u8 reformat_data_size[0xa];
7143
7144 u8 reformat_param_1[0x8];
7145 u8 reserved_at_28[0x8];
7146 u8 reformat_data[2][0x8];
7147
7148 u8 more_reformat_data[][0x8];
7149};
7150
7151struct mlx5_ifc_query_packet_reformat_context_out_bits {
7152 u8 status[0x8];
7153 u8 reserved_at_8[0x18];
7154
7155 u8 syndrome[0x20];
7156
7157 u8 reserved_at_40[0xa0];
7158
7159 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
7160};
7161
7162struct mlx5_ifc_query_packet_reformat_context_in_bits {
7163 u8 opcode[0x10];
7164 u8 reserved_at_10[0x10];
7165
7166 u8 reserved_at_20[0x10];
7167 u8 op_mod[0x10];
7168
7169 u8 packet_reformat_id[0x20];
7170
7171 u8 reserved_at_60[0xa0];
7172};
7173
7174struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
7175 u8 status[0x8];
7176 u8 reserved_at_8[0x18];
7177
7178 u8 syndrome[0x20];
7179
7180 u8 packet_reformat_id[0x20];
7181
7182 u8 reserved_at_60[0x20];
7183};
7184
7185enum {
7186 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
7187 MLX5_REFORMAT_CONTEXT_ANCHOR_VLAN_START = 0x2,
7188 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
7189 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
7190};
7191
7192enum mlx5_reformat_ctx_type {
7193 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
7194 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
7195 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
7196 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
7197 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
7198 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
7199 MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
7200 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
7201 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
7202 MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
7203 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
7204 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
7205 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
7206 MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd,
7207 MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe,
7208 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
7209 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
7210 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
7211 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
7212};
7213
7214struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
7215 u8 opcode[0x10];
7216 u8 reserved_at_10[0x10];
7217
7218 u8 reserved_at_20[0x10];
7219 u8 op_mod[0x10];
7220
7221 u8 reserved_at_40[0xa0];
7222
7223 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
7224};
7225
7226struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
7227 u8 status[0x8];
7228 u8 reserved_at_8[0x18];
7229
7230 u8 syndrome[0x20];
7231
7232 u8 reserved_at_40[0x40];
7233};
7234
7235struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
7236 u8 opcode[0x10];
7237 u8 reserved_at_10[0x10];
7238
7239 u8 reserved_20[0x10];
7240 u8 op_mod[0x10];
7241
7242 u8 packet_reformat_id[0x20];
7243
7244 u8 reserved_60[0x20];
7245};
7246
7247struct mlx5_ifc_set_action_in_bits {
7248 u8 action_type[0x4];
7249 u8 field[0xc];
7250 u8 reserved_at_10[0x3];
7251 u8 offset[0x5];
7252 u8 reserved_at_18[0x3];
7253 u8 length[0x5];
7254
7255 u8 data[0x20];
7256};
7257
7258struct mlx5_ifc_add_action_in_bits {
7259 u8 action_type[0x4];
7260 u8 field[0xc];
7261 u8 reserved_at_10[0x10];
7262
7263 u8 data[0x20];
7264};
7265
7266struct mlx5_ifc_copy_action_in_bits {
7267 u8 action_type[0x4];
7268 u8 src_field[0xc];
7269 u8 reserved_at_10[0x3];
7270 u8 src_offset[0x5];
7271 u8 reserved_at_18[0x3];
7272 u8 length[0x5];
7273
7274 u8 reserved_at_20[0x4];
7275 u8 dst_field[0xc];
7276 u8 reserved_at_30[0x3];
7277 u8 dst_offset[0x5];
7278 u8 reserved_at_38[0x8];
7279};
7280
7281union mlx5_ifc_set_add_copy_action_in_auto_bits {
7282 struct mlx5_ifc_set_action_in_bits set_action_in;
7283 struct mlx5_ifc_add_action_in_bits add_action_in;
7284 struct mlx5_ifc_copy_action_in_bits copy_action_in;
7285 u8 reserved_at_0[0x40];
7286};
7287
7288enum {
7289 MLX5_ACTION_TYPE_SET = 0x1,
7290 MLX5_ACTION_TYPE_ADD = 0x2,
7291 MLX5_ACTION_TYPE_COPY = 0x3,
7292};
7293
7294enum {
7295 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
7296 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
7297 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
7298 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
7299 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
7300 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
7301 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
7302 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
7303 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
7304 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
7305 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
7306 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
7307 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
7308 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
7309 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
7310 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
7311 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
7312 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
7313 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
7314 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
7315 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
7316 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
7317 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
7318 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
7319 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
7320 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
7321 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
7322 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
7323 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
7324 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
7325 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
7326 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
7327 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
7328 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
7329 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
7330 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
7331 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
7332 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
7333 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
7334 MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71,
7335};
7336
7337struct mlx5_ifc_alloc_modify_header_context_out_bits {
7338 u8 status[0x8];
7339 u8 reserved_at_8[0x18];
7340
7341 u8 syndrome[0x20];
7342
7343 u8 modify_header_id[0x20];
7344
7345 u8 reserved_at_60[0x20];
7346};
7347
7348struct mlx5_ifc_alloc_modify_header_context_in_bits {
7349 u8 opcode[0x10];
7350 u8 reserved_at_10[0x10];
7351
7352 u8 reserved_at_20[0x10];
7353 u8 op_mod[0x10];
7354
7355 u8 reserved_at_40[0x20];
7356
7357 u8 table_type[0x8];
7358 u8 reserved_at_68[0x10];
7359 u8 num_of_actions[0x8];
7360
7361 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
7362};
7363
7364struct mlx5_ifc_dealloc_modify_header_context_out_bits {
7365 u8 status[0x8];
7366 u8 reserved_at_8[0x18];
7367
7368 u8 syndrome[0x20];
7369
7370 u8 reserved_at_40[0x40];
7371};
7372
7373struct mlx5_ifc_dealloc_modify_header_context_in_bits {
7374 u8 opcode[0x10];
7375 u8 reserved_at_10[0x10];
7376
7377 u8 reserved_at_20[0x10];
7378 u8 op_mod[0x10];
7379
7380 u8 modify_header_id[0x20];
7381
7382 u8 reserved_at_60[0x20];
7383};
7384
7385struct mlx5_ifc_query_modify_header_context_in_bits {
7386 u8 opcode[0x10];
7387 u8 uid[0x10];
7388
7389 u8 reserved_at_20[0x10];
7390 u8 op_mod[0x10];
7391
7392 u8 modify_header_id[0x20];
7393
7394 u8 reserved_at_60[0xa0];
7395};
7396
7397struct mlx5_ifc_query_dct_out_bits {
7398 u8 status[0x8];
7399 u8 reserved_at_8[0x18];
7400
7401 u8 syndrome[0x20];
7402
7403 u8 reserved_at_40[0x40];
7404
7405 struct mlx5_ifc_dctc_bits dct_context_entry;
7406
7407 u8 reserved_at_280[0x180];
7408};
7409
7410struct mlx5_ifc_query_dct_in_bits {
7411 u8 opcode[0x10];
7412 u8 reserved_at_10[0x10];
7413
7414 u8 reserved_at_20[0x10];
7415 u8 op_mod[0x10];
7416
7417 u8 reserved_at_40[0x8];
7418 u8 dctn[0x18];
7419
7420 u8 reserved_at_60[0x20];
7421};
7422
7423struct mlx5_ifc_query_cq_out_bits {
7424 u8 status[0x8];
7425 u8 reserved_at_8[0x18];
7426
7427 u8 syndrome[0x20];
7428
7429 u8 reserved_at_40[0x40];
7430
7431 struct mlx5_ifc_cqc_bits cq_context;
7432
7433 u8 reserved_at_280[0x600];
7434
7435 u8 pas[][0x40];
7436};
7437
7438struct mlx5_ifc_query_cq_in_bits {
7439 u8 opcode[0x10];
7440 u8 reserved_at_10[0x10];
7441
7442 u8 reserved_at_20[0x10];
7443 u8 op_mod[0x10];
7444
7445 u8 reserved_at_40[0x8];
7446 u8 cqn[0x18];
7447
7448 u8 reserved_at_60[0x20];
7449};
7450
7451struct mlx5_ifc_query_cong_status_out_bits {
7452 u8 status[0x8];
7453 u8 reserved_at_8[0x18];
7454
7455 u8 syndrome[0x20];
7456
7457 u8 reserved_at_40[0x20];
7458
7459 u8 enable[0x1];
7460 u8 tag_enable[0x1];
7461 u8 reserved_at_62[0x1e];
7462};
7463
7464struct mlx5_ifc_query_cong_status_in_bits {
7465 u8 opcode[0x10];
7466 u8 reserved_at_10[0x10];
7467
7468 u8 reserved_at_20[0x10];
7469 u8 op_mod[0x10];
7470
7471 u8 reserved_at_40[0x18];
7472 u8 priority[0x4];
7473 u8 cong_protocol[0x4];
7474
7475 u8 reserved_at_60[0x20];
7476};
7477
7478struct mlx5_ifc_query_cong_statistics_out_bits {
7479 u8 status[0x8];
7480 u8 reserved_at_8[0x18];
7481
7482 u8 syndrome[0x20];
7483
7484 u8 reserved_at_40[0x40];
7485
7486 u8 rp_cur_flows[0x20];
7487
7488 u8 sum_flows[0x20];
7489
7490 u8 rp_cnp_ignored_high[0x20];
7491
7492 u8 rp_cnp_ignored_low[0x20];
7493
7494 u8 rp_cnp_handled_high[0x20];
7495
7496 u8 rp_cnp_handled_low[0x20];
7497
7498 u8 reserved_at_140[0x100];
7499
7500 u8 time_stamp_high[0x20];
7501
7502 u8 time_stamp_low[0x20];
7503
7504 u8 accumulators_period[0x20];
7505
7506 u8 np_ecn_marked_roce_packets_high[0x20];
7507
7508 u8 np_ecn_marked_roce_packets_low[0x20];
7509
7510 u8 np_cnp_sent_high[0x20];
7511
7512 u8 np_cnp_sent_low[0x20];
7513
7514 u8 reserved_at_320[0x560];
7515};
7516
7517struct mlx5_ifc_query_cong_statistics_in_bits {
7518 u8 opcode[0x10];
7519 u8 reserved_at_10[0x10];
7520
7521 u8 reserved_at_20[0x10];
7522 u8 op_mod[0x10];
7523
7524 u8 clear[0x1];
7525 u8 reserved_at_41[0x1f];
7526
7527 u8 reserved_at_60[0x20];
7528};
7529
7530struct mlx5_ifc_query_cong_params_out_bits {
7531 u8 status[0x8];
7532 u8 reserved_at_8[0x18];
7533
7534 u8 syndrome[0x20];
7535
7536 u8 reserved_at_40[0x40];
7537
7538 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7539};
7540
7541struct mlx5_ifc_query_cong_params_in_bits {
7542 u8 opcode[0x10];
7543 u8 reserved_at_10[0x10];
7544
7545 u8 reserved_at_20[0x10];
7546 u8 op_mod[0x10];
7547
7548 u8 reserved_at_40[0x1c];
7549 u8 cong_protocol[0x4];
7550
7551 u8 reserved_at_60[0x20];
7552};
7553
7554struct mlx5_ifc_query_adapter_out_bits {
7555 u8 status[0x8];
7556 u8 reserved_at_8[0x18];
7557
7558 u8 syndrome[0x20];
7559
7560 u8 reserved_at_40[0x40];
7561
7562 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
7563};
7564
7565struct mlx5_ifc_query_adapter_in_bits {
7566 u8 opcode[0x10];
7567 u8 reserved_at_10[0x10];
7568
7569 u8 reserved_at_20[0x10];
7570 u8 op_mod[0x10];
7571
7572 u8 reserved_at_40[0x40];
7573};
7574
7575struct mlx5_ifc_function_vhca_rid_info_reg_bits {
7576 u8 host_number[0x8];
7577 u8 host_pci_device_function[0x8];
7578 u8 host_pci_bus[0x8];
7579 u8 reserved_at_18[0x3];
7580 u8 pci_bus_assigned[0x1];
7581 u8 function_type[0x4];
7582
7583 u8 parent_pci_device_function[0x8];
7584 u8 parent_pci_bus[0x8];
7585 u8 vhca_id[0x10];
7586
7587 u8 reserved_at_40[0x10];
7588 u8 function_id[0x10];
7589
7590 u8 reserved_at_60[0x20];
7591};
7592
7593struct mlx5_ifc_delegated_function_vhca_rid_info_bits {
7594 struct mlx5_ifc_function_vhca_rid_info_reg_bits function_vhca_rid_info;
7595
7596 u8 reserved_at_80[0x18];
7597 u8 manage_profile[0x8];
7598
7599 u8 reserved_at_a0[0x60];
7600};
7601
7602struct mlx5_ifc_query_delegated_vhca_out_bits {
7603 u8 status[0x8];
7604 u8 reserved_at_8[0x18];
7605
7606 u8 syndrome[0x20];
7607
7608 u8 reserved_at_40[0x20];
7609
7610 u8 reserved_at_60[0x10];
7611 u8 functions_count[0x10];
7612
7613 u8 reserved_at_80[0x80];
7614
7615 struct mlx5_ifc_delegated_function_vhca_rid_info_bits
7616 delegated_function_vhca_rid_info[];
7617};
7618
7619struct mlx5_ifc_query_delegated_vhca_in_bits {
7620 u8 opcode[0x10];
7621 u8 uid[0x10];
7622
7623 u8 reserved_at_20[0x10];
7624 u8 op_mod[0x10];
7625
7626 u8 reserved_at_40[0x40];
7627};
7628
7629struct mlx5_ifc_create_esw_vport_out_bits {
7630 u8 status[0x8];
7631 u8 reserved_at_8[0x18];
7632
7633 u8 syndrome[0x20];
7634
7635 u8 reserved_at_40[0x20];
7636
7637 u8 reserved_at_60[0x10];
7638 u8 vport_num[0x10];
7639};
7640
7641struct mlx5_ifc_create_esw_vport_in_bits {
7642 u8 opcode[0x10];
7643 u8 reserved_at_10[0x10];
7644
7645 u8 reserved_at_20[0x10];
7646 u8 op_mod[0x10];
7647
7648 u8 reserved_at_40[0x10];
7649 u8 managed_vhca_id[0x10];
7650
7651 u8 reserved_at_60[0x20];
7652};
7653
7654struct mlx5_ifc_qp_2rst_out_bits {
7655 u8 status[0x8];
7656 u8 reserved_at_8[0x18];
7657
7658 u8 syndrome[0x20];
7659
7660 u8 reserved_at_40[0x40];
7661};
7662
7663struct mlx5_ifc_qp_2rst_in_bits {
7664 u8 opcode[0x10];
7665 u8 uid[0x10];
7666
7667 u8 reserved_at_20[0x10];
7668 u8 op_mod[0x10];
7669
7670 u8 reserved_at_40[0x8];
7671 u8 qpn[0x18];
7672
7673 u8 reserved_at_60[0x20];
7674};
7675
7676struct mlx5_ifc_qp_2err_out_bits {
7677 u8 status[0x8];
7678 u8 reserved_at_8[0x18];
7679
7680 u8 syndrome[0x20];
7681
7682 u8 reserved_at_40[0x40];
7683};
7684
7685struct mlx5_ifc_qp_2err_in_bits {
7686 u8 opcode[0x10];
7687 u8 uid[0x10];
7688
7689 u8 reserved_at_20[0x10];
7690 u8 op_mod[0x10];
7691
7692 u8 reserved_at_40[0x8];
7693 u8 qpn[0x18];
7694
7695 u8 reserved_at_60[0x20];
7696};
7697
7698struct mlx5_ifc_trans_page_fault_info_bits {
7699 u8 error[0x1];
7700 u8 reserved_at_1[0x4];
7701 u8 page_fault_type[0x3];
7702 u8 wq_number[0x18];
7703
7704 u8 reserved_at_20[0x8];
7705 u8 fault_token[0x18];
7706};
7707
7708struct mlx5_ifc_mem_page_fault_info_bits {
7709 u8 error[0x1];
7710 u8 reserved_at_1[0xf];
7711 u8 fault_token_47_32[0x10];
7712
7713 u8 fault_token_31_0[0x20];
7714};
7715
7716union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits {
7717 struct mlx5_ifc_trans_page_fault_info_bits trans_page_fault_info;
7718 struct mlx5_ifc_mem_page_fault_info_bits mem_page_fault_info;
7719 u8 reserved_at_0[0x40];
7720};
7721
7722struct mlx5_ifc_page_fault_resume_out_bits {
7723 u8 status[0x8];
7724 u8 reserved_at_8[0x18];
7725
7726 u8 syndrome[0x20];
7727
7728 u8 reserved_at_40[0x40];
7729};
7730
7731struct mlx5_ifc_page_fault_resume_in_bits {
7732 u8 opcode[0x10];
7733 u8 reserved_at_10[0x10];
7734
7735 u8 reserved_at_20[0x10];
7736 u8 op_mod[0x10];
7737
7738 union mlx5_ifc_page_fault_resume_in_page_fault_info_auto_bits
7739 page_fault_info;
7740};
7741
7742struct mlx5_ifc_nop_out_bits {
7743 u8 status[0x8];
7744 u8 reserved_at_8[0x18];
7745
7746 u8 syndrome[0x20];
7747
7748 u8 reserved_at_40[0x40];
7749};
7750
7751struct mlx5_ifc_nop_in_bits {
7752 u8 opcode[0x10];
7753 u8 reserved_at_10[0x10];
7754
7755 u8 reserved_at_20[0x10];
7756 u8 op_mod[0x10];
7757
7758 u8 reserved_at_40[0x40];
7759};
7760
7761struct mlx5_ifc_modify_vport_state_out_bits {
7762 u8 status[0x8];
7763 u8 reserved_at_8[0x18];
7764
7765 u8 syndrome[0x20];
7766
7767 u8 reserved_at_40[0x40];
7768};
7769
7770struct mlx5_ifc_modify_vport_state_in_bits {
7771 u8 opcode[0x10];
7772 u8 reserved_at_10[0x10];
7773
7774 u8 reserved_at_20[0x10];
7775 u8 op_mod[0x10];
7776
7777 u8 other_vport[0x1];
7778 u8 reserved_at_41[0xf];
7779 u8 vport_number[0x10];
7780
7781 u8 reserved_at_60[0x10];
7782 u8 ingress_connect[0x1];
7783 u8 egress_connect[0x1];
7784 u8 ingress_connect_valid[0x1];
7785 u8 egress_connect_valid[0x1];
7786 u8 reserved_at_74[0x4];
7787 u8 admin_state[0x4];
7788 u8 reserved_at_7c[0x4];
7789};
7790
7791struct mlx5_ifc_modify_tis_out_bits {
7792 u8 status[0x8];
7793 u8 reserved_at_8[0x18];
7794
7795 u8 syndrome[0x20];
7796
7797 u8 reserved_at_40[0x40];
7798};
7799
7800struct mlx5_ifc_modify_tis_bitmask_bits {
7801 u8 reserved_at_0[0x20];
7802
7803 u8 reserved_at_20[0x1d];
7804 u8 lag_tx_port_affinity[0x1];
7805 u8 strict_lag_tx_port_affinity[0x1];
7806 u8 prio[0x1];
7807};
7808
7809struct mlx5_ifc_modify_tis_in_bits {
7810 u8 opcode[0x10];
7811 u8 uid[0x10];
7812
7813 u8 reserved_at_20[0x10];
7814 u8 op_mod[0x10];
7815
7816 u8 reserved_at_40[0x8];
7817 u8 tisn[0x18];
7818
7819 u8 reserved_at_60[0x20];
7820
7821 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7822
7823 u8 reserved_at_c0[0x40];
7824
7825 struct mlx5_ifc_tisc_bits ctx;
7826};
7827
7828struct mlx5_ifc_modify_tir_bitmask_bits {
7829 u8 reserved_at_0[0x20];
7830
7831 u8 reserved_at_20[0x1b];
7832 u8 self_lb_en[0x1];
7833 u8 reserved_at_3c[0x1];
7834 u8 hash[0x1];
7835 u8 reserved_at_3e[0x1];
7836 u8 packet_merge[0x1];
7837};
7838
7839struct mlx5_ifc_modify_tir_out_bits {
7840 u8 status[0x8];
7841 u8 reserved_at_8[0x18];
7842
7843 u8 syndrome[0x20];
7844
7845 u8 reserved_at_40[0x40];
7846};
7847
7848struct mlx5_ifc_modify_tir_in_bits {
7849 u8 opcode[0x10];
7850 u8 uid[0x10];
7851
7852 u8 reserved_at_20[0x10];
7853 u8 op_mod[0x10];
7854
7855 u8 reserved_at_40[0x8];
7856 u8 tirn[0x18];
7857
7858 u8 reserved_at_60[0x20];
7859
7860 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7861
7862 u8 reserved_at_c0[0x40];
7863
7864 struct mlx5_ifc_tirc_bits ctx;
7865};
7866
7867struct mlx5_ifc_modify_sq_out_bits {
7868 u8 status[0x8];
7869 u8 reserved_at_8[0x18];
7870
7871 u8 syndrome[0x20];
7872
7873 u8 reserved_at_40[0x40];
7874};
7875
7876struct mlx5_ifc_modify_sq_in_bits {
7877 u8 opcode[0x10];
7878 u8 uid[0x10];
7879
7880 u8 reserved_at_20[0x10];
7881 u8 op_mod[0x10];
7882
7883 u8 sq_state[0x4];
7884 u8 reserved_at_44[0x4];
7885 u8 sqn[0x18];
7886
7887 u8 reserved_at_60[0x20];
7888
7889 u8 modify_bitmask[0x40];
7890
7891 u8 reserved_at_c0[0x40];
7892
7893 struct mlx5_ifc_sqc_bits ctx;
7894};
7895
7896struct mlx5_ifc_modify_scheduling_element_out_bits {
7897 u8 status[0x8];
7898 u8 reserved_at_8[0x18];
7899
7900 u8 syndrome[0x20];
7901
7902 u8 reserved_at_40[0x1c0];
7903};
7904
7905enum {
7906 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7907 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7908};
7909
7910struct mlx5_ifc_modify_scheduling_element_in_bits {
7911 u8 opcode[0x10];
7912 u8 reserved_at_10[0x10];
7913
7914 u8 reserved_at_20[0x10];
7915 u8 op_mod[0x10];
7916
7917 u8 scheduling_hierarchy[0x8];
7918 u8 reserved_at_48[0x18];
7919
7920 u8 scheduling_element_id[0x20];
7921
7922 u8 reserved_at_80[0x20];
7923
7924 u8 modify_bitmask[0x20];
7925
7926 u8 reserved_at_c0[0x40];
7927
7928 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7929
7930 u8 reserved_at_300[0x100];
7931};
7932
7933struct mlx5_ifc_modify_rqt_out_bits {
7934 u8 status[0x8];
7935 u8 reserved_at_8[0x18];
7936
7937 u8 syndrome[0x20];
7938
7939 u8 reserved_at_40[0x40];
7940};
7941
7942struct mlx5_ifc_rqt_bitmask_bits {
7943 u8 reserved_at_0[0x20];
7944
7945 u8 reserved_at_20[0x1f];
7946 u8 rqn_list[0x1];
7947};
7948
7949struct mlx5_ifc_modify_rqt_in_bits {
7950 u8 opcode[0x10];
7951 u8 uid[0x10];
7952
7953 u8 reserved_at_20[0x10];
7954 u8 op_mod[0x10];
7955
7956 u8 reserved_at_40[0x8];
7957 u8 rqtn[0x18];
7958
7959 u8 reserved_at_60[0x20];
7960
7961 struct mlx5_ifc_rqt_bitmask_bits bitmask;
7962
7963 u8 reserved_at_c0[0x40];
7964
7965 struct mlx5_ifc_rqtc_bits ctx;
7966};
7967
7968struct mlx5_ifc_modify_rq_out_bits {
7969 u8 status[0x8];
7970 u8 reserved_at_8[0x18];
7971
7972 u8 syndrome[0x20];
7973
7974 u8 reserved_at_40[0x40];
7975};
7976
7977enum {
7978 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7979 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7980 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7981};
7982
7983struct mlx5_ifc_modify_rq_in_bits {
7984 u8 opcode[0x10];
7985 u8 uid[0x10];
7986
7987 u8 reserved_at_20[0x10];
7988 u8 op_mod[0x10];
7989
7990 u8 rq_state[0x4];
7991 u8 reserved_at_44[0x4];
7992 u8 rqn[0x18];
7993
7994 u8 reserved_at_60[0x20];
7995
7996 u8 modify_bitmask[0x40];
7997
7998 u8 reserved_at_c0[0x40];
7999
8000 struct mlx5_ifc_rqc_bits ctx;
8001};
8002
8003struct mlx5_ifc_modify_rmp_out_bits {
8004 u8 status[0x8];
8005 u8 reserved_at_8[0x18];
8006
8007 u8 syndrome[0x20];
8008
8009 u8 reserved_at_40[0x40];
8010};
8011
8012struct mlx5_ifc_rmp_bitmask_bits {
8013 u8 reserved_at_0[0x20];
8014
8015 u8 reserved_at_20[0x1f];
8016 u8 lwm[0x1];
8017};
8018
8019struct mlx5_ifc_modify_rmp_in_bits {
8020 u8 opcode[0x10];
8021 u8 uid[0x10];
8022
8023 u8 reserved_at_20[0x10];
8024 u8 op_mod[0x10];
8025
8026 u8 rmp_state[0x4];
8027 u8 reserved_at_44[0x4];
8028 u8 rmpn[0x18];
8029
8030 u8 reserved_at_60[0x20];
8031
8032 struct mlx5_ifc_rmp_bitmask_bits bitmask;
8033
8034 u8 reserved_at_c0[0x40];
8035
8036 struct mlx5_ifc_rmpc_bits ctx;
8037};
8038
8039struct mlx5_ifc_modify_nic_vport_context_out_bits {
8040 u8 status[0x8];
8041 u8 reserved_at_8[0x18];
8042
8043 u8 syndrome[0x20];
8044
8045 u8 reserved_at_40[0x40];
8046};
8047
8048struct mlx5_ifc_modify_nic_vport_field_select_bits {
8049 u8 reserved_at_0[0x12];
8050 u8 affiliation[0x1];
8051 u8 reserved_at_13[0x1];
8052 u8 disable_uc_local_lb[0x1];
8053 u8 disable_mc_local_lb[0x1];
8054 u8 node_guid[0x1];
8055 u8 port_guid[0x1];
8056 u8 min_inline[0x1];
8057 u8 mtu[0x1];
8058 u8 change_event[0x1];
8059 u8 promisc[0x1];
8060 u8 permanent_address[0x1];
8061 u8 addresses_list[0x1];
8062 u8 roce_en[0x1];
8063 u8 reserved_at_1f[0x1];
8064};
8065
8066struct mlx5_ifc_modify_nic_vport_context_in_bits {
8067 u8 opcode[0x10];
8068 u8 reserved_at_10[0x10];
8069
8070 u8 reserved_at_20[0x10];
8071 u8 op_mod[0x10];
8072
8073 u8 other_vport[0x1];
8074 u8 reserved_at_41[0xf];
8075 u8 vport_number[0x10];
8076
8077 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
8078
8079 u8 reserved_at_80[0x780];
8080
8081 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
8082};
8083
8084struct mlx5_ifc_modify_hca_vport_context_out_bits {
8085 u8 status[0x8];
8086 u8 reserved_at_8[0x18];
8087
8088 u8 syndrome[0x20];
8089
8090 u8 reserved_at_40[0x40];
8091};
8092
8093struct mlx5_ifc_modify_hca_vport_context_in_bits {
8094 u8 opcode[0x10];
8095 u8 reserved_at_10[0x10];
8096
8097 u8 reserved_at_20[0x10];
8098 u8 op_mod[0x10];
8099
8100 u8 other_vport[0x1];
8101 u8 reserved_at_41[0xb];
8102 u8 port_num[0x4];
8103 u8 vport_number[0x10];
8104
8105 u8 reserved_at_60[0x20];
8106
8107 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
8108};
8109
8110struct mlx5_ifc_modify_cq_out_bits {
8111 u8 status[0x8];
8112 u8 reserved_at_8[0x18];
8113
8114 u8 syndrome[0x20];
8115
8116 u8 reserved_at_40[0x40];
8117};
8118
8119enum {
8120 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
8121 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
8122};
8123
8124struct mlx5_ifc_modify_cq_in_bits {
8125 u8 opcode[0x10];
8126 u8 uid[0x10];
8127
8128 u8 reserved_at_20[0x10];
8129 u8 op_mod[0x10];
8130
8131 u8 reserved_at_40[0x8];
8132 u8 cqn[0x18];
8133
8134 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
8135
8136 struct mlx5_ifc_cqc_bits cq_context;
8137
8138 u8 reserved_at_280[0x60];
8139
8140 u8 cq_umem_valid[0x1];
8141 u8 reserved_at_2e1[0x1f];
8142
8143 u8 reserved_at_300[0x580];
8144
8145 u8 pas[][0x40];
8146};
8147
8148struct mlx5_ifc_modify_cong_status_out_bits {
8149 u8 status[0x8];
8150 u8 reserved_at_8[0x18];
8151
8152 u8 syndrome[0x20];
8153
8154 u8 reserved_at_40[0x40];
8155};
8156
8157struct mlx5_ifc_modify_cong_status_in_bits {
8158 u8 opcode[0x10];
8159 u8 reserved_at_10[0x10];
8160
8161 u8 reserved_at_20[0x10];
8162 u8 op_mod[0x10];
8163
8164 u8 reserved_at_40[0x18];
8165 u8 priority[0x4];
8166 u8 cong_protocol[0x4];
8167
8168 u8 enable[0x1];
8169 u8 tag_enable[0x1];
8170 u8 reserved_at_62[0x1e];
8171};
8172
8173struct mlx5_ifc_modify_cong_params_out_bits {
8174 u8 status[0x8];
8175 u8 reserved_at_8[0x18];
8176
8177 u8 syndrome[0x20];
8178
8179 u8 reserved_at_40[0x40];
8180};
8181
8182struct mlx5_ifc_modify_cong_params_in_bits {
8183 u8 opcode[0x10];
8184 u8 reserved_at_10[0x10];
8185
8186 u8 reserved_at_20[0x10];
8187 u8 op_mod[0x10];
8188
8189 u8 reserved_at_40[0x1c];
8190 u8 cong_protocol[0x4];
8191
8192 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
8193
8194 u8 reserved_at_80[0x80];
8195
8196 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
8197};
8198
8199struct mlx5_ifc_manage_pages_out_bits {
8200 u8 status[0x8];
8201 u8 reserved_at_8[0x18];
8202
8203 u8 syndrome[0x20];
8204
8205 u8 output_num_entries[0x20];
8206
8207 u8 reserved_at_60[0x20];
8208
8209 u8 pas[][0x40];
8210};
8211
8212enum {
8213 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
8214 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
8215 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
8216};
8217
8218struct mlx5_ifc_manage_pages_in_bits {
8219 u8 opcode[0x10];
8220 u8 reserved_at_10[0x10];
8221
8222 u8 reserved_at_20[0x10];
8223 u8 op_mod[0x10];
8224
8225 u8 embedded_cpu_function[0x1];
8226 u8 reserved_at_41[0xf];
8227 u8 function_id[0x10];
8228
8229 u8 input_num_entries[0x20];
8230
8231 u8 pas[][0x40];
8232};
8233
8234struct mlx5_ifc_mad_ifc_out_bits {
8235 u8 status[0x8];
8236 u8 reserved_at_8[0x18];
8237
8238 u8 syndrome[0x20];
8239
8240 u8 reserved_at_40[0x40];
8241
8242 u8 response_mad_packet[256][0x8];
8243};
8244
8245struct mlx5_ifc_mad_ifc_in_bits {
8246 u8 opcode[0x10];
8247 u8 reserved_at_10[0x10];
8248
8249 u8 reserved_at_20[0x10];
8250 u8 op_mod[0x10];
8251
8252 u8 remote_lid[0x10];
8253 u8 plane_index[0x8];
8254 u8 port[0x8];
8255
8256 u8 reserved_at_60[0x20];
8257
8258 u8 mad[256][0x8];
8259};
8260
8261struct mlx5_ifc_init_hca_out_bits {
8262 u8 status[0x8];
8263 u8 reserved_at_8[0x18];
8264
8265 u8 syndrome[0x20];
8266
8267 u8 reserved_at_40[0x40];
8268};
8269
8270struct mlx5_ifc_init_hca_in_bits {
8271 u8 opcode[0x10];
8272 u8 reserved_at_10[0x10];
8273
8274 u8 reserved_at_20[0x10];
8275 u8 op_mod[0x10];
8276
8277 u8 reserved_at_40[0x20];
8278
8279 u8 reserved_at_60[0x2];
8280 u8 sw_vhca_id[0xe];
8281 u8 reserved_at_70[0x10];
8282
8283 u8 sw_owner_id[4][0x20];
8284};
8285
8286struct mlx5_ifc_init2rtr_qp_out_bits {
8287 u8 status[0x8];
8288 u8 reserved_at_8[0x18];
8289
8290 u8 syndrome[0x20];
8291
8292 u8 reserved_at_40[0x20];
8293 u8 ece[0x20];
8294};
8295
8296struct mlx5_ifc_init2rtr_qp_in_bits {
8297 u8 opcode[0x10];
8298 u8 uid[0x10];
8299
8300 u8 reserved_at_20[0x10];
8301 u8 op_mod[0x10];
8302
8303 u8 reserved_at_40[0x8];
8304 u8 qpn[0x18];
8305
8306 u8 reserved_at_60[0x20];
8307
8308 u8 opt_param_mask[0x20];
8309
8310 u8 ece[0x20];
8311
8312 struct mlx5_ifc_qpc_bits qpc;
8313
8314 u8 reserved_at_800[0x80];
8315};
8316
8317struct mlx5_ifc_init2init_qp_out_bits {
8318 u8 status[0x8];
8319 u8 reserved_at_8[0x18];
8320
8321 u8 syndrome[0x20];
8322
8323 u8 reserved_at_40[0x20];
8324 u8 ece[0x20];
8325};
8326
8327struct mlx5_ifc_init2init_qp_in_bits {
8328 u8 opcode[0x10];
8329 u8 uid[0x10];
8330
8331 u8 reserved_at_20[0x10];
8332 u8 op_mod[0x10];
8333
8334 u8 reserved_at_40[0x8];
8335 u8 qpn[0x18];
8336
8337 u8 reserved_at_60[0x20];
8338
8339 u8 opt_param_mask[0x20];
8340
8341 u8 ece[0x20];
8342
8343 struct mlx5_ifc_qpc_bits qpc;
8344
8345 u8 reserved_at_800[0x80];
8346};
8347
8348struct mlx5_ifc_get_dropped_packet_log_out_bits {
8349 u8 status[0x8];
8350 u8 reserved_at_8[0x18];
8351
8352 u8 syndrome[0x20];
8353
8354 u8 reserved_at_40[0x40];
8355
8356 u8 packet_headers_log[128][0x8];
8357
8358 u8 packet_syndrome[64][0x8];
8359};
8360
8361struct mlx5_ifc_get_dropped_packet_log_in_bits {
8362 u8 opcode[0x10];
8363 u8 reserved_at_10[0x10];
8364
8365 u8 reserved_at_20[0x10];
8366 u8 op_mod[0x10];
8367
8368 u8 reserved_at_40[0x40];
8369};
8370
8371struct mlx5_ifc_gen_eqe_in_bits {
8372 u8 opcode[0x10];
8373 u8 reserved_at_10[0x10];
8374
8375 u8 reserved_at_20[0x10];
8376 u8 op_mod[0x10];
8377
8378 u8 reserved_at_40[0x18];
8379 u8 eq_number[0x8];
8380
8381 u8 reserved_at_60[0x20];
8382
8383 u8 eqe[64][0x8];
8384};
8385
8386struct mlx5_ifc_gen_eq_out_bits {
8387 u8 status[0x8];
8388 u8 reserved_at_8[0x18];
8389
8390 u8 syndrome[0x20];
8391
8392 u8 reserved_at_40[0x40];
8393};
8394
8395struct mlx5_ifc_enable_hca_out_bits {
8396 u8 status[0x8];
8397 u8 reserved_at_8[0x18];
8398
8399 u8 syndrome[0x20];
8400
8401 u8 reserved_at_40[0x20];
8402};
8403
8404struct mlx5_ifc_enable_hca_in_bits {
8405 u8 opcode[0x10];
8406 u8 reserved_at_10[0x10];
8407
8408 u8 reserved_at_20[0x10];
8409 u8 op_mod[0x10];
8410
8411 u8 embedded_cpu_function[0x1];
8412 u8 reserved_at_41[0xf];
8413 u8 function_id[0x10];
8414
8415 u8 reserved_at_60[0x20];
8416};
8417
8418struct mlx5_ifc_drain_dct_out_bits {
8419 u8 status[0x8];
8420 u8 reserved_at_8[0x18];
8421
8422 u8 syndrome[0x20];
8423
8424 u8 reserved_at_40[0x40];
8425};
8426
8427struct mlx5_ifc_drain_dct_in_bits {
8428 u8 opcode[0x10];
8429 u8 uid[0x10];
8430
8431 u8 reserved_at_20[0x10];
8432 u8 op_mod[0x10];
8433
8434 u8 reserved_at_40[0x8];
8435 u8 dctn[0x18];
8436
8437 u8 reserved_at_60[0x20];
8438};
8439
8440struct mlx5_ifc_disable_hca_out_bits {
8441 u8 status[0x8];
8442 u8 reserved_at_8[0x18];
8443
8444 u8 syndrome[0x20];
8445
8446 u8 reserved_at_40[0x20];
8447};
8448
8449struct mlx5_ifc_disable_hca_in_bits {
8450 u8 opcode[0x10];
8451 u8 reserved_at_10[0x10];
8452
8453 u8 reserved_at_20[0x10];
8454 u8 op_mod[0x10];
8455
8456 u8 embedded_cpu_function[0x1];
8457 u8 reserved_at_41[0xf];
8458 u8 function_id[0x10];
8459
8460 u8 reserved_at_60[0x20];
8461};
8462
8463struct mlx5_ifc_detach_from_mcg_out_bits {
8464 u8 status[0x8];
8465 u8 reserved_at_8[0x18];
8466
8467 u8 syndrome[0x20];
8468
8469 u8 reserved_at_40[0x40];
8470};
8471
8472struct mlx5_ifc_detach_from_mcg_in_bits {
8473 u8 opcode[0x10];
8474 u8 uid[0x10];
8475
8476 u8 reserved_at_20[0x10];
8477 u8 op_mod[0x10];
8478
8479 u8 reserved_at_40[0x8];
8480 u8 qpn[0x18];
8481
8482 u8 reserved_at_60[0x20];
8483
8484 u8 multicast_gid[16][0x8];
8485};
8486
8487struct mlx5_ifc_destroy_xrq_out_bits {
8488 u8 status[0x8];
8489 u8 reserved_at_8[0x18];
8490
8491 u8 syndrome[0x20];
8492
8493 u8 reserved_at_40[0x40];
8494};
8495
8496struct mlx5_ifc_destroy_xrq_in_bits {
8497 u8 opcode[0x10];
8498 u8 uid[0x10];
8499
8500 u8 reserved_at_20[0x10];
8501 u8 op_mod[0x10];
8502
8503 u8 reserved_at_40[0x8];
8504 u8 xrqn[0x18];
8505
8506 u8 reserved_at_60[0x20];
8507};
8508
8509struct mlx5_ifc_destroy_xrc_srq_out_bits {
8510 u8 status[0x8];
8511 u8 reserved_at_8[0x18];
8512
8513 u8 syndrome[0x20];
8514
8515 u8 reserved_at_40[0x40];
8516};
8517
8518struct mlx5_ifc_destroy_xrc_srq_in_bits {
8519 u8 opcode[0x10];
8520 u8 uid[0x10];
8521
8522 u8 reserved_at_20[0x10];
8523 u8 op_mod[0x10];
8524
8525 u8 reserved_at_40[0x8];
8526 u8 xrc_srqn[0x18];
8527
8528 u8 reserved_at_60[0x20];
8529};
8530
8531struct mlx5_ifc_destroy_tis_out_bits {
8532 u8 status[0x8];
8533 u8 reserved_at_8[0x18];
8534
8535 u8 syndrome[0x20];
8536
8537 u8 reserved_at_40[0x40];
8538};
8539
8540struct mlx5_ifc_destroy_tis_in_bits {
8541 u8 opcode[0x10];
8542 u8 uid[0x10];
8543
8544 u8 reserved_at_20[0x10];
8545 u8 op_mod[0x10];
8546
8547 u8 reserved_at_40[0x8];
8548 u8 tisn[0x18];
8549
8550 u8 reserved_at_60[0x20];
8551};
8552
8553struct mlx5_ifc_destroy_tir_out_bits {
8554 u8 status[0x8];
8555 u8 reserved_at_8[0x18];
8556
8557 u8 syndrome[0x20];
8558
8559 u8 reserved_at_40[0x40];
8560};
8561
8562struct mlx5_ifc_destroy_tir_in_bits {
8563 u8 opcode[0x10];
8564 u8 uid[0x10];
8565
8566 u8 reserved_at_20[0x10];
8567 u8 op_mod[0x10];
8568
8569 u8 reserved_at_40[0x8];
8570 u8 tirn[0x18];
8571
8572 u8 reserved_at_60[0x20];
8573};
8574
8575struct mlx5_ifc_destroy_srq_out_bits {
8576 u8 status[0x8];
8577 u8 reserved_at_8[0x18];
8578
8579 u8 syndrome[0x20];
8580
8581 u8 reserved_at_40[0x40];
8582};
8583
8584struct mlx5_ifc_destroy_srq_in_bits {
8585 u8 opcode[0x10];
8586 u8 uid[0x10];
8587
8588 u8 reserved_at_20[0x10];
8589 u8 op_mod[0x10];
8590
8591 u8 reserved_at_40[0x8];
8592 u8 srqn[0x18];
8593
8594 u8 reserved_at_60[0x20];
8595};
8596
8597struct mlx5_ifc_destroy_sq_out_bits {
8598 u8 status[0x8];
8599 u8 reserved_at_8[0x18];
8600
8601 u8 syndrome[0x20];
8602
8603 u8 reserved_at_40[0x40];
8604};
8605
8606struct mlx5_ifc_destroy_sq_in_bits {
8607 u8 opcode[0x10];
8608 u8 uid[0x10];
8609
8610 u8 reserved_at_20[0x10];
8611 u8 op_mod[0x10];
8612
8613 u8 reserved_at_40[0x8];
8614 u8 sqn[0x18];
8615
8616 u8 reserved_at_60[0x20];
8617};
8618
8619struct mlx5_ifc_destroy_scheduling_element_out_bits {
8620 u8 status[0x8];
8621 u8 reserved_at_8[0x18];
8622
8623 u8 syndrome[0x20];
8624
8625 u8 reserved_at_40[0x1c0];
8626};
8627
8628struct mlx5_ifc_destroy_scheduling_element_in_bits {
8629 u8 opcode[0x10];
8630 u8 reserved_at_10[0x10];
8631
8632 u8 reserved_at_20[0x10];
8633 u8 op_mod[0x10];
8634
8635 u8 scheduling_hierarchy[0x8];
8636 u8 reserved_at_48[0x18];
8637
8638 u8 scheduling_element_id[0x20];
8639
8640 u8 reserved_at_80[0x180];
8641};
8642
8643struct mlx5_ifc_destroy_rqt_out_bits {
8644 u8 status[0x8];
8645 u8 reserved_at_8[0x18];
8646
8647 u8 syndrome[0x20];
8648
8649 u8 reserved_at_40[0x40];
8650};
8651
8652struct mlx5_ifc_destroy_rqt_in_bits {
8653 u8 opcode[0x10];
8654 u8 uid[0x10];
8655
8656 u8 reserved_at_20[0x10];
8657 u8 op_mod[0x10];
8658
8659 u8 reserved_at_40[0x8];
8660 u8 rqtn[0x18];
8661
8662 u8 reserved_at_60[0x20];
8663};
8664
8665struct mlx5_ifc_destroy_rq_out_bits {
8666 u8 status[0x8];
8667 u8 reserved_at_8[0x18];
8668
8669 u8 syndrome[0x20];
8670
8671 u8 reserved_at_40[0x40];
8672};
8673
8674struct mlx5_ifc_destroy_rq_in_bits {
8675 u8 opcode[0x10];
8676 u8 uid[0x10];
8677
8678 u8 reserved_at_20[0x10];
8679 u8 op_mod[0x10];
8680
8681 u8 reserved_at_40[0x8];
8682 u8 rqn[0x18];
8683
8684 u8 reserved_at_60[0x20];
8685};
8686
8687struct mlx5_ifc_set_delay_drop_params_in_bits {
8688 u8 opcode[0x10];
8689 u8 reserved_at_10[0x10];
8690
8691 u8 reserved_at_20[0x10];
8692 u8 op_mod[0x10];
8693
8694 u8 reserved_at_40[0x20];
8695
8696 u8 reserved_at_60[0x10];
8697 u8 delay_drop_timeout[0x10];
8698};
8699
8700struct mlx5_ifc_set_delay_drop_params_out_bits {
8701 u8 status[0x8];
8702 u8 reserved_at_8[0x18];
8703
8704 u8 syndrome[0x20];
8705
8706 u8 reserved_at_40[0x40];
8707};
8708
8709struct mlx5_ifc_destroy_rmp_out_bits {
8710 u8 status[0x8];
8711 u8 reserved_at_8[0x18];
8712
8713 u8 syndrome[0x20];
8714
8715 u8 reserved_at_40[0x40];
8716};
8717
8718struct mlx5_ifc_destroy_rmp_in_bits {
8719 u8 opcode[0x10];
8720 u8 uid[0x10];
8721
8722 u8 reserved_at_20[0x10];
8723 u8 op_mod[0x10];
8724
8725 u8 reserved_at_40[0x8];
8726 u8 rmpn[0x18];
8727
8728 u8 reserved_at_60[0x20];
8729};
8730
8731struct mlx5_ifc_destroy_qp_out_bits {
8732 u8 status[0x8];
8733 u8 reserved_at_8[0x18];
8734
8735 u8 syndrome[0x20];
8736
8737 u8 reserved_at_40[0x40];
8738};
8739
8740struct mlx5_ifc_destroy_qp_in_bits {
8741 u8 opcode[0x10];
8742 u8 uid[0x10];
8743
8744 u8 reserved_at_20[0x10];
8745 u8 op_mod[0x10];
8746
8747 u8 reserved_at_40[0x8];
8748 u8 qpn[0x18];
8749
8750 u8 reserved_at_60[0x20];
8751};
8752
8753struct mlx5_ifc_destroy_psv_out_bits {
8754 u8 status[0x8];
8755 u8 reserved_at_8[0x18];
8756
8757 u8 syndrome[0x20];
8758
8759 u8 reserved_at_40[0x40];
8760};
8761
8762struct mlx5_ifc_destroy_psv_in_bits {
8763 u8 opcode[0x10];
8764 u8 reserved_at_10[0x10];
8765
8766 u8 reserved_at_20[0x10];
8767 u8 op_mod[0x10];
8768
8769 u8 reserved_at_40[0x8];
8770 u8 psvn[0x18];
8771
8772 u8 reserved_at_60[0x20];
8773};
8774
8775struct mlx5_ifc_destroy_mkey_out_bits {
8776 u8 status[0x8];
8777 u8 reserved_at_8[0x18];
8778
8779 u8 syndrome[0x20];
8780
8781 u8 reserved_at_40[0x40];
8782};
8783
8784struct mlx5_ifc_destroy_mkey_in_bits {
8785 u8 opcode[0x10];
8786 u8 uid[0x10];
8787
8788 u8 reserved_at_20[0x10];
8789 u8 op_mod[0x10];
8790
8791 u8 reserved_at_40[0x8];
8792 u8 mkey_index[0x18];
8793
8794 u8 reserved_at_60[0x20];
8795};
8796
8797struct mlx5_ifc_destroy_flow_table_out_bits {
8798 u8 status[0x8];
8799 u8 reserved_at_8[0x18];
8800
8801 u8 syndrome[0x20];
8802
8803 u8 reserved_at_40[0x40];
8804};
8805
8806struct mlx5_ifc_destroy_flow_table_in_bits {
8807 u8 opcode[0x10];
8808 u8 reserved_at_10[0x10];
8809
8810 u8 reserved_at_20[0x10];
8811 u8 op_mod[0x10];
8812
8813 u8 other_vport[0x1];
8814 u8 other_eswitch[0x1];
8815 u8 reserved_at_42[0xe];
8816 u8 vport_number[0x10];
8817
8818 u8 reserved_at_60[0x20];
8819
8820 u8 table_type[0x8];
8821 u8 reserved_at_88[0x8];
8822 u8 eswitch_owner_vhca_id[0x10];
8823
8824 u8 reserved_at_a0[0x8];
8825 u8 table_id[0x18];
8826
8827 u8 reserved_at_c0[0x140];
8828};
8829
8830struct mlx5_ifc_destroy_flow_group_out_bits {
8831 u8 status[0x8];
8832 u8 reserved_at_8[0x18];
8833
8834 u8 syndrome[0x20];
8835
8836 u8 reserved_at_40[0x40];
8837};
8838
8839struct mlx5_ifc_destroy_flow_group_in_bits {
8840 u8 opcode[0x10];
8841 u8 reserved_at_10[0x10];
8842
8843 u8 reserved_at_20[0x10];
8844 u8 op_mod[0x10];
8845
8846 u8 other_vport[0x1];
8847 u8 other_eswitch[0x1];
8848 u8 reserved_at_42[0xe];
8849 u8 vport_number[0x10];
8850
8851 u8 reserved_at_60[0x20];
8852
8853 u8 table_type[0x8];
8854 u8 reserved_at_88[0x8];
8855 u8 eswitch_owner_vhca_id[0x10];
8856
8857 u8 reserved_at_a0[0x8];
8858 u8 table_id[0x18];
8859
8860 u8 group_id[0x20];
8861
8862 u8 reserved_at_e0[0x120];
8863};
8864
8865struct mlx5_ifc_destroy_eq_out_bits {
8866 u8 status[0x8];
8867 u8 reserved_at_8[0x18];
8868
8869 u8 syndrome[0x20];
8870
8871 u8 reserved_at_40[0x40];
8872};
8873
8874struct mlx5_ifc_destroy_eq_in_bits {
8875 u8 opcode[0x10];
8876 u8 reserved_at_10[0x10];
8877
8878 u8 reserved_at_20[0x10];
8879 u8 op_mod[0x10];
8880
8881 u8 reserved_at_40[0x18];
8882 u8 eq_number[0x8];
8883
8884 u8 reserved_at_60[0x20];
8885};
8886
8887struct mlx5_ifc_destroy_dct_out_bits {
8888 u8 status[0x8];
8889 u8 reserved_at_8[0x18];
8890
8891 u8 syndrome[0x20];
8892
8893 u8 reserved_at_40[0x40];
8894};
8895
8896struct mlx5_ifc_destroy_dct_in_bits {
8897 u8 opcode[0x10];
8898 u8 uid[0x10];
8899
8900 u8 reserved_at_20[0x10];
8901 u8 op_mod[0x10];
8902
8903 u8 reserved_at_40[0x8];
8904 u8 dctn[0x18];
8905
8906 u8 reserved_at_60[0x20];
8907};
8908
8909struct mlx5_ifc_destroy_cq_out_bits {
8910 u8 status[0x8];
8911 u8 reserved_at_8[0x18];
8912
8913 u8 syndrome[0x20];
8914
8915 u8 reserved_at_40[0x40];
8916};
8917
8918struct mlx5_ifc_destroy_cq_in_bits {
8919 u8 opcode[0x10];
8920 u8 uid[0x10];
8921
8922 u8 reserved_at_20[0x10];
8923 u8 op_mod[0x10];
8924
8925 u8 reserved_at_40[0x8];
8926 u8 cqn[0x18];
8927
8928 u8 reserved_at_60[0x20];
8929};
8930
8931struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8932 u8 status[0x8];
8933 u8 reserved_at_8[0x18];
8934
8935 u8 syndrome[0x20];
8936
8937 u8 reserved_at_40[0x40];
8938};
8939
8940struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8941 u8 opcode[0x10];
8942 u8 reserved_at_10[0x10];
8943
8944 u8 reserved_at_20[0x10];
8945 u8 op_mod[0x10];
8946
8947 u8 reserved_at_40[0x20];
8948
8949 u8 reserved_at_60[0x10];
8950 u8 vxlan_udp_port[0x10];
8951};
8952
8953struct mlx5_ifc_delete_l2_table_entry_out_bits {
8954 u8 status[0x8];
8955 u8 reserved_at_8[0x18];
8956
8957 u8 syndrome[0x20];
8958
8959 u8 reserved_at_40[0x40];
8960};
8961
8962struct mlx5_ifc_delete_l2_table_entry_in_bits {
8963 u8 opcode[0x10];
8964 u8 reserved_at_10[0x10];
8965
8966 u8 reserved_at_20[0x10];
8967 u8 op_mod[0x10];
8968
8969 u8 reserved_at_40[0x60];
8970
8971 u8 reserved_at_a0[0x8];
8972 u8 table_index[0x18];
8973
8974 u8 reserved_at_c0[0x140];
8975};
8976
8977struct mlx5_ifc_delete_fte_out_bits {
8978 u8 status[0x8];
8979 u8 reserved_at_8[0x18];
8980
8981 u8 syndrome[0x20];
8982
8983 u8 reserved_at_40[0x40];
8984};
8985
8986struct mlx5_ifc_delete_fte_in_bits {
8987 u8 opcode[0x10];
8988 u8 reserved_at_10[0x10];
8989
8990 u8 reserved_at_20[0x10];
8991 u8 op_mod[0x10];
8992
8993 u8 other_vport[0x1];
8994 u8 other_eswitch[0x1];
8995 u8 reserved_at_42[0xe];
8996 u8 vport_number[0x10];
8997
8998 u8 reserved_at_60[0x20];
8999
9000 u8 table_type[0x8];
9001 u8 reserved_at_88[0x8];
9002 u8 eswitch_owner_vhca_id[0x10];
9003
9004 u8 reserved_at_a0[0x8];
9005 u8 table_id[0x18];
9006
9007 u8 reserved_at_c0[0x40];
9008
9009 u8 flow_index[0x20];
9010
9011 u8 reserved_at_120[0xe0];
9012};
9013
9014struct mlx5_ifc_dealloc_xrcd_out_bits {
9015 u8 status[0x8];
9016 u8 reserved_at_8[0x18];
9017
9018 u8 syndrome[0x20];
9019
9020 u8 reserved_at_40[0x40];
9021};
9022
9023struct mlx5_ifc_dealloc_xrcd_in_bits {
9024 u8 opcode[0x10];
9025 u8 uid[0x10];
9026
9027 u8 reserved_at_20[0x10];
9028 u8 op_mod[0x10];
9029
9030 u8 reserved_at_40[0x8];
9031 u8 xrcd[0x18];
9032
9033 u8 reserved_at_60[0x20];
9034};
9035
9036struct mlx5_ifc_dealloc_uar_out_bits {
9037 u8 status[0x8];
9038 u8 reserved_at_8[0x18];
9039
9040 u8 syndrome[0x20];
9041
9042 u8 reserved_at_40[0x40];
9043};
9044
9045struct mlx5_ifc_dealloc_uar_in_bits {
9046 u8 opcode[0x10];
9047 u8 uid[0x10];
9048
9049 u8 reserved_at_20[0x10];
9050 u8 op_mod[0x10];
9051
9052 u8 reserved_at_40[0x8];
9053 u8 uar[0x18];
9054
9055 u8 reserved_at_60[0x20];
9056};
9057
9058struct mlx5_ifc_dealloc_transport_domain_out_bits {
9059 u8 status[0x8];
9060 u8 reserved_at_8[0x18];
9061
9062 u8 syndrome[0x20];
9063
9064 u8 reserved_at_40[0x40];
9065};
9066
9067struct mlx5_ifc_dealloc_transport_domain_in_bits {
9068 u8 opcode[0x10];
9069 u8 uid[0x10];
9070
9071 u8 reserved_at_20[0x10];
9072 u8 op_mod[0x10];
9073
9074 u8 reserved_at_40[0x8];
9075 u8 transport_domain[0x18];
9076
9077 u8 reserved_at_60[0x20];
9078};
9079
9080struct mlx5_ifc_dealloc_q_counter_out_bits {
9081 u8 status[0x8];
9082 u8 reserved_at_8[0x18];
9083
9084 u8 syndrome[0x20];
9085
9086 u8 reserved_at_40[0x40];
9087};
9088
9089struct mlx5_ifc_dealloc_q_counter_in_bits {
9090 u8 opcode[0x10];
9091 u8 reserved_at_10[0x10];
9092
9093 u8 reserved_at_20[0x10];
9094 u8 op_mod[0x10];
9095
9096 u8 reserved_at_40[0x18];
9097 u8 counter_set_id[0x8];
9098
9099 u8 reserved_at_60[0x20];
9100};
9101
9102struct mlx5_ifc_dealloc_pd_out_bits {
9103 u8 status[0x8];
9104 u8 reserved_at_8[0x18];
9105
9106 u8 syndrome[0x20];
9107
9108 u8 reserved_at_40[0x40];
9109};
9110
9111struct mlx5_ifc_dealloc_pd_in_bits {
9112 u8 opcode[0x10];
9113 u8 uid[0x10];
9114
9115 u8 reserved_at_20[0x10];
9116 u8 op_mod[0x10];
9117
9118 u8 reserved_at_40[0x8];
9119 u8 pd[0x18];
9120
9121 u8 reserved_at_60[0x20];
9122};
9123
9124struct mlx5_ifc_dealloc_flow_counter_out_bits {
9125 u8 status[0x8];
9126 u8 reserved_at_8[0x18];
9127
9128 u8 syndrome[0x20];
9129
9130 u8 reserved_at_40[0x40];
9131};
9132
9133struct mlx5_ifc_dealloc_flow_counter_in_bits {
9134 u8 opcode[0x10];
9135 u8 reserved_at_10[0x10];
9136
9137 u8 reserved_at_20[0x10];
9138 u8 op_mod[0x10];
9139
9140 u8 flow_counter_id[0x20];
9141
9142 u8 reserved_at_60[0x20];
9143};
9144
9145struct mlx5_ifc_create_xrq_out_bits {
9146 u8 status[0x8];
9147 u8 reserved_at_8[0x18];
9148
9149 u8 syndrome[0x20];
9150
9151 u8 reserved_at_40[0x8];
9152 u8 xrqn[0x18];
9153
9154 u8 reserved_at_60[0x20];
9155};
9156
9157struct mlx5_ifc_create_xrq_in_bits {
9158 u8 opcode[0x10];
9159 u8 uid[0x10];
9160
9161 u8 reserved_at_20[0x10];
9162 u8 op_mod[0x10];
9163
9164 u8 reserved_at_40[0x40];
9165
9166 struct mlx5_ifc_xrqc_bits xrq_context;
9167};
9168
9169struct mlx5_ifc_create_xrc_srq_out_bits {
9170 u8 status[0x8];
9171 u8 reserved_at_8[0x18];
9172
9173 u8 syndrome[0x20];
9174
9175 u8 reserved_at_40[0x8];
9176 u8 xrc_srqn[0x18];
9177
9178 u8 reserved_at_60[0x20];
9179};
9180
9181struct mlx5_ifc_create_xrc_srq_in_bits {
9182 u8 opcode[0x10];
9183 u8 uid[0x10];
9184
9185 u8 reserved_at_20[0x10];
9186 u8 op_mod[0x10];
9187
9188 u8 reserved_at_40[0x40];
9189
9190 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
9191
9192 u8 reserved_at_280[0x60];
9193
9194 u8 xrc_srq_umem_valid[0x1];
9195 u8 reserved_at_2e1[0x1f];
9196
9197 u8 reserved_at_300[0x580];
9198
9199 u8 pas[][0x40];
9200};
9201
9202struct mlx5_ifc_create_tis_out_bits {
9203 u8 status[0x8];
9204 u8 reserved_at_8[0x18];
9205
9206 u8 syndrome[0x20];
9207
9208 u8 reserved_at_40[0x8];
9209 u8 tisn[0x18];
9210
9211 u8 reserved_at_60[0x20];
9212};
9213
9214struct mlx5_ifc_create_tis_in_bits {
9215 u8 opcode[0x10];
9216 u8 uid[0x10];
9217
9218 u8 reserved_at_20[0x10];
9219 u8 op_mod[0x10];
9220
9221 u8 reserved_at_40[0xc0];
9222
9223 struct mlx5_ifc_tisc_bits ctx;
9224};
9225
9226struct mlx5_ifc_create_tir_out_bits {
9227 u8 status[0x8];
9228 u8 icm_address_63_40[0x18];
9229
9230 u8 syndrome[0x20];
9231
9232 u8 icm_address_39_32[0x8];
9233 u8 tirn[0x18];
9234
9235 u8 icm_address_31_0[0x20];
9236};
9237
9238struct mlx5_ifc_create_tir_in_bits {
9239 u8 opcode[0x10];
9240 u8 uid[0x10];
9241
9242 u8 reserved_at_20[0x10];
9243 u8 op_mod[0x10];
9244
9245 u8 reserved_at_40[0xc0];
9246
9247 struct mlx5_ifc_tirc_bits ctx;
9248};
9249
9250struct mlx5_ifc_create_srq_out_bits {
9251 u8 status[0x8];
9252 u8 reserved_at_8[0x18];
9253
9254 u8 syndrome[0x20];
9255
9256 u8 reserved_at_40[0x8];
9257 u8 srqn[0x18];
9258
9259 u8 reserved_at_60[0x20];
9260};
9261
9262struct mlx5_ifc_create_srq_in_bits {
9263 u8 opcode[0x10];
9264 u8 uid[0x10];
9265
9266 u8 reserved_at_20[0x10];
9267 u8 op_mod[0x10];
9268
9269 u8 reserved_at_40[0x40];
9270
9271 struct mlx5_ifc_srqc_bits srq_context_entry;
9272
9273 u8 reserved_at_280[0x600];
9274
9275 u8 pas[][0x40];
9276};
9277
9278struct mlx5_ifc_create_sq_out_bits {
9279 u8 status[0x8];
9280 u8 reserved_at_8[0x18];
9281
9282 u8 syndrome[0x20];
9283
9284 u8 reserved_at_40[0x8];
9285 u8 sqn[0x18];
9286
9287 u8 reserved_at_60[0x20];
9288};
9289
9290struct mlx5_ifc_create_sq_in_bits {
9291 u8 opcode[0x10];
9292 u8 uid[0x10];
9293
9294 u8 reserved_at_20[0x10];
9295 u8 op_mod[0x10];
9296
9297 u8 reserved_at_40[0xc0];
9298
9299 struct mlx5_ifc_sqc_bits ctx;
9300};
9301
9302struct mlx5_ifc_create_scheduling_element_out_bits {
9303 u8 status[0x8];
9304 u8 reserved_at_8[0x18];
9305
9306 u8 syndrome[0x20];
9307
9308 u8 reserved_at_40[0x40];
9309
9310 u8 scheduling_element_id[0x20];
9311
9312 u8 reserved_at_a0[0x160];
9313};
9314
9315struct mlx5_ifc_create_scheduling_element_in_bits {
9316 u8 opcode[0x10];
9317 u8 reserved_at_10[0x10];
9318
9319 u8 reserved_at_20[0x10];
9320 u8 op_mod[0x10];
9321
9322 u8 scheduling_hierarchy[0x8];
9323 u8 reserved_at_48[0x18];
9324
9325 u8 reserved_at_60[0xa0];
9326
9327 struct mlx5_ifc_scheduling_context_bits scheduling_context;
9328
9329 u8 reserved_at_300[0x100];
9330};
9331
9332struct mlx5_ifc_create_rqt_out_bits {
9333 u8 status[0x8];
9334 u8 reserved_at_8[0x18];
9335
9336 u8 syndrome[0x20];
9337
9338 u8 reserved_at_40[0x8];
9339 u8 rqtn[0x18];
9340
9341 u8 reserved_at_60[0x20];
9342};
9343
9344struct mlx5_ifc_create_rqt_in_bits {
9345 u8 opcode[0x10];
9346 u8 uid[0x10];
9347
9348 u8 reserved_at_20[0x10];
9349 u8 op_mod[0x10];
9350
9351 u8 reserved_at_40[0xc0];
9352
9353 struct mlx5_ifc_rqtc_bits rqt_context;
9354};
9355
9356struct mlx5_ifc_create_rq_out_bits {
9357 u8 status[0x8];
9358 u8 reserved_at_8[0x18];
9359
9360 u8 syndrome[0x20];
9361
9362 u8 reserved_at_40[0x8];
9363 u8 rqn[0x18];
9364
9365 u8 reserved_at_60[0x20];
9366};
9367
9368struct mlx5_ifc_create_rq_in_bits {
9369 u8 opcode[0x10];
9370 u8 uid[0x10];
9371
9372 u8 reserved_at_20[0x10];
9373 u8 op_mod[0x10];
9374
9375 u8 reserved_at_40[0xc0];
9376
9377 struct mlx5_ifc_rqc_bits ctx;
9378};
9379
9380struct mlx5_ifc_create_rmp_out_bits {
9381 u8 status[0x8];
9382 u8 reserved_at_8[0x18];
9383
9384 u8 syndrome[0x20];
9385
9386 u8 reserved_at_40[0x8];
9387 u8 rmpn[0x18];
9388
9389 u8 reserved_at_60[0x20];
9390};
9391
9392struct mlx5_ifc_create_rmp_in_bits {
9393 u8 opcode[0x10];
9394 u8 uid[0x10];
9395
9396 u8 reserved_at_20[0x10];
9397 u8 op_mod[0x10];
9398
9399 u8 reserved_at_40[0xc0];
9400
9401 struct mlx5_ifc_rmpc_bits ctx;
9402};
9403
9404struct mlx5_ifc_create_qp_out_bits {
9405 u8 status[0x8];
9406 u8 reserved_at_8[0x18];
9407
9408 u8 syndrome[0x20];
9409
9410 u8 reserved_at_40[0x8];
9411 u8 qpn[0x18];
9412
9413 u8 ece[0x20];
9414};
9415
9416struct mlx5_ifc_create_qp_in_bits {
9417 u8 opcode[0x10];
9418 u8 uid[0x10];
9419
9420 u8 reserved_at_20[0x10];
9421 u8 op_mod[0x10];
9422
9423 u8 qpc_ext[0x1];
9424 u8 reserved_at_41[0x7];
9425 u8 input_qpn[0x18];
9426
9427 u8 reserved_at_60[0x20];
9428 u8 opt_param_mask[0x20];
9429
9430 u8 ece[0x20];
9431
9432 struct mlx5_ifc_qpc_bits qpc;
9433
9434 u8 wq_umem_offset[0x40];
9435
9436 u8 wq_umem_id[0x20];
9437
9438 u8 wq_umem_valid[0x1];
9439 u8 reserved_at_861[0x1f];
9440
9441 u8 pas[][0x40];
9442};
9443
9444struct mlx5_ifc_create_psv_out_bits {
9445 u8 status[0x8];
9446 u8 reserved_at_8[0x18];
9447
9448 u8 syndrome[0x20];
9449
9450 u8 reserved_at_40[0x40];
9451
9452 u8 reserved_at_80[0x8];
9453 u8 psv0_index[0x18];
9454
9455 u8 reserved_at_a0[0x8];
9456 u8 psv1_index[0x18];
9457
9458 u8 reserved_at_c0[0x8];
9459 u8 psv2_index[0x18];
9460
9461 u8 reserved_at_e0[0x8];
9462 u8 psv3_index[0x18];
9463};
9464
9465struct mlx5_ifc_create_psv_in_bits {
9466 u8 opcode[0x10];
9467 u8 reserved_at_10[0x10];
9468
9469 u8 reserved_at_20[0x10];
9470 u8 op_mod[0x10];
9471
9472 u8 num_psv[0x4];
9473 u8 reserved_at_44[0x4];
9474 u8 pd[0x18];
9475
9476 u8 reserved_at_60[0x20];
9477};
9478
9479struct mlx5_ifc_create_mkey_out_bits {
9480 u8 status[0x8];
9481 u8 reserved_at_8[0x18];
9482
9483 u8 syndrome[0x20];
9484
9485 u8 reserved_at_40[0x8];
9486 u8 mkey_index[0x18];
9487
9488 u8 reserved_at_60[0x20];
9489};
9490
9491struct mlx5_ifc_create_mkey_in_bits {
9492 u8 opcode[0x10];
9493 u8 uid[0x10];
9494
9495 u8 reserved_at_20[0x10];
9496 u8 op_mod[0x10];
9497
9498 u8 reserved_at_40[0x20];
9499
9500 u8 pg_access[0x1];
9501 u8 mkey_umem_valid[0x1];
9502 u8 data_direct[0x1];
9503 u8 reserved_at_63[0x1d];
9504
9505 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
9506
9507 u8 reserved_at_280[0x80];
9508
9509 u8 translations_octword_actual_size[0x20];
9510
9511 u8 reserved_at_320[0x560];
9512
9513 u8 klm_pas_mtt[][0x20];
9514};
9515
9516enum {
9517 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
9518 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
9519 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
9520 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
9521 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
9522 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
9523 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
9524};
9525
9526struct mlx5_ifc_create_flow_table_out_bits {
9527 u8 status[0x8];
9528 u8 icm_address_63_40[0x18];
9529
9530 u8 syndrome[0x20];
9531
9532 u8 icm_address_39_32[0x8];
9533 u8 table_id[0x18];
9534
9535 u8 icm_address_31_0[0x20];
9536};
9537
9538struct mlx5_ifc_create_flow_table_in_bits {
9539 u8 opcode[0x10];
9540 u8 uid[0x10];
9541
9542 u8 reserved_at_20[0x10];
9543 u8 op_mod[0x10];
9544
9545 u8 other_vport[0x1];
9546 u8 other_eswitch[0x1];
9547 u8 reserved_at_42[0xe];
9548 u8 vport_number[0x10];
9549
9550 u8 reserved_at_60[0x20];
9551
9552 u8 table_type[0x8];
9553 u8 reserved_at_88[0x8];
9554 u8 eswitch_owner_vhca_id[0x10];
9555
9556 u8 reserved_at_a0[0x20];
9557
9558 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9559};
9560
9561struct mlx5_ifc_create_flow_group_out_bits {
9562 u8 status[0x8];
9563 u8 reserved_at_8[0x18];
9564
9565 u8 syndrome[0x20];
9566
9567 u8 reserved_at_40[0x8];
9568 u8 group_id[0x18];
9569
9570 u8 reserved_at_60[0x20];
9571};
9572
9573enum {
9574 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0,
9575 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1,
9576};
9577
9578enum {
9579 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
9580 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
9581 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
9582 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
9583};
9584
9585struct mlx5_ifc_create_flow_group_in_bits {
9586 u8 opcode[0x10];
9587 u8 reserved_at_10[0x10];
9588
9589 u8 reserved_at_20[0x10];
9590 u8 op_mod[0x10];
9591
9592 u8 other_vport[0x1];
9593 u8 other_eswitch[0x1];
9594 u8 reserved_at_42[0xe];
9595 u8 vport_number[0x10];
9596
9597 u8 reserved_at_60[0x20];
9598
9599 u8 table_type[0x8];
9600 u8 reserved_at_88[0x4];
9601 u8 group_type[0x4];
9602 u8 eswitch_owner_vhca_id[0x10];
9603
9604 u8 reserved_at_a0[0x8];
9605 u8 table_id[0x18];
9606
9607 u8 source_eswitch_owner_vhca_id_valid[0x1];
9608
9609 u8 reserved_at_c1[0x1f];
9610
9611 u8 start_flow_index[0x20];
9612
9613 u8 reserved_at_100[0x20];
9614
9615 u8 end_flow_index[0x20];
9616
9617 u8 reserved_at_140[0x10];
9618 u8 match_definer_id[0x10];
9619
9620 u8 reserved_at_160[0x80];
9621
9622 u8 reserved_at_1e0[0x18];
9623 u8 match_criteria_enable[0x8];
9624
9625 struct mlx5_ifc_fte_match_param_bits match_criteria;
9626
9627 u8 reserved_at_1200[0xe00];
9628};
9629
9630struct mlx5_ifc_create_eq_out_bits {
9631 u8 status[0x8];
9632 u8 reserved_at_8[0x18];
9633
9634 u8 syndrome[0x20];
9635
9636 u8 reserved_at_40[0x18];
9637 u8 eq_number[0x8];
9638
9639 u8 reserved_at_60[0x20];
9640};
9641
9642struct mlx5_ifc_create_eq_in_bits {
9643 u8 opcode[0x10];
9644 u8 uid[0x10];
9645
9646 u8 reserved_at_20[0x10];
9647 u8 op_mod[0x10];
9648
9649 u8 reserved_at_40[0x40];
9650
9651 struct mlx5_ifc_eqc_bits eq_context_entry;
9652
9653 u8 reserved_at_280[0x40];
9654
9655 u8 event_bitmask[4][0x40];
9656
9657 u8 reserved_at_3c0[0x4c0];
9658
9659 u8 pas[][0x40];
9660};
9661
9662struct mlx5_ifc_create_dct_out_bits {
9663 u8 status[0x8];
9664 u8 reserved_at_8[0x18];
9665
9666 u8 syndrome[0x20];
9667
9668 u8 reserved_at_40[0x8];
9669 u8 dctn[0x18];
9670
9671 u8 ece[0x20];
9672};
9673
9674struct mlx5_ifc_create_dct_in_bits {
9675 u8 opcode[0x10];
9676 u8 uid[0x10];
9677
9678 u8 reserved_at_20[0x10];
9679 u8 op_mod[0x10];
9680
9681 u8 reserved_at_40[0x40];
9682
9683 struct mlx5_ifc_dctc_bits dct_context_entry;
9684
9685 u8 reserved_at_280[0x180];
9686};
9687
9688struct mlx5_ifc_create_cq_out_bits {
9689 u8 status[0x8];
9690 u8 reserved_at_8[0x18];
9691
9692 u8 syndrome[0x20];
9693
9694 u8 reserved_at_40[0x8];
9695 u8 cqn[0x18];
9696
9697 u8 reserved_at_60[0x20];
9698};
9699
9700struct mlx5_ifc_create_cq_in_bits {
9701 u8 opcode[0x10];
9702 u8 uid[0x10];
9703
9704 u8 reserved_at_20[0x10];
9705 u8 op_mod[0x10];
9706
9707 u8 reserved_at_40[0x40];
9708
9709 struct mlx5_ifc_cqc_bits cq_context;
9710
9711 u8 reserved_at_280[0x60];
9712
9713 u8 cq_umem_valid[0x1];
9714 u8 reserved_at_2e1[0x59f];
9715
9716 u8 pas[][0x40];
9717};
9718
9719struct mlx5_ifc_config_int_moderation_out_bits {
9720 u8 status[0x8];
9721 u8 reserved_at_8[0x18];
9722
9723 u8 syndrome[0x20];
9724
9725 u8 reserved_at_40[0x4];
9726 u8 min_delay[0xc];
9727 u8 int_vector[0x10];
9728
9729 u8 reserved_at_60[0x20];
9730};
9731
9732enum {
9733 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
9734 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
9735};
9736
9737struct mlx5_ifc_config_int_moderation_in_bits {
9738 u8 opcode[0x10];
9739 u8 reserved_at_10[0x10];
9740
9741 u8 reserved_at_20[0x10];
9742 u8 op_mod[0x10];
9743
9744 u8 reserved_at_40[0x4];
9745 u8 min_delay[0xc];
9746 u8 int_vector[0x10];
9747
9748 u8 reserved_at_60[0x20];
9749};
9750
9751struct mlx5_ifc_attach_to_mcg_out_bits {
9752 u8 status[0x8];
9753 u8 reserved_at_8[0x18];
9754
9755 u8 syndrome[0x20];
9756
9757 u8 reserved_at_40[0x40];
9758};
9759
9760struct mlx5_ifc_attach_to_mcg_in_bits {
9761 u8 opcode[0x10];
9762 u8 uid[0x10];
9763
9764 u8 reserved_at_20[0x10];
9765 u8 op_mod[0x10];
9766
9767 u8 reserved_at_40[0x8];
9768 u8 qpn[0x18];
9769
9770 u8 reserved_at_60[0x20];
9771
9772 u8 multicast_gid[16][0x8];
9773};
9774
9775struct mlx5_ifc_arm_xrq_out_bits {
9776 u8 status[0x8];
9777 u8 reserved_at_8[0x18];
9778
9779 u8 syndrome[0x20];
9780
9781 u8 reserved_at_40[0x40];
9782};
9783
9784struct mlx5_ifc_arm_xrq_in_bits {
9785 u8 opcode[0x10];
9786 u8 reserved_at_10[0x10];
9787
9788 u8 reserved_at_20[0x10];
9789 u8 op_mod[0x10];
9790
9791 u8 reserved_at_40[0x8];
9792 u8 xrqn[0x18];
9793
9794 u8 reserved_at_60[0x10];
9795 u8 lwm[0x10];
9796};
9797
9798struct mlx5_ifc_arm_xrc_srq_out_bits {
9799 u8 status[0x8];
9800 u8 reserved_at_8[0x18];
9801
9802 u8 syndrome[0x20];
9803
9804 u8 reserved_at_40[0x40];
9805};
9806
9807enum {
9808 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
9809};
9810
9811struct mlx5_ifc_arm_xrc_srq_in_bits {
9812 u8 opcode[0x10];
9813 u8 uid[0x10];
9814
9815 u8 reserved_at_20[0x10];
9816 u8 op_mod[0x10];
9817
9818 u8 reserved_at_40[0x8];
9819 u8 xrc_srqn[0x18];
9820
9821 u8 reserved_at_60[0x10];
9822 u8 lwm[0x10];
9823};
9824
9825struct mlx5_ifc_arm_rq_out_bits {
9826 u8 status[0x8];
9827 u8 reserved_at_8[0x18];
9828
9829 u8 syndrome[0x20];
9830
9831 u8 reserved_at_40[0x40];
9832};
9833
9834enum {
9835 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9836 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9837};
9838
9839struct mlx5_ifc_arm_rq_in_bits {
9840 u8 opcode[0x10];
9841 u8 uid[0x10];
9842
9843 u8 reserved_at_20[0x10];
9844 u8 op_mod[0x10];
9845
9846 u8 reserved_at_40[0x8];
9847 u8 srq_number[0x18];
9848
9849 u8 reserved_at_60[0x10];
9850 u8 lwm[0x10];
9851};
9852
9853struct mlx5_ifc_arm_dct_out_bits {
9854 u8 status[0x8];
9855 u8 reserved_at_8[0x18];
9856
9857 u8 syndrome[0x20];
9858
9859 u8 reserved_at_40[0x40];
9860};
9861
9862struct mlx5_ifc_arm_dct_in_bits {
9863 u8 opcode[0x10];
9864 u8 reserved_at_10[0x10];
9865
9866 u8 reserved_at_20[0x10];
9867 u8 op_mod[0x10];
9868
9869 u8 reserved_at_40[0x8];
9870 u8 dct_number[0x18];
9871
9872 u8 reserved_at_60[0x20];
9873};
9874
9875struct mlx5_ifc_alloc_xrcd_out_bits {
9876 u8 status[0x8];
9877 u8 reserved_at_8[0x18];
9878
9879 u8 syndrome[0x20];
9880
9881 u8 reserved_at_40[0x8];
9882 u8 xrcd[0x18];
9883
9884 u8 reserved_at_60[0x20];
9885};
9886
9887struct mlx5_ifc_alloc_xrcd_in_bits {
9888 u8 opcode[0x10];
9889 u8 uid[0x10];
9890
9891 u8 reserved_at_20[0x10];
9892 u8 op_mod[0x10];
9893
9894 u8 reserved_at_40[0x40];
9895};
9896
9897struct mlx5_ifc_alloc_uar_out_bits {
9898 u8 status[0x8];
9899 u8 reserved_at_8[0x18];
9900
9901 u8 syndrome[0x20];
9902
9903 u8 reserved_at_40[0x8];
9904 u8 uar[0x18];
9905
9906 u8 reserved_at_60[0x20];
9907};
9908
9909struct mlx5_ifc_alloc_uar_in_bits {
9910 u8 opcode[0x10];
9911 u8 uid[0x10];
9912
9913 u8 reserved_at_20[0x10];
9914 u8 op_mod[0x10];
9915
9916 u8 reserved_at_40[0x40];
9917};
9918
9919struct mlx5_ifc_alloc_transport_domain_out_bits {
9920 u8 status[0x8];
9921 u8 reserved_at_8[0x18];
9922
9923 u8 syndrome[0x20];
9924
9925 u8 reserved_at_40[0x8];
9926 u8 transport_domain[0x18];
9927
9928 u8 reserved_at_60[0x20];
9929};
9930
9931struct mlx5_ifc_alloc_transport_domain_in_bits {
9932 u8 opcode[0x10];
9933 u8 uid[0x10];
9934
9935 u8 reserved_at_20[0x10];
9936 u8 op_mod[0x10];
9937
9938 u8 reserved_at_40[0x40];
9939};
9940
9941struct mlx5_ifc_alloc_q_counter_out_bits {
9942 u8 status[0x8];
9943 u8 reserved_at_8[0x18];
9944
9945 u8 syndrome[0x20];
9946
9947 u8 reserved_at_40[0x18];
9948 u8 counter_set_id[0x8];
9949
9950 u8 reserved_at_60[0x20];
9951};
9952
9953struct mlx5_ifc_alloc_q_counter_in_bits {
9954 u8 opcode[0x10];
9955 u8 uid[0x10];
9956
9957 u8 reserved_at_20[0x10];
9958 u8 op_mod[0x10];
9959
9960 u8 reserved_at_40[0x40];
9961};
9962
9963struct mlx5_ifc_alloc_pd_out_bits {
9964 u8 status[0x8];
9965 u8 reserved_at_8[0x18];
9966
9967 u8 syndrome[0x20];
9968
9969 u8 reserved_at_40[0x8];
9970 u8 pd[0x18];
9971
9972 u8 reserved_at_60[0x20];
9973};
9974
9975struct mlx5_ifc_alloc_pd_in_bits {
9976 u8 opcode[0x10];
9977 u8 uid[0x10];
9978
9979 u8 reserved_at_20[0x10];
9980 u8 op_mod[0x10];
9981
9982 u8 reserved_at_40[0x40];
9983};
9984
9985struct mlx5_ifc_alloc_flow_counter_out_bits {
9986 u8 status[0x8];
9987 u8 reserved_at_8[0x18];
9988
9989 u8 syndrome[0x20];
9990
9991 u8 flow_counter_id[0x20];
9992
9993 u8 reserved_at_60[0x20];
9994};
9995
9996struct mlx5_ifc_alloc_flow_counter_in_bits {
9997 u8 opcode[0x10];
9998 u8 reserved_at_10[0x10];
9999
10000 u8 reserved_at_20[0x10];
10001 u8 op_mod[0x10];
10002
10003 u8 reserved_at_40[0x33];
10004 u8 flow_counter_bulk_log_size[0x5];
10005 u8 flow_counter_bulk[0x8];
10006};
10007
10008struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
10009 u8 status[0x8];
10010 u8 reserved_at_8[0x18];
10011
10012 u8 syndrome[0x20];
10013
10014 u8 reserved_at_40[0x40];
10015};
10016
10017struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
10018 u8 opcode[0x10];
10019 u8 reserved_at_10[0x10];
10020
10021 u8 reserved_at_20[0x10];
10022 u8 op_mod[0x10];
10023
10024 u8 reserved_at_40[0x20];
10025
10026 u8 reserved_at_60[0x10];
10027 u8 vxlan_udp_port[0x10];
10028};
10029
10030struct mlx5_ifc_set_pp_rate_limit_out_bits {
10031 u8 status[0x8];
10032 u8 reserved_at_8[0x18];
10033
10034 u8 syndrome[0x20];
10035
10036 u8 reserved_at_40[0x40];
10037};
10038
10039struct mlx5_ifc_set_pp_rate_limit_context_bits {
10040 u8 rate_limit[0x20];
10041
10042 u8 burst_upper_bound[0x20];
10043
10044 u8 reserved_at_40[0x10];
10045 u8 typical_packet_size[0x10];
10046
10047 u8 reserved_at_60[0x120];
10048};
10049
10050struct mlx5_ifc_set_pp_rate_limit_in_bits {
10051 u8 opcode[0x10];
10052 u8 uid[0x10];
10053
10054 u8 reserved_at_20[0x10];
10055 u8 op_mod[0x10];
10056
10057 u8 reserved_at_40[0x10];
10058 u8 rate_limit_index[0x10];
10059
10060 u8 reserved_at_60[0x20];
10061
10062 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
10063};
10064
10065struct mlx5_ifc_access_register_out_bits {
10066 u8 status[0x8];
10067 u8 reserved_at_8[0x18];
10068
10069 u8 syndrome[0x20];
10070
10071 u8 reserved_at_40[0x40];
10072
10073 u8 register_data[][0x20];
10074};
10075
10076enum {
10077 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
10078 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
10079};
10080
10081struct mlx5_ifc_access_register_in_bits {
10082 u8 opcode[0x10];
10083 u8 reserved_at_10[0x10];
10084
10085 u8 reserved_at_20[0x10];
10086 u8 op_mod[0x10];
10087
10088 u8 reserved_at_40[0x10];
10089 u8 register_id[0x10];
10090
10091 u8 argument[0x20];
10092
10093 u8 register_data[][0x20];
10094};
10095
10096struct mlx5_ifc_sltp_reg_bits {
10097 u8 status[0x4];
10098 u8 version[0x4];
10099 u8 local_port[0x8];
10100 u8 pnat[0x2];
10101 u8 reserved_at_12[0x2];
10102 u8 lane[0x4];
10103 u8 reserved_at_18[0x8];
10104
10105 u8 reserved_at_20[0x20];
10106
10107 u8 reserved_at_40[0x7];
10108 u8 polarity[0x1];
10109 u8 ob_tap0[0x8];
10110 u8 ob_tap1[0x8];
10111 u8 ob_tap2[0x8];
10112
10113 u8 reserved_at_60[0xc];
10114 u8 ob_preemp_mode[0x4];
10115 u8 ob_reg[0x8];
10116 u8 ob_bias[0x8];
10117
10118 u8 reserved_at_80[0x20];
10119};
10120
10121struct mlx5_ifc_slrg_reg_bits {
10122 u8 status[0x4];
10123 u8 version[0x4];
10124 u8 local_port[0x8];
10125 u8 pnat[0x2];
10126 u8 reserved_at_12[0x2];
10127 u8 lane[0x4];
10128 u8 reserved_at_18[0x8];
10129
10130 u8 time_to_link_up[0x10];
10131 u8 reserved_at_30[0xc];
10132 u8 grade_lane_speed[0x4];
10133
10134 u8 grade_version[0x8];
10135 u8 grade[0x18];
10136
10137 u8 reserved_at_60[0x4];
10138 u8 height_grade_type[0x4];
10139 u8 height_grade[0x18];
10140
10141 u8 height_dz[0x10];
10142 u8 height_dv[0x10];
10143
10144 u8 reserved_at_a0[0x10];
10145 u8 height_sigma[0x10];
10146
10147 u8 reserved_at_c0[0x20];
10148
10149 u8 reserved_at_e0[0x4];
10150 u8 phase_grade_type[0x4];
10151 u8 phase_grade[0x18];
10152
10153 u8 reserved_at_100[0x8];
10154 u8 phase_eo_pos[0x8];
10155 u8 reserved_at_110[0x8];
10156 u8 phase_eo_neg[0x8];
10157
10158 u8 ffe_set_tested[0x10];
10159 u8 test_errors_per_lane[0x10];
10160};
10161
10162struct mlx5_ifc_pvlc_reg_bits {
10163 u8 reserved_at_0[0x8];
10164 u8 local_port[0x8];
10165 u8 reserved_at_10[0x10];
10166
10167 u8 reserved_at_20[0x1c];
10168 u8 vl_hw_cap[0x4];
10169
10170 u8 reserved_at_40[0x1c];
10171 u8 vl_admin[0x4];
10172
10173 u8 reserved_at_60[0x1c];
10174 u8 vl_operational[0x4];
10175};
10176
10177struct mlx5_ifc_pude_reg_bits {
10178 u8 swid[0x8];
10179 u8 local_port[0x8];
10180 u8 reserved_at_10[0x4];
10181 u8 admin_status[0x4];
10182 u8 reserved_at_18[0x4];
10183 u8 oper_status[0x4];
10184
10185 u8 reserved_at_20[0x60];
10186};
10187
10188enum {
10189 MLX5_PTYS_CONNECTOR_TYPE_PORT_DA = 0x7,
10190};
10191
10192struct mlx5_ifc_ptys_reg_bits {
10193 u8 reserved_at_0[0x1];
10194 u8 an_disable_admin[0x1];
10195 u8 an_disable_cap[0x1];
10196 u8 reserved_at_3[0x5];
10197 u8 local_port[0x8];
10198 u8 reserved_at_10[0x8];
10199 u8 plane_ind[0x4];
10200 u8 reserved_at_1c[0x1];
10201 u8 proto_mask[0x3];
10202
10203 u8 an_status[0x4];
10204 u8 reserved_at_24[0xc];
10205 u8 data_rate_oper[0x10];
10206
10207 u8 ext_eth_proto_capability[0x20];
10208
10209 u8 eth_proto_capability[0x20];
10210
10211 u8 ib_link_width_capability[0x10];
10212 u8 ib_proto_capability[0x10];
10213
10214 u8 ext_eth_proto_admin[0x20];
10215
10216 u8 eth_proto_admin[0x20];
10217
10218 u8 ib_link_width_admin[0x10];
10219 u8 ib_proto_admin[0x10];
10220
10221 u8 ext_eth_proto_oper[0x20];
10222
10223 u8 eth_proto_oper[0x20];
10224
10225 u8 ib_link_width_oper[0x10];
10226 u8 ib_proto_oper[0x10];
10227
10228 u8 reserved_at_160[0x8];
10229 u8 lane_rate_oper[0x14];
10230 u8 connector_type[0x4];
10231
10232 u8 eth_proto_lp_advertise[0x20];
10233
10234 u8 reserved_at_1a0[0x60];
10235};
10236
10237struct mlx5_ifc_mlcr_reg_bits {
10238 u8 reserved_at_0[0x8];
10239 u8 local_port[0x8];
10240 u8 reserved_at_10[0x20];
10241
10242 u8 beacon_duration[0x10];
10243 u8 reserved_at_40[0x10];
10244
10245 u8 beacon_remain[0x10];
10246};
10247
10248struct mlx5_ifc_ptas_reg_bits {
10249 u8 reserved_at_0[0x20];
10250
10251 u8 algorithm_options[0x10];
10252 u8 reserved_at_30[0x4];
10253 u8 repetitions_mode[0x4];
10254 u8 num_of_repetitions[0x8];
10255
10256 u8 grade_version[0x8];
10257 u8 height_grade_type[0x4];
10258 u8 phase_grade_type[0x4];
10259 u8 height_grade_weight[0x8];
10260 u8 phase_grade_weight[0x8];
10261
10262 u8 gisim_measure_bits[0x10];
10263 u8 adaptive_tap_measure_bits[0x10];
10264
10265 u8 ber_bath_high_error_threshold[0x10];
10266 u8 ber_bath_mid_error_threshold[0x10];
10267
10268 u8 ber_bath_low_error_threshold[0x10];
10269 u8 one_ratio_high_threshold[0x10];
10270
10271 u8 one_ratio_high_mid_threshold[0x10];
10272 u8 one_ratio_low_mid_threshold[0x10];
10273
10274 u8 one_ratio_low_threshold[0x10];
10275 u8 ndeo_error_threshold[0x10];
10276
10277 u8 mixer_offset_step_size[0x10];
10278 u8 reserved_at_110[0x8];
10279 u8 mix90_phase_for_voltage_bath[0x8];
10280
10281 u8 mixer_offset_start[0x10];
10282 u8 mixer_offset_end[0x10];
10283
10284 u8 reserved_at_140[0x15];
10285 u8 ber_test_time[0xb];
10286};
10287
10288struct mlx5_ifc_pspa_reg_bits {
10289 u8 swid[0x8];
10290 u8 local_port[0x8];
10291 u8 sub_port[0x8];
10292 u8 reserved_at_18[0x8];
10293
10294 u8 reserved_at_20[0x20];
10295};
10296
10297struct mlx5_ifc_pqdr_reg_bits {
10298 u8 reserved_at_0[0x8];
10299 u8 local_port[0x8];
10300 u8 reserved_at_10[0x5];
10301 u8 prio[0x3];
10302 u8 reserved_at_18[0x6];
10303 u8 mode[0x2];
10304
10305 u8 reserved_at_20[0x20];
10306
10307 u8 reserved_at_40[0x10];
10308 u8 min_threshold[0x10];
10309
10310 u8 reserved_at_60[0x10];
10311 u8 max_threshold[0x10];
10312
10313 u8 reserved_at_80[0x10];
10314 u8 mark_probability_denominator[0x10];
10315
10316 u8 reserved_at_a0[0x60];
10317};
10318
10319struct mlx5_ifc_ppsc_reg_bits {
10320 u8 reserved_at_0[0x8];
10321 u8 local_port[0x8];
10322 u8 reserved_at_10[0x10];
10323
10324 u8 reserved_at_20[0x60];
10325
10326 u8 reserved_at_80[0x1c];
10327 u8 wrps_admin[0x4];
10328
10329 u8 reserved_at_a0[0x1c];
10330 u8 wrps_status[0x4];
10331
10332 u8 reserved_at_c0[0x8];
10333 u8 up_threshold[0x8];
10334 u8 reserved_at_d0[0x8];
10335 u8 down_threshold[0x8];
10336
10337 u8 reserved_at_e0[0x20];
10338
10339 u8 reserved_at_100[0x1c];
10340 u8 srps_admin[0x4];
10341
10342 u8 reserved_at_120[0x1c];
10343 u8 srps_status[0x4];
10344
10345 u8 reserved_at_140[0x40];
10346};
10347
10348struct mlx5_ifc_pplr_reg_bits {
10349 u8 reserved_at_0[0x8];
10350 u8 local_port[0x8];
10351 u8 reserved_at_10[0x10];
10352
10353 u8 reserved_at_20[0x8];
10354 u8 lb_cap[0x8];
10355 u8 reserved_at_30[0x8];
10356 u8 lb_en[0x8];
10357};
10358
10359struct mlx5_ifc_pplm_reg_bits {
10360 u8 reserved_at_0[0x8];
10361 u8 local_port[0x8];
10362 u8 reserved_at_10[0x10];
10363
10364 u8 reserved_at_20[0x20];
10365
10366 u8 port_profile_mode[0x8];
10367 u8 static_port_profile[0x8];
10368 u8 active_port_profile[0x8];
10369 u8 reserved_at_58[0x8];
10370
10371 u8 retransmission_active[0x8];
10372 u8 fec_mode_active[0x18];
10373
10374 u8 rs_fec_correction_bypass_cap[0x4];
10375 u8 reserved_at_84[0x8];
10376 u8 fec_override_cap_56g[0x4];
10377 u8 fec_override_cap_100g[0x4];
10378 u8 fec_override_cap_50g[0x4];
10379 u8 fec_override_cap_25g[0x4];
10380 u8 fec_override_cap_10g_40g[0x4];
10381
10382 u8 rs_fec_correction_bypass_admin[0x4];
10383 u8 reserved_at_a4[0x8];
10384 u8 fec_override_admin_56g[0x4];
10385 u8 fec_override_admin_100g[0x4];
10386 u8 fec_override_admin_50g[0x4];
10387 u8 fec_override_admin_25g[0x4];
10388 u8 fec_override_admin_10g_40g[0x4];
10389
10390 u8 fec_override_cap_400g_8x[0x10];
10391 u8 fec_override_cap_200g_4x[0x10];
10392
10393 u8 fec_override_cap_100g_2x[0x10];
10394 u8 fec_override_cap_50g_1x[0x10];
10395
10396 u8 fec_override_admin_400g_8x[0x10];
10397 u8 fec_override_admin_200g_4x[0x10];
10398
10399 u8 fec_override_admin_100g_2x[0x10];
10400 u8 fec_override_admin_50g_1x[0x10];
10401
10402 u8 fec_override_cap_800g_8x[0x10];
10403 u8 fec_override_cap_400g_4x[0x10];
10404
10405 u8 fec_override_cap_200g_2x[0x10];
10406 u8 fec_override_cap_100g_1x[0x10];
10407
10408 u8 reserved_at_180[0xa0];
10409
10410 u8 fec_override_admin_800g_8x[0x10];
10411 u8 fec_override_admin_400g_4x[0x10];
10412
10413 u8 fec_override_admin_200g_2x[0x10];
10414 u8 fec_override_admin_100g_1x[0x10];
10415
10416 u8 reserved_at_260[0x60];
10417
10418 u8 fec_override_cap_1600g_8x[0x10];
10419 u8 fec_override_cap_800g_4x[0x10];
10420
10421 u8 fec_override_cap_400g_2x[0x10];
10422 u8 fec_override_cap_200g_1x[0x10];
10423
10424 u8 fec_override_admin_1600g_8x[0x10];
10425 u8 fec_override_admin_800g_4x[0x10];
10426
10427 u8 fec_override_admin_400g_2x[0x10];
10428 u8 fec_override_admin_200g_1x[0x10];
10429
10430 u8 reserved_at_340[0x80];
10431};
10432
10433struct mlx5_ifc_ppcnt_reg_bits {
10434 u8 swid[0x8];
10435 u8 local_port[0x8];
10436 u8 pnat[0x2];
10437 u8 reserved_at_12[0x8];
10438 u8 grp[0x6];
10439
10440 u8 clr[0x1];
10441 u8 reserved_at_21[0x13];
10442 u8 plane_ind[0x4];
10443 u8 reserved_at_38[0x3];
10444 u8 prio_tc[0x5];
10445
10446 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
10447};
10448
10449struct mlx5_ifc_mpein_reg_bits {
10450 u8 reserved_at_0[0x2];
10451 u8 depth[0x6];
10452 u8 pcie_index[0x8];
10453 u8 node[0x8];
10454 u8 reserved_at_18[0x8];
10455
10456 u8 capability_mask[0x20];
10457
10458 u8 reserved_at_40[0x8];
10459 u8 link_width_enabled[0x8];
10460 u8 link_speed_enabled[0x10];
10461
10462 u8 lane0_physical_position[0x8];
10463 u8 link_width_active[0x8];
10464 u8 link_speed_active[0x10];
10465
10466 u8 num_of_pfs[0x10];
10467 u8 num_of_vfs[0x10];
10468
10469 u8 bdf0[0x10];
10470 u8 reserved_at_b0[0x10];
10471
10472 u8 max_read_request_size[0x4];
10473 u8 max_payload_size[0x4];
10474 u8 reserved_at_c8[0x5];
10475 u8 pwr_status[0x3];
10476 u8 port_type[0x4];
10477 u8 reserved_at_d4[0xb];
10478 u8 lane_reversal[0x1];
10479
10480 u8 reserved_at_e0[0x14];
10481 u8 pci_power[0xc];
10482
10483 u8 reserved_at_100[0x20];
10484
10485 u8 device_status[0x10];
10486 u8 port_state[0x8];
10487 u8 reserved_at_138[0x8];
10488
10489 u8 reserved_at_140[0x10];
10490 u8 receiver_detect_result[0x10];
10491
10492 u8 reserved_at_160[0x20];
10493};
10494
10495struct mlx5_ifc_mpcnt_reg_bits {
10496 u8 reserved_at_0[0x8];
10497 u8 pcie_index[0x8];
10498 u8 reserved_at_10[0xa];
10499 u8 grp[0x6];
10500
10501 u8 clr[0x1];
10502 u8 reserved_at_21[0x1f];
10503
10504 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
10505};
10506
10507struct mlx5_ifc_ppad_reg_bits {
10508 u8 reserved_at_0[0x3];
10509 u8 single_mac[0x1];
10510 u8 reserved_at_4[0x4];
10511 u8 local_port[0x8];
10512 u8 mac_47_32[0x10];
10513
10514 u8 mac_31_0[0x20];
10515
10516 u8 reserved_at_40[0x40];
10517};
10518
10519struct mlx5_ifc_pmtu_reg_bits {
10520 u8 reserved_at_0[0x8];
10521 u8 local_port[0x8];
10522 u8 reserved_at_10[0x10];
10523
10524 u8 max_mtu[0x10];
10525 u8 reserved_at_30[0x10];
10526
10527 u8 admin_mtu[0x10];
10528 u8 reserved_at_50[0x10];
10529
10530 u8 oper_mtu[0x10];
10531 u8 reserved_at_70[0x10];
10532};
10533
10534struct mlx5_ifc_pmpr_reg_bits {
10535 u8 reserved_at_0[0x8];
10536 u8 module[0x8];
10537 u8 reserved_at_10[0x10];
10538
10539 u8 reserved_at_20[0x18];
10540 u8 attenuation_5g[0x8];
10541
10542 u8 reserved_at_40[0x18];
10543 u8 attenuation_7g[0x8];
10544
10545 u8 reserved_at_60[0x18];
10546 u8 attenuation_12g[0x8];
10547};
10548
10549struct mlx5_ifc_pmpe_reg_bits {
10550 u8 reserved_at_0[0x8];
10551 u8 module[0x8];
10552 u8 reserved_at_10[0xc];
10553 u8 module_status[0x4];
10554
10555 u8 reserved_at_20[0x60];
10556};
10557
10558struct mlx5_ifc_pmpc_reg_bits {
10559 u8 module_state_updated[32][0x8];
10560};
10561
10562struct mlx5_ifc_pmlpn_reg_bits {
10563 u8 reserved_at_0[0x4];
10564 u8 mlpn_status[0x4];
10565 u8 local_port[0x8];
10566 u8 reserved_at_10[0x10];
10567
10568 u8 e[0x1];
10569 u8 reserved_at_21[0x1f];
10570};
10571
10572struct mlx5_ifc_pmlp_reg_bits {
10573 u8 rxtx[0x1];
10574 u8 reserved_at_1[0x7];
10575 u8 local_port[0x8];
10576 u8 reserved_at_10[0x8];
10577 u8 width[0x8];
10578
10579 u8 lane0_module_mapping[0x20];
10580
10581 u8 lane1_module_mapping[0x20];
10582
10583 u8 lane2_module_mapping[0x20];
10584
10585 u8 lane3_module_mapping[0x20];
10586
10587 u8 reserved_at_a0[0x160];
10588};
10589
10590struct mlx5_ifc_pmaos_reg_bits {
10591 u8 reserved_at_0[0x8];
10592 u8 module[0x8];
10593 u8 reserved_at_10[0x4];
10594 u8 admin_status[0x4];
10595 u8 reserved_at_18[0x4];
10596 u8 oper_status[0x4];
10597
10598 u8 ase[0x1];
10599 u8 ee[0x1];
10600 u8 reserved_at_22[0x1c];
10601 u8 e[0x2];
10602
10603 u8 reserved_at_40[0x40];
10604};
10605
10606struct mlx5_ifc_plpc_reg_bits {
10607 u8 reserved_at_0[0x4];
10608 u8 profile_id[0xc];
10609 u8 reserved_at_10[0x4];
10610 u8 proto_mask[0x4];
10611 u8 reserved_at_18[0x8];
10612
10613 u8 reserved_at_20[0x10];
10614 u8 lane_speed[0x10];
10615
10616 u8 reserved_at_40[0x17];
10617 u8 lpbf[0x1];
10618 u8 fec_mode_policy[0x8];
10619
10620 u8 retransmission_capability[0x8];
10621 u8 fec_mode_capability[0x18];
10622
10623 u8 retransmission_support_admin[0x8];
10624 u8 fec_mode_support_admin[0x18];
10625
10626 u8 retransmission_request_admin[0x8];
10627 u8 fec_mode_request_admin[0x18];
10628
10629 u8 reserved_at_c0[0x80];
10630};
10631
10632struct mlx5_ifc_plib_reg_bits {
10633 u8 reserved_at_0[0x8];
10634 u8 local_port[0x8];
10635 u8 reserved_at_10[0x8];
10636 u8 ib_port[0x8];
10637
10638 u8 reserved_at_20[0x60];
10639};
10640
10641struct mlx5_ifc_plbf_reg_bits {
10642 u8 reserved_at_0[0x8];
10643 u8 local_port[0x8];
10644 u8 reserved_at_10[0xd];
10645 u8 lbf_mode[0x3];
10646
10647 u8 reserved_at_20[0x20];
10648};
10649
10650struct mlx5_ifc_pipg_reg_bits {
10651 u8 reserved_at_0[0x8];
10652 u8 local_port[0x8];
10653 u8 reserved_at_10[0x10];
10654
10655 u8 dic[0x1];
10656 u8 reserved_at_21[0x19];
10657 u8 ipg[0x4];
10658 u8 reserved_at_3e[0x2];
10659};
10660
10661struct mlx5_ifc_pifr_reg_bits {
10662 u8 reserved_at_0[0x8];
10663 u8 local_port[0x8];
10664 u8 reserved_at_10[0x10];
10665
10666 u8 reserved_at_20[0xe0];
10667
10668 u8 port_filter[8][0x20];
10669
10670 u8 port_filter_update_en[8][0x20];
10671};
10672
10673enum {
10674 MLX5_BUF_OWNERSHIP_UNKNOWN = 0x0,
10675 MLX5_BUF_OWNERSHIP_FW_OWNED = 0x1,
10676 MLX5_BUF_OWNERSHIP_SW_OWNED = 0x2,
10677};
10678
10679struct mlx5_ifc_pfcc_reg_bits {
10680 u8 reserved_at_0[0x4];
10681 u8 buf_ownership[0x2];
10682 u8 reserved_at_6[0x2];
10683 u8 local_port[0x8];
10684 u8 reserved_at_10[0xa];
10685 u8 cable_length_mask[0x1];
10686 u8 ppan_mask_n[0x1];
10687 u8 minor_stall_mask[0x1];
10688 u8 critical_stall_mask[0x1];
10689 u8 reserved_at_1e[0x2];
10690
10691 u8 ppan[0x4];
10692 u8 reserved_at_24[0x4];
10693 u8 prio_mask_tx[0x8];
10694 u8 reserved_at_30[0x8];
10695 u8 prio_mask_rx[0x8];
10696
10697 u8 pptx[0x1];
10698 u8 aptx[0x1];
10699 u8 pptx_mask_n[0x1];
10700 u8 reserved_at_43[0x5];
10701 u8 pfctx[0x8];
10702 u8 reserved_at_50[0x10];
10703
10704 u8 pprx[0x1];
10705 u8 aprx[0x1];
10706 u8 pprx_mask_n[0x1];
10707 u8 reserved_at_63[0x5];
10708 u8 pfcrx[0x8];
10709 u8 reserved_at_70[0x10];
10710
10711 u8 device_stall_minor_watermark[0x10];
10712 u8 device_stall_critical_watermark[0x10];
10713
10714 u8 reserved_at_a0[0x18];
10715 u8 cable_length[0x8];
10716
10717 u8 reserved_at_c0[0x40];
10718};
10719
10720struct mlx5_ifc_pelc_reg_bits {
10721 u8 op[0x4];
10722 u8 reserved_at_4[0x4];
10723 u8 local_port[0x8];
10724 u8 reserved_at_10[0x10];
10725
10726 u8 op_admin[0x8];
10727 u8 op_capability[0x8];
10728 u8 op_request[0x8];
10729 u8 op_active[0x8];
10730
10731 u8 admin[0x40];
10732
10733 u8 capability[0x40];
10734
10735 u8 request[0x40];
10736
10737 u8 active[0x40];
10738
10739 u8 reserved_at_140[0x80];
10740};
10741
10742struct mlx5_ifc_peir_reg_bits {
10743 u8 reserved_at_0[0x8];
10744 u8 local_port[0x8];
10745 u8 reserved_at_10[0x10];
10746
10747 u8 reserved_at_20[0xc];
10748 u8 error_count[0x4];
10749 u8 reserved_at_30[0x10];
10750
10751 u8 reserved_at_40[0xc];
10752 u8 lane[0x4];
10753 u8 reserved_at_50[0x8];
10754 u8 error_type[0x8];
10755};
10756
10757struct mlx5_ifc_mpegc_reg_bits {
10758 u8 reserved_at_0[0x30];
10759 u8 field_select[0x10];
10760
10761 u8 tx_overflow_sense[0x1];
10762 u8 mark_cqe[0x1];
10763 u8 mark_cnp[0x1];
10764 u8 reserved_at_43[0x1b];
10765 u8 tx_lossy_overflow_oper[0x2];
10766
10767 u8 reserved_at_60[0x100];
10768};
10769
10770struct mlx5_ifc_mpir_reg_bits {
10771 u8 sdm[0x1];
10772 u8 reserved_at_1[0x1b];
10773 u8 host_buses[0x4];
10774
10775 u8 reserved_at_20[0x20];
10776
10777 u8 local_port[0x8];
10778 u8 reserved_at_28[0x18];
10779
10780 u8 reserved_at_60[0x20];
10781};
10782
10783enum {
10784 MLX5_MTUTC_FREQ_ADJ_UNITS_PPB = 0x0,
10785 MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM = 0x1,
10786};
10787
10788enum {
10789 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1,
10790 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2,
10791 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3,
10792};
10793
10794struct mlx5_ifc_mtutc_reg_bits {
10795 u8 reserved_at_0[0x5];
10796 u8 freq_adj_units[0x3];
10797 u8 reserved_at_8[0x3];
10798 u8 log_max_freq_adjustment[0x5];
10799
10800 u8 reserved_at_10[0xc];
10801 u8 operation[0x4];
10802
10803 u8 freq_adjustment[0x20];
10804
10805 u8 reserved_at_40[0x40];
10806
10807 u8 utc_sec[0x20];
10808
10809 u8 reserved_at_a0[0x2];
10810 u8 utc_nsec[0x1e];
10811
10812 u8 time_adjustment[0x20];
10813};
10814
10815struct mlx5_ifc_pcam_enhanced_features_bits {
10816 u8 reserved_at_0[0x10];
10817 u8 ppcnt_recovery_counters[0x1];
10818 u8 reserved_at_11[0x7];
10819 u8 cable_length[0x1];
10820 u8 reserved_at_19[0x4];
10821 u8 fec_200G_per_lane_in_pplm[0x1];
10822 u8 reserved_at_1e[0x2a];
10823 u8 fec_100G_per_lane_in_pplm[0x1];
10824 u8 reserved_at_49[0xa];
10825 u8 buffer_ownership[0x1];
10826 u8 resereved_at_54[0x14];
10827 u8 fec_50G_per_lane_in_pplm[0x1];
10828 u8 reserved_at_69[0x4];
10829 u8 rx_icrc_encapsulated_counter[0x1];
10830 u8 reserved_at_6e[0x4];
10831 u8 ptys_extended_ethernet[0x1];
10832 u8 reserved_at_73[0x3];
10833 u8 pfcc_mask[0x1];
10834 u8 reserved_at_77[0x3];
10835 u8 per_lane_error_counters[0x1];
10836 u8 rx_buffer_fullness_counters[0x1];
10837 u8 ptys_connector_type[0x1];
10838 u8 reserved_at_7d[0x1];
10839 u8 ppcnt_discard_group[0x1];
10840 u8 ppcnt_statistical_group[0x1];
10841};
10842
10843struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10844 u8 port_access_reg_cap_mask_127_to_96[0x20];
10845 u8 port_access_reg_cap_mask_95_to_64[0x20];
10846
10847 u8 port_access_reg_cap_mask_63[0x1];
10848 u8 pphcr[0x1];
10849 u8 port_access_reg_cap_mask_61_to_36[0x1a];
10850 u8 pplm[0x1];
10851 u8 port_access_reg_cap_mask_34_to_32[0x3];
10852
10853 u8 port_access_reg_cap_mask_31_to_13[0x13];
10854 u8 pbmc[0x1];
10855 u8 pptb[0x1];
10856 u8 port_access_reg_cap_mask_10_to_09[0x2];
10857 u8 ppcnt[0x1];
10858 u8 port_access_reg_cap_mask_07_to_00[0x8];
10859};
10860
10861struct mlx5_ifc_pcam_reg_bits {
10862 u8 reserved_at_0[0x8];
10863 u8 feature_group[0x8];
10864 u8 reserved_at_10[0x8];
10865 u8 access_reg_group[0x8];
10866
10867 u8 reserved_at_20[0x20];
10868
10869 union {
10870 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10871 u8 reserved_at_0[0x80];
10872 } port_access_reg_cap_mask;
10873
10874 u8 reserved_at_c0[0x80];
10875
10876 union {
10877 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10878 u8 reserved_at_0[0x80];
10879 } feature_cap_mask;
10880
10881 u8 reserved_at_1c0[0xc0];
10882};
10883
10884struct mlx5_ifc_mcam_enhanced_features_bits {
10885 u8 reserved_at_0[0x50];
10886 u8 mtutc_freq_adj_units[0x1];
10887 u8 mtutc_time_adjustment_extended_range[0x1];
10888 u8 reserved_at_52[0xb];
10889 u8 mcia_32dwords[0x1];
10890 u8 out_pulse_duration_ns[0x1];
10891 u8 npps_period[0x1];
10892 u8 reserved_at_60[0xa];
10893 u8 reset_state[0x1];
10894 u8 ptpcyc2realtime_modify[0x1];
10895 u8 reserved_at_6c[0x2];
10896 u8 pci_status_and_power[0x1];
10897 u8 reserved_at_6f[0x5];
10898 u8 mark_tx_action_cnp[0x1];
10899 u8 mark_tx_action_cqe[0x1];
10900 u8 dynamic_tx_overflow[0x1];
10901 u8 reserved_at_77[0x4];
10902 u8 pcie_outbound_stalled[0x1];
10903 u8 tx_overflow_buffer_pkt[0x1];
10904 u8 mtpps_enh_out_per_adj[0x1];
10905 u8 mtpps_fs[0x1];
10906 u8 pcie_performance_group[0x1];
10907};
10908
10909struct mlx5_ifc_mcam_access_reg_bits {
10910 u8 reserved_at_0[0x1c];
10911 u8 mcda[0x1];
10912 u8 mcc[0x1];
10913 u8 mcqi[0x1];
10914 u8 mcqs[0x1];
10915
10916 u8 regs_95_to_90[0x6];
10917 u8 mpir[0x1];
10918 u8 regs_88_to_87[0x2];
10919 u8 mpegc[0x1];
10920 u8 mtutc[0x1];
10921 u8 regs_84_to_68[0x11];
10922 u8 tracer_registers[0x4];
10923
10924 u8 regs_63_to_46[0x12];
10925 u8 mrtc[0x1];
10926 u8 regs_44_to_41[0x4];
10927 u8 mfrl[0x1];
10928 u8 regs_39_to_32[0x8];
10929
10930 u8 regs_31_to_11[0x15];
10931 u8 mtmp[0x1];
10932 u8 regs_9_to_0[0xa];
10933};
10934
10935struct mlx5_ifc_mcam_access_reg_bits1 {
10936 u8 regs_127_to_96[0x20];
10937
10938 u8 regs_95_to_64[0x20];
10939
10940 u8 regs_63_to_32[0x20];
10941
10942 u8 regs_31_to_0[0x20];
10943};
10944
10945struct mlx5_ifc_mcam_access_reg_bits2 {
10946 u8 regs_127_to_99[0x1d];
10947 u8 mirc[0x1];
10948 u8 regs_97_to_96[0x2];
10949
10950 u8 regs_95_to_87[0x09];
10951 u8 synce_registers[0x2];
10952 u8 regs_84_to_64[0x15];
10953
10954 u8 regs_63_to_32[0x20];
10955
10956 u8 regs_31_to_0[0x20];
10957};
10958
10959struct mlx5_ifc_mcam_access_reg_bits3 {
10960 u8 regs_127_to_96[0x20];
10961
10962 u8 regs_95_to_64[0x20];
10963
10964 u8 regs_63_to_32[0x20];
10965
10966 u8 regs_31_to_3[0x1d];
10967 u8 mrtcq[0x1];
10968 u8 mtctr[0x1];
10969 u8 mtptm[0x1];
10970};
10971
10972struct mlx5_ifc_mcam_reg_bits {
10973 u8 reserved_at_0[0x8];
10974 u8 feature_group[0x8];
10975 u8 reserved_at_10[0x8];
10976 u8 access_reg_group[0x8];
10977
10978 u8 reserved_at_20[0x20];
10979
10980 union {
10981 struct mlx5_ifc_mcam_access_reg_bits access_regs;
10982 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10983 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10984 struct mlx5_ifc_mcam_access_reg_bits3 access_regs3;
10985 u8 reserved_at_0[0x80];
10986 } mng_access_reg_cap_mask;
10987
10988 u8 reserved_at_c0[0x80];
10989
10990 union {
10991 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10992 u8 reserved_at_0[0x80];
10993 } mng_feature_cap_mask;
10994
10995 u8 reserved_at_1c0[0x80];
10996};
10997
10998struct mlx5_ifc_qcam_access_reg_cap_mask {
10999 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
11000 u8 qpdpm[0x1];
11001 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
11002 u8 qdpm[0x1];
11003 u8 qpts[0x1];
11004 u8 qcap[0x1];
11005 u8 qcam_access_reg_cap_mask_0[0x1];
11006};
11007
11008struct mlx5_ifc_qcam_qos_feature_cap_mask {
11009 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
11010 u8 qpts_trust_both[0x1];
11011};
11012
11013struct mlx5_ifc_qcam_reg_bits {
11014 u8 reserved_at_0[0x8];
11015 u8 feature_group[0x8];
11016 u8 reserved_at_10[0x8];
11017 u8 access_reg_group[0x8];
11018 u8 reserved_at_20[0x20];
11019
11020 union {
11021 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
11022 u8 reserved_at_0[0x80];
11023 } qos_access_reg_cap_mask;
11024
11025 u8 reserved_at_c0[0x80];
11026
11027 union {
11028 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
11029 u8 reserved_at_0[0x80];
11030 } qos_feature_cap_mask;
11031
11032 u8 reserved_at_1c0[0x80];
11033};
11034
11035struct mlx5_ifc_core_dump_reg_bits {
11036 u8 reserved_at_0[0x18];
11037 u8 core_dump_type[0x8];
11038
11039 u8 reserved_at_20[0x30];
11040 u8 vhca_id[0x10];
11041
11042 u8 reserved_at_60[0x8];
11043 u8 qpn[0x18];
11044 u8 reserved_at_80[0x180];
11045};
11046
11047struct mlx5_ifc_pcap_reg_bits {
11048 u8 reserved_at_0[0x8];
11049 u8 local_port[0x8];
11050 u8 reserved_at_10[0x10];
11051
11052 u8 port_capability_mask[4][0x20];
11053};
11054
11055struct mlx5_ifc_paos_reg_bits {
11056 u8 swid[0x8];
11057 u8 local_port[0x8];
11058 u8 reserved_at_10[0x4];
11059 u8 admin_status[0x4];
11060 u8 reserved_at_18[0x4];
11061 u8 oper_status[0x4];
11062
11063 u8 ase[0x1];
11064 u8 ee[0x1];
11065 u8 reserved_at_22[0x1c];
11066 u8 e[0x2];
11067
11068 u8 reserved_at_40[0x40];
11069};
11070
11071struct mlx5_ifc_pamp_reg_bits {
11072 u8 reserved_at_0[0x8];
11073 u8 opamp_group[0x8];
11074 u8 reserved_at_10[0xc];
11075 u8 opamp_group_type[0x4];
11076
11077 u8 start_index[0x10];
11078 u8 reserved_at_30[0x4];
11079 u8 num_of_indices[0xc];
11080
11081 u8 index_data[18][0x10];
11082};
11083
11084struct mlx5_ifc_pcmr_reg_bits {
11085 u8 reserved_at_0[0x8];
11086 u8 local_port[0x8];
11087 u8 reserved_at_10[0x10];
11088
11089 u8 entropy_force_cap[0x1];
11090 u8 entropy_calc_cap[0x1];
11091 u8 entropy_gre_calc_cap[0x1];
11092 u8 reserved_at_23[0xf];
11093 u8 rx_ts_over_crc_cap[0x1];
11094 u8 reserved_at_33[0xb];
11095 u8 fcs_cap[0x1];
11096 u8 reserved_at_3f[0x1];
11097
11098 u8 entropy_force[0x1];
11099 u8 entropy_calc[0x1];
11100 u8 entropy_gre_calc[0x1];
11101 u8 reserved_at_43[0xf];
11102 u8 rx_ts_over_crc[0x1];
11103 u8 reserved_at_53[0xb];
11104 u8 fcs_chk[0x1];
11105 u8 reserved_at_5f[0x1];
11106};
11107
11108struct mlx5_ifc_lane_2_module_mapping_bits {
11109 u8 reserved_at_0[0x4];
11110 u8 rx_lane[0x4];
11111 u8 reserved_at_8[0x4];
11112 u8 tx_lane[0x4];
11113 u8 reserved_at_10[0x8];
11114 u8 module[0x8];
11115};
11116
11117struct mlx5_ifc_bufferx_reg_bits {
11118 u8 reserved_at_0[0x6];
11119 u8 lossy[0x1];
11120 u8 epsb[0x1];
11121 u8 reserved_at_8[0x8];
11122 u8 size[0x10];
11123
11124 u8 xoff_threshold[0x10];
11125 u8 xon_threshold[0x10];
11126};
11127
11128struct mlx5_ifc_set_node_in_bits {
11129 u8 node_description[64][0x8];
11130};
11131
11132struct mlx5_ifc_register_power_settings_bits {
11133 u8 reserved_at_0[0x18];
11134 u8 power_settings_level[0x8];
11135
11136 u8 reserved_at_20[0x60];
11137};
11138
11139struct mlx5_ifc_register_host_endianness_bits {
11140 u8 he[0x1];
11141 u8 reserved_at_1[0x1f];
11142
11143 u8 reserved_at_20[0x60];
11144};
11145
11146struct mlx5_ifc_umr_pointer_desc_argument_bits {
11147 u8 reserved_at_0[0x20];
11148
11149 u8 mkey[0x20];
11150
11151 u8 addressh_63_32[0x20];
11152
11153 u8 addressl_31_0[0x20];
11154};
11155
11156struct mlx5_ifc_ud_adrs_vector_bits {
11157 u8 dc_key[0x40];
11158
11159 u8 ext[0x1];
11160 u8 reserved_at_41[0x7];
11161 u8 destination_qp_dct[0x18];
11162
11163 u8 static_rate[0x4];
11164 u8 sl_eth_prio[0x4];
11165 u8 fl[0x1];
11166 u8 mlid[0x7];
11167 u8 rlid_udp_sport[0x10];
11168
11169 u8 reserved_at_80[0x20];
11170
11171 u8 rmac_47_16[0x20];
11172
11173 u8 rmac_15_0[0x10];
11174 u8 tclass[0x8];
11175 u8 hop_limit[0x8];
11176
11177 u8 reserved_at_e0[0x1];
11178 u8 grh[0x1];
11179 u8 reserved_at_e2[0x2];
11180 u8 src_addr_index[0x8];
11181 u8 flow_label[0x14];
11182
11183 u8 rgid_rip[16][0x8];
11184};
11185
11186struct mlx5_ifc_pages_req_event_bits {
11187 u8 reserved_at_0[0x10];
11188 u8 function_id[0x10];
11189
11190 u8 num_pages[0x20];
11191
11192 u8 reserved_at_40[0xa0];
11193};
11194
11195struct mlx5_ifc_eqe_bits {
11196 u8 reserved_at_0[0x8];
11197 u8 event_type[0x8];
11198 u8 reserved_at_10[0x8];
11199 u8 event_sub_type[0x8];
11200
11201 u8 reserved_at_20[0xe0];
11202
11203 union mlx5_ifc_event_auto_bits event_data;
11204
11205 u8 reserved_at_1e0[0x10];
11206 u8 signature[0x8];
11207 u8 reserved_at_1f8[0x7];
11208 u8 owner[0x1];
11209};
11210
11211enum {
11212 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
11213};
11214
11215struct mlx5_ifc_cmd_queue_entry_bits {
11216 u8 type[0x8];
11217 u8 reserved_at_8[0x18];
11218
11219 u8 input_length[0x20];
11220
11221 u8 input_mailbox_pointer_63_32[0x20];
11222
11223 u8 input_mailbox_pointer_31_9[0x17];
11224 u8 reserved_at_77[0x9];
11225
11226 u8 command_input_inline_data[16][0x8];
11227
11228 u8 command_output_inline_data[16][0x8];
11229
11230 u8 output_mailbox_pointer_63_32[0x20];
11231
11232 u8 output_mailbox_pointer_31_9[0x17];
11233 u8 reserved_at_1b7[0x9];
11234
11235 u8 output_length[0x20];
11236
11237 u8 token[0x8];
11238 u8 signature[0x8];
11239 u8 reserved_at_1f0[0x8];
11240 u8 status[0x7];
11241 u8 ownership[0x1];
11242};
11243
11244struct mlx5_ifc_cmd_out_bits {
11245 u8 status[0x8];
11246 u8 reserved_at_8[0x18];
11247
11248 u8 syndrome[0x20];
11249
11250 u8 command_output[0x20];
11251};
11252
11253struct mlx5_ifc_cmd_in_bits {
11254 u8 opcode[0x10];
11255 u8 reserved_at_10[0x10];
11256
11257 u8 reserved_at_20[0x10];
11258 u8 op_mod[0x10];
11259
11260 u8 command[][0x20];
11261};
11262
11263struct mlx5_ifc_cmd_if_box_bits {
11264 u8 mailbox_data[512][0x8];
11265
11266 u8 reserved_at_1000[0x180];
11267
11268 u8 next_pointer_63_32[0x20];
11269
11270 u8 next_pointer_31_10[0x16];
11271 u8 reserved_at_11b6[0xa];
11272
11273 u8 block_number[0x20];
11274
11275 u8 reserved_at_11e0[0x8];
11276 u8 token[0x8];
11277 u8 ctrl_signature[0x8];
11278 u8 signature[0x8];
11279};
11280
11281struct mlx5_ifc_mtt_bits {
11282 u8 ptag_63_32[0x20];
11283
11284 u8 ptag_31_8[0x18];
11285 u8 reserved_at_38[0x6];
11286 u8 wr_en[0x1];
11287 u8 rd_en[0x1];
11288};
11289
11290struct mlx5_ifc_query_wol_rol_out_bits {
11291 u8 status[0x8];
11292 u8 reserved_at_8[0x18];
11293
11294 u8 syndrome[0x20];
11295
11296 u8 reserved_at_40[0x10];
11297 u8 rol_mode[0x8];
11298 u8 wol_mode[0x8];
11299
11300 u8 reserved_at_60[0x20];
11301};
11302
11303struct mlx5_ifc_query_wol_rol_in_bits {
11304 u8 opcode[0x10];
11305 u8 reserved_at_10[0x10];
11306
11307 u8 reserved_at_20[0x10];
11308 u8 op_mod[0x10];
11309
11310 u8 reserved_at_40[0x40];
11311};
11312
11313struct mlx5_ifc_set_wol_rol_out_bits {
11314 u8 status[0x8];
11315 u8 reserved_at_8[0x18];
11316
11317 u8 syndrome[0x20];
11318
11319 u8 reserved_at_40[0x40];
11320};
11321
11322struct mlx5_ifc_set_wol_rol_in_bits {
11323 u8 opcode[0x10];
11324 u8 reserved_at_10[0x10];
11325
11326 u8 reserved_at_20[0x10];
11327 u8 op_mod[0x10];
11328
11329 u8 rol_mode_valid[0x1];
11330 u8 wol_mode_valid[0x1];
11331 u8 reserved_at_42[0xe];
11332 u8 rol_mode[0x8];
11333 u8 wol_mode[0x8];
11334
11335 u8 reserved_at_60[0x20];
11336};
11337
11338enum {
11339 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
11340 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
11341 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
11342 MLX5_INITIAL_SEG_NIC_INTERFACE_SW_RESET = 0x7,
11343};
11344
11345enum {
11346 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
11347 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
11348 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
11349};
11350
11351enum {
11352 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
11353 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
11354 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
11355 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
11356 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
11357 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
11358 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
11359 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
11360 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
11361 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
11362 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
11363 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PCI_POISONED_ERR = 0x12,
11364 MLX5_INITIAL_SEG_HEALTH_SYNDROME_TRUST_LOCKDOWN_ERR = 0x13,
11365};
11366
11367struct mlx5_ifc_initial_seg_bits {
11368 u8 fw_rev_minor[0x10];
11369 u8 fw_rev_major[0x10];
11370
11371 u8 cmd_interface_rev[0x10];
11372 u8 fw_rev_subminor[0x10];
11373
11374 u8 reserved_at_40[0x40];
11375
11376 u8 cmdq_phy_addr_63_32[0x20];
11377
11378 u8 cmdq_phy_addr_31_12[0x14];
11379 u8 reserved_at_b4[0x2];
11380 u8 nic_interface[0x2];
11381 u8 log_cmdq_size[0x4];
11382 u8 log_cmdq_stride[0x4];
11383
11384 u8 command_doorbell_vector[0x20];
11385
11386 u8 reserved_at_e0[0xf00];
11387
11388 u8 initializing[0x1];
11389 u8 reserved_at_fe1[0x4];
11390 u8 nic_interface_supported[0x3];
11391 u8 embedded_cpu[0x1];
11392 u8 reserved_at_fe9[0x17];
11393
11394 struct mlx5_ifc_health_buffer_bits health_buffer;
11395
11396 u8 no_dram_nic_offset[0x20];
11397
11398 u8 reserved_at_1220[0x6e40];
11399
11400 u8 reserved_at_8060[0x1f];
11401 u8 clear_int[0x1];
11402
11403 u8 health_syndrome[0x8];
11404 u8 health_counter[0x18];
11405
11406 u8 reserved_at_80a0[0x17fc0];
11407};
11408
11409struct mlx5_ifc_mtpps_reg_bits {
11410 u8 reserved_at_0[0xc];
11411 u8 cap_number_of_pps_pins[0x4];
11412 u8 reserved_at_10[0x4];
11413 u8 cap_max_num_of_pps_in_pins[0x4];
11414 u8 reserved_at_18[0x4];
11415 u8 cap_max_num_of_pps_out_pins[0x4];
11416
11417 u8 reserved_at_20[0x13];
11418 u8 cap_log_min_npps_period[0x5];
11419 u8 reserved_at_38[0x3];
11420 u8 cap_log_min_out_pulse_duration_ns[0x5];
11421
11422 u8 reserved_at_40[0x4];
11423 u8 cap_pin_3_mode[0x4];
11424 u8 reserved_at_48[0x4];
11425 u8 cap_pin_2_mode[0x4];
11426 u8 reserved_at_50[0x4];
11427 u8 cap_pin_1_mode[0x4];
11428 u8 reserved_at_58[0x4];
11429 u8 cap_pin_0_mode[0x4];
11430
11431 u8 reserved_at_60[0x4];
11432 u8 cap_pin_7_mode[0x4];
11433 u8 reserved_at_68[0x4];
11434 u8 cap_pin_6_mode[0x4];
11435 u8 reserved_at_70[0x4];
11436 u8 cap_pin_5_mode[0x4];
11437 u8 reserved_at_78[0x4];
11438 u8 cap_pin_4_mode[0x4];
11439
11440 u8 field_select[0x20];
11441 u8 reserved_at_a0[0x20];
11442
11443 u8 npps_period[0x40];
11444
11445 u8 enable[0x1];
11446 u8 reserved_at_101[0xb];
11447 u8 pattern[0x4];
11448 u8 reserved_at_110[0x4];
11449 u8 pin_mode[0x4];
11450 u8 pin[0x8];
11451
11452 u8 reserved_at_120[0x2];
11453 u8 out_pulse_duration_ns[0x1e];
11454
11455 u8 time_stamp[0x40];
11456
11457 u8 out_pulse_duration[0x10];
11458 u8 out_periodic_adjustment[0x10];
11459 u8 enhanced_out_periodic_adjustment[0x20];
11460
11461 u8 reserved_at_1c0[0x20];
11462};
11463
11464struct mlx5_ifc_mtppse_reg_bits {
11465 u8 reserved_at_0[0x18];
11466 u8 pin[0x8];
11467 u8 event_arm[0x1];
11468 u8 reserved_at_21[0x1b];
11469 u8 event_generation_mode[0x4];
11470 u8 reserved_at_40[0x40];
11471};
11472
11473struct mlx5_ifc_mcqs_reg_bits {
11474 u8 last_index_flag[0x1];
11475 u8 reserved_at_1[0x7];
11476 u8 fw_device[0x8];
11477 u8 component_index[0x10];
11478
11479 u8 reserved_at_20[0x10];
11480 u8 identifier[0x10];
11481
11482 u8 reserved_at_40[0x17];
11483 u8 component_status[0x5];
11484 u8 component_update_state[0x4];
11485
11486 u8 last_update_state_changer_type[0x4];
11487 u8 last_update_state_changer_host_id[0x4];
11488 u8 reserved_at_68[0x18];
11489};
11490
11491struct mlx5_ifc_mcqi_cap_bits {
11492 u8 supported_info_bitmask[0x20];
11493
11494 u8 component_size[0x20];
11495
11496 u8 max_component_size[0x20];
11497
11498 u8 log_mcda_word_size[0x4];
11499 u8 reserved_at_64[0xc];
11500 u8 mcda_max_write_size[0x10];
11501
11502 u8 rd_en[0x1];
11503 u8 reserved_at_81[0x1];
11504 u8 match_chip_id[0x1];
11505 u8 match_psid[0x1];
11506 u8 check_user_timestamp[0x1];
11507 u8 match_base_guid_mac[0x1];
11508 u8 reserved_at_86[0x1a];
11509};
11510
11511struct mlx5_ifc_mcqi_version_bits {
11512 u8 reserved_at_0[0x2];
11513 u8 build_time_valid[0x1];
11514 u8 user_defined_time_valid[0x1];
11515 u8 reserved_at_4[0x14];
11516 u8 version_string_length[0x8];
11517
11518 u8 version[0x20];
11519
11520 u8 build_time[0x40];
11521
11522 u8 user_defined_time[0x40];
11523
11524 u8 build_tool_version[0x20];
11525
11526 u8 reserved_at_e0[0x20];
11527
11528 u8 version_string[92][0x8];
11529};
11530
11531struct mlx5_ifc_mcqi_activation_method_bits {
11532 u8 pending_server_ac_power_cycle[0x1];
11533 u8 pending_server_dc_power_cycle[0x1];
11534 u8 pending_server_reboot[0x1];
11535 u8 pending_fw_reset[0x1];
11536 u8 auto_activate[0x1];
11537 u8 all_hosts_sync[0x1];
11538 u8 device_hw_reset[0x1];
11539 u8 reserved_at_7[0x19];
11540};
11541
11542union mlx5_ifc_mcqi_reg_data_bits {
11543 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
11544 struct mlx5_ifc_mcqi_version_bits mcqi_version;
11545 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
11546};
11547
11548struct mlx5_ifc_mcqi_reg_bits {
11549 u8 read_pending_component[0x1];
11550 u8 reserved_at_1[0xf];
11551 u8 component_index[0x10];
11552
11553 u8 reserved_at_20[0x20];
11554
11555 u8 reserved_at_40[0x1b];
11556 u8 info_type[0x5];
11557
11558 u8 info_size[0x20];
11559
11560 u8 offset[0x20];
11561
11562 u8 reserved_at_a0[0x10];
11563 u8 data_size[0x10];
11564
11565 union mlx5_ifc_mcqi_reg_data_bits data[];
11566};
11567
11568struct mlx5_ifc_mcc_reg_bits {
11569 u8 reserved_at_0[0x4];
11570 u8 time_elapsed_since_last_cmd[0xc];
11571 u8 reserved_at_10[0x8];
11572 u8 instruction[0x8];
11573
11574 u8 reserved_at_20[0x10];
11575 u8 component_index[0x10];
11576
11577 u8 reserved_at_40[0x8];
11578 u8 update_handle[0x18];
11579
11580 u8 handle_owner_type[0x4];
11581 u8 handle_owner_host_id[0x4];
11582 u8 reserved_at_68[0x1];
11583 u8 control_progress[0x7];
11584 u8 error_code[0x8];
11585 u8 reserved_at_78[0x4];
11586 u8 control_state[0x4];
11587
11588 u8 component_size[0x20];
11589
11590 u8 reserved_at_a0[0x60];
11591};
11592
11593struct mlx5_ifc_mcda_reg_bits {
11594 u8 reserved_at_0[0x8];
11595 u8 update_handle[0x18];
11596
11597 u8 offset[0x20];
11598
11599 u8 reserved_at_40[0x10];
11600 u8 size[0x10];
11601
11602 u8 reserved_at_60[0x20];
11603
11604 u8 data[][0x20];
11605};
11606
11607enum {
11608 MLX5_MFRL_REG_PCI_RESET_METHOD_LINK_TOGGLE = 0,
11609 MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET = 1,
11610};
11611
11612enum {
11613 MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
11614 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
11615 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
11616 MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
11617 MLX5_MFRL_REG_RESET_STATE_NACK = 4,
11618 MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
11619};
11620
11621enum {
11622 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
11623 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
11624};
11625
11626enum {
11627 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
11628 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
11629 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
11630};
11631
11632struct mlx5_ifc_mfrl_reg_bits {
11633 u8 reserved_at_0[0x20];
11634
11635 u8 reserved_at_20[0x2];
11636 u8 pci_sync_for_fw_update_start[0x1];
11637 u8 pci_sync_for_fw_update_resp[0x2];
11638 u8 rst_type_sel[0x3];
11639 u8 pci_reset_req_method[0x3];
11640 u8 reserved_at_2b[0x1];
11641 u8 reset_state[0x4];
11642 u8 reset_type[0x8];
11643 u8 reset_level[0x8];
11644};
11645
11646struct mlx5_ifc_mirc_reg_bits {
11647 u8 reserved_at_0[0x18];
11648 u8 status_code[0x8];
11649
11650 u8 reserved_at_20[0x20];
11651};
11652
11653struct mlx5_ifc_pddr_monitor_opcode_bits {
11654 u8 reserved_at_0[0x10];
11655 u8 monitor_opcode[0x10];
11656};
11657
11658union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
11659 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11660 u8 reserved_at_0[0x20];
11661};
11662
11663enum {
11664 /* Monitor opcodes */
11665 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
11666};
11667
11668struct mlx5_ifc_pddr_troubleshooting_page_bits {
11669 u8 reserved_at_0[0x10];
11670 u8 group_opcode[0x10];
11671
11672 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
11673
11674 u8 reserved_at_40[0x20];
11675
11676 u8 status_message[59][0x20];
11677};
11678
11679union mlx5_ifc_pddr_reg_page_data_auto_bits {
11680 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11681 u8 reserved_at_0[0x7c0];
11682};
11683
11684enum {
11685 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1,
11686};
11687
11688struct mlx5_ifc_pddr_reg_bits {
11689 u8 reserved_at_0[0x8];
11690 u8 local_port[0x8];
11691 u8 pnat[0x2];
11692 u8 reserved_at_12[0xe];
11693
11694 u8 reserved_at_20[0x18];
11695 u8 page_select[0x8];
11696
11697 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
11698};
11699
11700struct mlx5_ifc_mrtc_reg_bits {
11701 u8 time_synced[0x1];
11702 u8 reserved_at_1[0x1f];
11703
11704 u8 reserved_at_20[0x20];
11705
11706 u8 time_h[0x20];
11707
11708 u8 time_l[0x20];
11709};
11710
11711struct mlx5_ifc_mtcap_reg_bits {
11712 u8 reserved_at_0[0x19];
11713 u8 sensor_count[0x7];
11714
11715 u8 reserved_at_20[0x20];
11716
11717 u8 sensor_map[0x40];
11718};
11719
11720struct mlx5_ifc_mtmp_reg_bits {
11721 u8 reserved_at_0[0x14];
11722 u8 sensor_index[0xc];
11723
11724 u8 reserved_at_20[0x10];
11725 u8 temperature[0x10];
11726
11727 u8 mte[0x1];
11728 u8 mtr[0x1];
11729 u8 reserved_at_42[0xe];
11730 u8 max_temperature[0x10];
11731
11732 u8 tee[0x2];
11733 u8 reserved_at_62[0xe];
11734 u8 temp_threshold_hi[0x10];
11735
11736 u8 reserved_at_80[0x10];
11737 u8 temp_threshold_lo[0x10];
11738
11739 u8 reserved_at_a0[0x20];
11740
11741 u8 sensor_name_hi[0x20];
11742 u8 sensor_name_lo[0x20];
11743};
11744
11745struct mlx5_ifc_mtptm_reg_bits {
11746 u8 reserved_at_0[0x10];
11747 u8 psta[0x1];
11748 u8 reserved_at_11[0xf];
11749
11750 u8 reserved_at_20[0x60];
11751};
11752
11753enum {
11754 MLX5_MTCTR_REQUEST_NOP = 0x0,
11755 MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1,
11756 MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2,
11757 MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3,
11758};
11759
11760struct mlx5_ifc_mtctr_reg_bits {
11761 u8 first_clock_timestamp_request[0x8];
11762 u8 second_clock_timestamp_request[0x8];
11763 u8 reserved_at_10[0x10];
11764
11765 u8 first_clock_valid[0x1];
11766 u8 second_clock_valid[0x1];
11767 u8 reserved_at_22[0x1e];
11768
11769 u8 first_clock_timestamp[0x40];
11770 u8 second_clock_timestamp[0x40];
11771};
11772
11773struct mlx5_ifc_bin_range_layout_bits {
11774 u8 reserved_at_0[0xa];
11775 u8 high_val[0x6];
11776 u8 reserved_at_10[0xa];
11777 u8 low_val[0x6];
11778};
11779
11780struct mlx5_ifc_pphcr_reg_bits {
11781 u8 active_hist_type[0x4];
11782 u8 reserved_at_4[0x4];
11783 u8 local_port[0x8];
11784 u8 reserved_at_10[0x10];
11785
11786 u8 reserved_at_20[0x8];
11787 u8 num_of_bins[0x8];
11788 u8 reserved_at_30[0x10];
11789
11790 u8 reserved_at_40[0x40];
11791
11792 struct mlx5_ifc_bin_range_layout_bits bin_range[16];
11793};
11794
11795union mlx5_ifc_ports_control_registers_document_bits {
11796 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
11797 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
11798 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
11799 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
11800 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
11801 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
11802 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
11803 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
11804 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
11805 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
11806 struct mlx5_ifc_pamp_reg_bits pamp_reg;
11807 struct mlx5_ifc_paos_reg_bits paos_reg;
11808 struct mlx5_ifc_pcap_reg_bits pcap_reg;
11809 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
11810 struct mlx5_ifc_pddr_reg_bits pddr_reg;
11811 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
11812 struct mlx5_ifc_peir_reg_bits peir_reg;
11813 struct mlx5_ifc_pelc_reg_bits pelc_reg;
11814 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
11815 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
11816 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
11817 struct mlx5_ifc_pifr_reg_bits pifr_reg;
11818 struct mlx5_ifc_pipg_reg_bits pipg_reg;
11819 struct mlx5_ifc_plbf_reg_bits plbf_reg;
11820 struct mlx5_ifc_plib_reg_bits plib_reg;
11821 struct mlx5_ifc_plpc_reg_bits plpc_reg;
11822 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
11823 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
11824 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
11825 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
11826 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
11827 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
11828 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
11829 struct mlx5_ifc_ppad_reg_bits ppad_reg;
11830 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
11831 struct mlx5_ifc_mpein_reg_bits mpein_reg;
11832 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
11833 struct mlx5_ifc_pplm_reg_bits pplm_reg;
11834 struct mlx5_ifc_pplr_reg_bits pplr_reg;
11835 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
11836 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
11837 struct mlx5_ifc_pspa_reg_bits pspa_reg;
11838 struct mlx5_ifc_ptas_reg_bits ptas_reg;
11839 struct mlx5_ifc_ptys_reg_bits ptys_reg;
11840 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
11841 struct mlx5_ifc_pude_reg_bits pude_reg;
11842 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
11843 struct mlx5_ifc_slrg_reg_bits slrg_reg;
11844 struct mlx5_ifc_sltp_reg_bits sltp_reg;
11845 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11846 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11847 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11848 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11849 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11850 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11851 struct mlx5_ifc_mcc_reg_bits mcc_reg;
11852 struct mlx5_ifc_mcda_reg_bits mcda_reg;
11853 struct mlx5_ifc_mirc_reg_bits mirc_reg;
11854 struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11855 struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11856 struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11857 struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11858 struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11859 struct mlx5_ifc_mtptm_reg_bits mtptm_reg;
11860 struct mlx5_ifc_mtctr_reg_bits mtctr_reg;
11861 struct mlx5_ifc_pphcr_reg_bits pphcr_reg;
11862 u8 reserved_at_0[0x60e0];
11863};
11864
11865union mlx5_ifc_debug_enhancements_document_bits {
11866 struct mlx5_ifc_health_buffer_bits health_buffer;
11867 u8 reserved_at_0[0x200];
11868};
11869
11870union mlx5_ifc_uplink_pci_interface_document_bits {
11871 struct mlx5_ifc_initial_seg_bits initial_seg;
11872 u8 reserved_at_0[0x20060];
11873};
11874
11875struct mlx5_ifc_set_flow_table_root_out_bits {
11876 u8 status[0x8];
11877 u8 reserved_at_8[0x18];
11878
11879 u8 syndrome[0x20];
11880
11881 u8 reserved_at_40[0x40];
11882};
11883
11884struct mlx5_ifc_set_flow_table_root_in_bits {
11885 u8 opcode[0x10];
11886 u8 reserved_at_10[0x10];
11887
11888 u8 reserved_at_20[0x10];
11889 u8 op_mod[0x10];
11890
11891 u8 other_vport[0x1];
11892 u8 other_eswitch[0x1];
11893 u8 reserved_at_42[0xe];
11894 u8 vport_number[0x10];
11895
11896 u8 reserved_at_60[0x10];
11897 u8 eswitch_owner_vhca_id[0x10];
11898
11899 u8 table_type[0x8];
11900 u8 reserved_at_88[0x7];
11901 u8 table_of_other_vport[0x1];
11902 u8 table_vport_number[0x10];
11903
11904 u8 reserved_at_a0[0x8];
11905 u8 table_id[0x18];
11906
11907 u8 reserved_at_c0[0x8];
11908 u8 underlay_qpn[0x18];
11909 u8 table_eswitch_owner_vhca_id_valid[0x1];
11910 u8 reserved_at_e1[0xf];
11911 u8 table_eswitch_owner_vhca_id[0x10];
11912 u8 reserved_at_100[0x100];
11913};
11914
11915enum {
11916 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
11917 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11918};
11919
11920struct mlx5_ifc_modify_flow_table_out_bits {
11921 u8 status[0x8];
11922 u8 reserved_at_8[0x18];
11923
11924 u8 syndrome[0x20];
11925
11926 u8 reserved_at_40[0x40];
11927};
11928
11929struct mlx5_ifc_modify_flow_table_in_bits {
11930 u8 opcode[0x10];
11931 u8 reserved_at_10[0x10];
11932
11933 u8 reserved_at_20[0x10];
11934 u8 op_mod[0x10];
11935
11936 u8 other_vport[0x1];
11937 u8 other_eswitch[0x1];
11938 u8 reserved_at_42[0xe];
11939 u8 vport_number[0x10];
11940
11941 u8 reserved_at_60[0x10];
11942 u8 modify_field_select[0x10];
11943
11944 u8 table_type[0x8];
11945 u8 reserved_at_88[0x8];
11946 u8 eswitch_owner_vhca_id[0x10];
11947
11948 u8 reserved_at_a0[0x8];
11949 u8 table_id[0x18];
11950
11951 struct mlx5_ifc_flow_table_context_bits flow_table_context;
11952};
11953
11954struct mlx5_ifc_ets_tcn_config_reg_bits {
11955 u8 g[0x1];
11956 u8 b[0x1];
11957 u8 r[0x1];
11958 u8 reserved_at_3[0x9];
11959 u8 group[0x4];
11960 u8 reserved_at_10[0x9];
11961 u8 bw_allocation[0x7];
11962
11963 u8 reserved_at_20[0xc];
11964 u8 max_bw_units[0x4];
11965 u8 reserved_at_30[0x8];
11966 u8 max_bw_value[0x8];
11967};
11968
11969struct mlx5_ifc_ets_global_config_reg_bits {
11970 u8 reserved_at_0[0x2];
11971 u8 r[0x1];
11972 u8 reserved_at_3[0x1d];
11973
11974 u8 reserved_at_20[0xc];
11975 u8 max_bw_units[0x4];
11976 u8 reserved_at_30[0x8];
11977 u8 max_bw_value[0x8];
11978};
11979
11980struct mlx5_ifc_qetc_reg_bits {
11981 u8 reserved_at_0[0x8];
11982 u8 port_number[0x8];
11983 u8 reserved_at_10[0x30];
11984
11985 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
11986 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11987};
11988
11989struct mlx5_ifc_qpdpm_dscp_reg_bits {
11990 u8 e[0x1];
11991 u8 reserved_at_01[0x0b];
11992 u8 prio[0x04];
11993};
11994
11995struct mlx5_ifc_qpdpm_reg_bits {
11996 u8 reserved_at_0[0x8];
11997 u8 local_port[0x8];
11998 u8 reserved_at_10[0x10];
11999 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
12000};
12001
12002struct mlx5_ifc_qpts_reg_bits {
12003 u8 reserved_at_0[0x8];
12004 u8 local_port[0x8];
12005 u8 reserved_at_10[0x2d];
12006 u8 trust_state[0x3];
12007};
12008
12009struct mlx5_ifc_pptb_reg_bits {
12010 u8 reserved_at_0[0x2];
12011 u8 mm[0x2];
12012 u8 reserved_at_4[0x4];
12013 u8 local_port[0x8];
12014 u8 reserved_at_10[0x6];
12015 u8 cm[0x1];
12016 u8 um[0x1];
12017 u8 pm[0x8];
12018
12019 u8 prio_x_buff[0x20];
12020
12021 u8 pm_msb[0x8];
12022 u8 reserved_at_48[0x10];
12023 u8 ctrl_buff[0x4];
12024 u8 untagged_buff[0x4];
12025};
12026
12027struct mlx5_ifc_sbcam_reg_bits {
12028 u8 reserved_at_0[0x8];
12029 u8 feature_group[0x8];
12030 u8 reserved_at_10[0x8];
12031 u8 access_reg_group[0x8];
12032
12033 u8 reserved_at_20[0x20];
12034
12035 u8 sb_access_reg_cap_mask[4][0x20];
12036
12037 u8 reserved_at_c0[0x80];
12038
12039 u8 sb_feature_cap_mask[4][0x20];
12040
12041 u8 reserved_at_1c0[0x40];
12042
12043 u8 cap_total_buffer_size[0x20];
12044
12045 u8 cap_cell_size[0x10];
12046 u8 cap_max_pg_buffers[0x8];
12047 u8 cap_num_pool_supported[0x8];
12048
12049 u8 reserved_at_240[0x8];
12050 u8 cap_sbsr_stat_size[0x8];
12051 u8 cap_max_tclass_data[0x8];
12052 u8 cap_max_cpu_ingress_tclass_sb[0x8];
12053};
12054
12055struct mlx5_ifc_pbmc_reg_bits {
12056 u8 reserved_at_0[0x8];
12057 u8 local_port[0x8];
12058 u8 reserved_at_10[0x10];
12059
12060 u8 xoff_timer_value[0x10];
12061 u8 xoff_refresh[0x10];
12062
12063 u8 reserved_at_40[0x9];
12064 u8 fullness_threshold[0x7];
12065 u8 port_buffer_size[0x10];
12066
12067 struct mlx5_ifc_bufferx_reg_bits buffer[10];
12068
12069 u8 reserved_at_2e0[0x80];
12070};
12071
12072struct mlx5_ifc_sbpr_reg_bits {
12073 u8 desc[0x1];
12074 u8 snap[0x1];
12075 u8 reserved_at_2[0x4];
12076 u8 dir[0x2];
12077 u8 reserved_at_8[0x14];
12078 u8 pool[0x4];
12079
12080 u8 infi_size[0x1];
12081 u8 reserved_at_21[0x7];
12082 u8 size[0x18];
12083
12084 u8 reserved_at_40[0x1c];
12085 u8 mode[0x4];
12086
12087 u8 reserved_at_60[0x8];
12088 u8 buff_occupancy[0x18];
12089
12090 u8 clr[0x1];
12091 u8 reserved_at_81[0x7];
12092 u8 max_buff_occupancy[0x18];
12093
12094 u8 reserved_at_a0[0x8];
12095 u8 ext_buff_occupancy[0x18];
12096};
12097
12098struct mlx5_ifc_sbcm_reg_bits {
12099 u8 desc[0x1];
12100 u8 snap[0x1];
12101 u8 reserved_at_2[0x6];
12102 u8 local_port[0x8];
12103 u8 pnat[0x2];
12104 u8 pg_buff[0x6];
12105 u8 reserved_at_18[0x6];
12106 u8 dir[0x2];
12107
12108 u8 reserved_at_20[0x1f];
12109 u8 exc[0x1];
12110
12111 u8 reserved_at_40[0x40];
12112
12113 u8 reserved_at_80[0x8];
12114 u8 buff_occupancy[0x18];
12115
12116 u8 clr[0x1];
12117 u8 reserved_at_a1[0x7];
12118 u8 max_buff_occupancy[0x18];
12119
12120 u8 reserved_at_c0[0x8];
12121 u8 min_buff[0x18];
12122
12123 u8 infi_max[0x1];
12124 u8 reserved_at_e1[0x7];
12125 u8 max_buff[0x18];
12126
12127 u8 reserved_at_100[0x20];
12128
12129 u8 reserved_at_120[0x1c];
12130 u8 pool[0x4];
12131};
12132
12133struct mlx5_ifc_qtct_reg_bits {
12134 u8 reserved_at_0[0x8];
12135 u8 port_number[0x8];
12136 u8 reserved_at_10[0xd];
12137 u8 prio[0x3];
12138
12139 u8 reserved_at_20[0x1d];
12140 u8 tclass[0x3];
12141};
12142
12143struct mlx5_ifc_mcia_reg_bits {
12144 u8 l[0x1];
12145 u8 reserved_at_1[0x7];
12146 u8 module[0x8];
12147 u8 reserved_at_10[0x8];
12148 u8 status[0x8];
12149
12150 u8 i2c_device_address[0x8];
12151 u8 page_number[0x8];
12152 u8 device_address[0x10];
12153
12154 u8 reserved_at_40[0x10];
12155 u8 size[0x10];
12156
12157 u8 reserved_at_60[0x20];
12158
12159 u8 dword_0[0x20];
12160 u8 dword_1[0x20];
12161 u8 dword_2[0x20];
12162 u8 dword_3[0x20];
12163 u8 dword_4[0x20];
12164 u8 dword_5[0x20];
12165 u8 dword_6[0x20];
12166 u8 dword_7[0x20];
12167 u8 dword_8[0x20];
12168 u8 dword_9[0x20];
12169 u8 dword_10[0x20];
12170 u8 dword_11[0x20];
12171};
12172
12173struct mlx5_ifc_dcbx_param_bits {
12174 u8 dcbx_cee_cap[0x1];
12175 u8 dcbx_ieee_cap[0x1];
12176 u8 dcbx_standby_cap[0x1];
12177 u8 reserved_at_3[0x5];
12178 u8 port_number[0x8];
12179 u8 reserved_at_10[0xa];
12180 u8 max_application_table_size[6];
12181 u8 reserved_at_20[0x15];
12182 u8 version_oper[0x3];
12183 u8 reserved_at_38[5];
12184 u8 version_admin[0x3];
12185 u8 willing_admin[0x1];
12186 u8 reserved_at_41[0x3];
12187 u8 pfc_cap_oper[0x4];
12188 u8 reserved_at_48[0x4];
12189 u8 pfc_cap_admin[0x4];
12190 u8 reserved_at_50[0x4];
12191 u8 num_of_tc_oper[0x4];
12192 u8 reserved_at_58[0x4];
12193 u8 num_of_tc_admin[0x4];
12194 u8 remote_willing[0x1];
12195 u8 reserved_at_61[3];
12196 u8 remote_pfc_cap[4];
12197 u8 reserved_at_68[0x14];
12198 u8 remote_num_of_tc[0x4];
12199 u8 reserved_at_80[0x18];
12200 u8 error[0x8];
12201 u8 reserved_at_a0[0x160];
12202};
12203
12204enum {
12205 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
12206 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
12207 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
12208};
12209
12210struct mlx5_ifc_lagc_bits {
12211 u8 fdb_selection_mode[0x1];
12212 u8 reserved_at_1[0x14];
12213 u8 port_select_mode[0x3];
12214 u8 reserved_at_18[0x5];
12215 u8 lag_state[0x3];
12216
12217 u8 reserved_at_20[0xc];
12218 u8 active_port[0x4];
12219 u8 reserved_at_30[0x4];
12220 u8 tx_remap_affinity_2[0x4];
12221 u8 reserved_at_38[0x4];
12222 u8 tx_remap_affinity_1[0x4];
12223};
12224
12225struct mlx5_ifc_create_lag_out_bits {
12226 u8 status[0x8];
12227 u8 reserved_at_8[0x18];
12228
12229 u8 syndrome[0x20];
12230
12231 u8 reserved_at_40[0x40];
12232};
12233
12234struct mlx5_ifc_create_lag_in_bits {
12235 u8 opcode[0x10];
12236 u8 reserved_at_10[0x10];
12237
12238 u8 reserved_at_20[0x10];
12239 u8 op_mod[0x10];
12240
12241 struct mlx5_ifc_lagc_bits ctx;
12242};
12243
12244struct mlx5_ifc_modify_lag_out_bits {
12245 u8 status[0x8];
12246 u8 reserved_at_8[0x18];
12247
12248 u8 syndrome[0x20];
12249
12250 u8 reserved_at_40[0x40];
12251};
12252
12253struct mlx5_ifc_modify_lag_in_bits {
12254 u8 opcode[0x10];
12255 u8 reserved_at_10[0x10];
12256
12257 u8 reserved_at_20[0x10];
12258 u8 op_mod[0x10];
12259
12260 u8 reserved_at_40[0x20];
12261 u8 field_select[0x20];
12262
12263 struct mlx5_ifc_lagc_bits ctx;
12264};
12265
12266struct mlx5_ifc_query_lag_out_bits {
12267 u8 status[0x8];
12268 u8 reserved_at_8[0x18];
12269
12270 u8 syndrome[0x20];
12271
12272 struct mlx5_ifc_lagc_bits ctx;
12273};
12274
12275struct mlx5_ifc_query_lag_in_bits {
12276 u8 opcode[0x10];
12277 u8 reserved_at_10[0x10];
12278
12279 u8 reserved_at_20[0x10];
12280 u8 op_mod[0x10];
12281
12282 u8 reserved_at_40[0x40];
12283};
12284
12285struct mlx5_ifc_destroy_lag_out_bits {
12286 u8 status[0x8];
12287 u8 reserved_at_8[0x18];
12288
12289 u8 syndrome[0x20];
12290
12291 u8 reserved_at_40[0x40];
12292};
12293
12294struct mlx5_ifc_destroy_lag_in_bits {
12295 u8 opcode[0x10];
12296 u8 reserved_at_10[0x10];
12297
12298 u8 reserved_at_20[0x10];
12299 u8 op_mod[0x10];
12300
12301 u8 reserved_at_40[0x40];
12302};
12303
12304struct mlx5_ifc_create_vport_lag_out_bits {
12305 u8 status[0x8];
12306 u8 reserved_at_8[0x18];
12307
12308 u8 syndrome[0x20];
12309
12310 u8 reserved_at_40[0x40];
12311};
12312
12313struct mlx5_ifc_create_vport_lag_in_bits {
12314 u8 opcode[0x10];
12315 u8 reserved_at_10[0x10];
12316
12317 u8 reserved_at_20[0x10];
12318 u8 op_mod[0x10];
12319
12320 u8 reserved_at_40[0x40];
12321};
12322
12323struct mlx5_ifc_destroy_vport_lag_out_bits {
12324 u8 status[0x8];
12325 u8 reserved_at_8[0x18];
12326
12327 u8 syndrome[0x20];
12328
12329 u8 reserved_at_40[0x40];
12330};
12331
12332struct mlx5_ifc_destroy_vport_lag_in_bits {
12333 u8 opcode[0x10];
12334 u8 reserved_at_10[0x10];
12335
12336 u8 reserved_at_20[0x10];
12337 u8 op_mod[0x10];
12338
12339 u8 reserved_at_40[0x40];
12340};
12341
12342enum {
12343 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
12344 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
12345};
12346
12347struct mlx5_ifc_modify_memic_in_bits {
12348 u8 opcode[0x10];
12349 u8 uid[0x10];
12350
12351 u8 reserved_at_20[0x10];
12352 u8 op_mod[0x10];
12353
12354 u8 reserved_at_40[0x20];
12355
12356 u8 reserved_at_60[0x18];
12357 u8 memic_operation_type[0x8];
12358
12359 u8 memic_start_addr[0x40];
12360
12361 u8 reserved_at_c0[0x140];
12362};
12363
12364struct mlx5_ifc_modify_memic_out_bits {
12365 u8 status[0x8];
12366 u8 reserved_at_8[0x18];
12367
12368 u8 syndrome[0x20];
12369
12370 u8 reserved_at_40[0x40];
12371
12372 u8 memic_operation_addr[0x40];
12373
12374 u8 reserved_at_c0[0x140];
12375};
12376
12377struct mlx5_ifc_alloc_memic_in_bits {
12378 u8 opcode[0x10];
12379 u8 reserved_at_10[0x10];
12380
12381 u8 reserved_at_20[0x10];
12382 u8 op_mod[0x10];
12383
12384 u8 reserved_at_30[0x20];
12385
12386 u8 reserved_at_40[0x18];
12387 u8 log_memic_addr_alignment[0x8];
12388
12389 u8 range_start_addr[0x40];
12390
12391 u8 range_size[0x20];
12392
12393 u8 memic_size[0x20];
12394};
12395
12396struct mlx5_ifc_alloc_memic_out_bits {
12397 u8 status[0x8];
12398 u8 reserved_at_8[0x18];
12399
12400 u8 syndrome[0x20];
12401
12402 u8 memic_start_addr[0x40];
12403};
12404
12405struct mlx5_ifc_dealloc_memic_in_bits {
12406 u8 opcode[0x10];
12407 u8 reserved_at_10[0x10];
12408
12409 u8 reserved_at_20[0x10];
12410 u8 op_mod[0x10];
12411
12412 u8 reserved_at_40[0x40];
12413
12414 u8 memic_start_addr[0x40];
12415
12416 u8 memic_size[0x20];
12417
12418 u8 reserved_at_e0[0x20];
12419};
12420
12421struct mlx5_ifc_dealloc_memic_out_bits {
12422 u8 status[0x8];
12423 u8 reserved_at_8[0x18];
12424
12425 u8 syndrome[0x20];
12426
12427 u8 reserved_at_40[0x40];
12428};
12429
12430struct mlx5_ifc_umem_bits {
12431 u8 reserved_at_0[0x80];
12432
12433 u8 ats[0x1];
12434 u8 reserved_at_81[0x1a];
12435 u8 log_page_size[0x5];
12436
12437 u8 page_offset[0x20];
12438
12439 u8 num_of_mtt[0x40];
12440
12441 struct mlx5_ifc_mtt_bits mtt[];
12442};
12443
12444struct mlx5_ifc_uctx_bits {
12445 u8 cap[0x20];
12446
12447 u8 reserved_at_20[0x160];
12448};
12449
12450struct mlx5_ifc_sw_icm_bits {
12451 u8 modify_field_select[0x40];
12452
12453 u8 reserved_at_40[0x18];
12454 u8 log_sw_icm_size[0x8];
12455
12456 u8 reserved_at_60[0x20];
12457
12458 u8 sw_icm_start_addr[0x40];
12459
12460 u8 reserved_at_c0[0x140];
12461};
12462
12463struct mlx5_ifc_geneve_tlv_option_bits {
12464 u8 modify_field_select[0x40];
12465
12466 u8 reserved_at_40[0x18];
12467 u8 geneve_option_fte_index[0x8];
12468
12469 u8 option_class[0x10];
12470 u8 option_type[0x8];
12471 u8 reserved_at_78[0x3];
12472 u8 option_data_length[0x5];
12473
12474 u8 reserved_at_80[0x180];
12475};
12476
12477struct mlx5_ifc_create_umem_in_bits {
12478 u8 opcode[0x10];
12479 u8 uid[0x10];
12480
12481 u8 reserved_at_20[0x10];
12482 u8 op_mod[0x10];
12483
12484 u8 reserved_at_40[0x40];
12485
12486 struct mlx5_ifc_umem_bits umem;
12487};
12488
12489struct mlx5_ifc_create_umem_out_bits {
12490 u8 status[0x8];
12491 u8 reserved_at_8[0x18];
12492
12493 u8 syndrome[0x20];
12494
12495 u8 reserved_at_40[0x8];
12496 u8 umem_id[0x18];
12497
12498 u8 reserved_at_60[0x20];
12499};
12500
12501struct mlx5_ifc_destroy_umem_in_bits {
12502 u8 opcode[0x10];
12503 u8 uid[0x10];
12504
12505 u8 reserved_at_20[0x10];
12506 u8 op_mod[0x10];
12507
12508 u8 reserved_at_40[0x8];
12509 u8 umem_id[0x18];
12510
12511 u8 reserved_at_60[0x20];
12512};
12513
12514struct mlx5_ifc_destroy_umem_out_bits {
12515 u8 status[0x8];
12516 u8 reserved_at_8[0x18];
12517
12518 u8 syndrome[0x20];
12519
12520 u8 reserved_at_40[0x40];
12521};
12522
12523struct mlx5_ifc_create_uctx_in_bits {
12524 u8 opcode[0x10];
12525 u8 reserved_at_10[0x10];
12526
12527 u8 reserved_at_20[0x10];
12528 u8 op_mod[0x10];
12529
12530 u8 reserved_at_40[0x40];
12531
12532 struct mlx5_ifc_uctx_bits uctx;
12533};
12534
12535struct mlx5_ifc_create_uctx_out_bits {
12536 u8 status[0x8];
12537 u8 reserved_at_8[0x18];
12538
12539 u8 syndrome[0x20];
12540
12541 u8 reserved_at_40[0x10];
12542 u8 uid[0x10];
12543
12544 u8 reserved_at_60[0x20];
12545};
12546
12547struct mlx5_ifc_destroy_uctx_in_bits {
12548 u8 opcode[0x10];
12549 u8 reserved_at_10[0x10];
12550
12551 u8 reserved_at_20[0x10];
12552 u8 op_mod[0x10];
12553
12554 u8 reserved_at_40[0x10];
12555 u8 uid[0x10];
12556
12557 u8 reserved_at_60[0x20];
12558};
12559
12560struct mlx5_ifc_destroy_uctx_out_bits {
12561 u8 status[0x8];
12562 u8 reserved_at_8[0x18];
12563
12564 u8 syndrome[0x20];
12565
12566 u8 reserved_at_40[0x40];
12567};
12568
12569struct mlx5_ifc_create_sw_icm_in_bits {
12570 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12571 struct mlx5_ifc_sw_icm_bits sw_icm;
12572};
12573
12574struct mlx5_ifc_create_geneve_tlv_option_in_bits {
12575 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12576 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
12577};
12578
12579struct mlx5_ifc_mtrc_string_db_param_bits {
12580 u8 string_db_base_address[0x20];
12581
12582 u8 reserved_at_20[0x8];
12583 u8 string_db_size[0x18];
12584};
12585
12586struct mlx5_ifc_mtrc_cap_bits {
12587 u8 trace_owner[0x1];
12588 u8 trace_to_memory[0x1];
12589 u8 reserved_at_2[0x4];
12590 u8 trc_ver[0x2];
12591 u8 reserved_at_8[0x14];
12592 u8 num_string_db[0x4];
12593
12594 u8 first_string_trace[0x8];
12595 u8 num_string_trace[0x8];
12596 u8 reserved_at_30[0x28];
12597
12598 u8 log_max_trace_buffer_size[0x8];
12599
12600 u8 reserved_at_60[0x20];
12601
12602 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
12603
12604 u8 reserved_at_280[0x180];
12605};
12606
12607struct mlx5_ifc_mtrc_conf_bits {
12608 u8 reserved_at_0[0x1c];
12609 u8 trace_mode[0x4];
12610 u8 reserved_at_20[0x18];
12611 u8 log_trace_buffer_size[0x8];
12612 u8 trace_mkey[0x20];
12613 u8 reserved_at_60[0x3a0];
12614};
12615
12616struct mlx5_ifc_mtrc_stdb_bits {
12617 u8 string_db_index[0x4];
12618 u8 reserved_at_4[0x4];
12619 u8 read_size[0x18];
12620 u8 start_offset[0x20];
12621 u8 string_db_data[];
12622};
12623
12624struct mlx5_ifc_mtrc_ctrl_bits {
12625 u8 trace_status[0x2];
12626 u8 reserved_at_2[0x2];
12627 u8 arm_event[0x1];
12628 u8 reserved_at_5[0xb];
12629 u8 modify_field_select[0x10];
12630 u8 reserved_at_20[0x2b];
12631 u8 current_timestamp52_32[0x15];
12632 u8 current_timestamp31_0[0x20];
12633 u8 reserved_at_80[0x180];
12634};
12635
12636struct mlx5_ifc_host_params_context_bits {
12637 u8 host_number[0x8];
12638 u8 reserved_at_8[0x5];
12639 u8 host_pf_not_exist[0x1];
12640 u8 reserved_at_14[0x1];
12641 u8 host_pf_disabled[0x1];
12642 u8 host_num_of_vfs[0x10];
12643
12644 u8 host_total_vfs[0x10];
12645 u8 host_pci_bus[0x10];
12646
12647 u8 reserved_at_40[0x10];
12648 u8 host_pci_device[0x10];
12649
12650 u8 reserved_at_60[0x10];
12651 u8 host_pci_function[0x10];
12652
12653 u8 reserved_at_80[0x180];
12654};
12655
12656struct mlx5_ifc_query_esw_functions_in_bits {
12657 u8 opcode[0x10];
12658 u8 reserved_at_10[0x10];
12659
12660 u8 reserved_at_20[0x10];
12661 u8 op_mod[0x10];
12662
12663 u8 reserved_at_40[0x40];
12664};
12665
12666struct mlx5_ifc_query_esw_functions_out_bits {
12667 u8 status[0x8];
12668 u8 reserved_at_8[0x18];
12669
12670 u8 syndrome[0x20];
12671
12672 u8 reserved_at_40[0x40];
12673
12674 struct mlx5_ifc_host_params_context_bits host_params_context;
12675
12676 u8 reserved_at_280[0x180];
12677 u8 host_sf_enable[][0x40];
12678};
12679
12680struct mlx5_ifc_sf_partition_bits {
12681 u8 reserved_at_0[0x10];
12682 u8 log_num_sf[0x8];
12683 u8 log_sf_bar_size[0x8];
12684};
12685
12686struct mlx5_ifc_query_sf_partitions_out_bits {
12687 u8 status[0x8];
12688 u8 reserved_at_8[0x18];
12689
12690 u8 syndrome[0x20];
12691
12692 u8 reserved_at_40[0x18];
12693 u8 num_sf_partitions[0x8];
12694
12695 u8 reserved_at_60[0x20];
12696
12697 struct mlx5_ifc_sf_partition_bits sf_partition[];
12698};
12699
12700struct mlx5_ifc_query_sf_partitions_in_bits {
12701 u8 opcode[0x10];
12702 u8 reserved_at_10[0x10];
12703
12704 u8 reserved_at_20[0x10];
12705 u8 op_mod[0x10];
12706
12707 u8 reserved_at_40[0x40];
12708};
12709
12710struct mlx5_ifc_dealloc_sf_out_bits {
12711 u8 status[0x8];
12712 u8 reserved_at_8[0x18];
12713
12714 u8 syndrome[0x20];
12715
12716 u8 reserved_at_40[0x40];
12717};
12718
12719struct mlx5_ifc_dealloc_sf_in_bits {
12720 u8 opcode[0x10];
12721 u8 reserved_at_10[0x10];
12722
12723 u8 reserved_at_20[0x10];
12724 u8 op_mod[0x10];
12725
12726 u8 reserved_at_40[0x10];
12727 u8 function_id[0x10];
12728
12729 u8 reserved_at_60[0x20];
12730};
12731
12732struct mlx5_ifc_alloc_sf_out_bits {
12733 u8 status[0x8];
12734 u8 reserved_at_8[0x18];
12735
12736 u8 syndrome[0x20];
12737
12738 u8 reserved_at_40[0x40];
12739};
12740
12741struct mlx5_ifc_alloc_sf_in_bits {
12742 u8 opcode[0x10];
12743 u8 reserved_at_10[0x10];
12744
12745 u8 reserved_at_20[0x10];
12746 u8 op_mod[0x10];
12747
12748 u8 reserved_at_40[0x10];
12749 u8 function_id[0x10];
12750
12751 u8 reserved_at_60[0x20];
12752};
12753
12754struct mlx5_ifc_affiliated_event_header_bits {
12755 u8 reserved_at_0[0x10];
12756 u8 obj_type[0x10];
12757
12758 u8 obj_id[0x20];
12759};
12760
12761enum {
12762 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
12763 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
12764 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
12765 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
12766 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
12767 MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
12768 MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL = 0x53,
12769 MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT = 0x58,
12770 MLX5_GENERAL_OBJECT_TYPES_FLOW_TABLE_ALIAS = 0xff15,
12771};
12772
12773enum {
12774 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY =
12775 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY),
12776 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC =
12777 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_IPSEC),
12778 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER =
12779 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_SAMPLER),
12780 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO =
12781 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO),
12782};
12783
12784enum {
12785 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_RDMA_CTRL =
12786 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_RDMA_CTRL - 0x40),
12787 MLX5_HCA_CAP_2_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT =
12788 BIT_ULL(MLX5_GENERAL_OBJECT_TYPES_PCIE_CONG_EVENT - 0x40),
12789};
12790
12791enum {
12792 MLX5_IPSEC_OBJECT_ICV_LEN_16B,
12793};
12794
12795enum {
12796 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
12797 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
12798 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
12799 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
12800};
12801
12802enum {
12803 MLX5_IPSEC_ASO_MODE = 0x0,
12804 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
12805 MLX5_IPSEC_ASO_INC_SN = 0x2,
12806};
12807
12808enum {
12809 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12810 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12811 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12812 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12813};
12814
12815struct mlx5_ifc_ipsec_aso_bits {
12816 u8 valid[0x1];
12817 u8 reserved_at_201[0x1];
12818 u8 mode[0x2];
12819 u8 window_sz[0x2];
12820 u8 soft_lft_arm[0x1];
12821 u8 hard_lft_arm[0x1];
12822 u8 remove_flow_enable[0x1];
12823 u8 esn_event_arm[0x1];
12824 u8 reserved_at_20a[0x16];
12825
12826 u8 remove_flow_pkt_cnt[0x20];
12827
12828 u8 remove_flow_soft_lft[0x20];
12829
12830 u8 reserved_at_260[0x80];
12831
12832 u8 mode_parameter[0x20];
12833
12834 u8 replay_protection_window[0x100];
12835};
12836
12837struct mlx5_ifc_ipsec_obj_bits {
12838 u8 modify_field_select[0x40];
12839 u8 full_offload[0x1];
12840 u8 reserved_at_41[0x1];
12841 u8 esn_en[0x1];
12842 u8 esn_overlap[0x1];
12843 u8 reserved_at_44[0x2];
12844 u8 icv_length[0x2];
12845 u8 reserved_at_48[0x4];
12846 u8 aso_return_reg[0x4];
12847 u8 reserved_at_50[0x10];
12848
12849 u8 esn_msb[0x20];
12850
12851 u8 reserved_at_80[0x8];
12852 u8 dekn[0x18];
12853
12854 u8 salt[0x20];
12855
12856 u8 implicit_iv[0x40];
12857
12858 u8 reserved_at_100[0x8];
12859 u8 ipsec_aso_access_pd[0x18];
12860 u8 reserved_at_120[0xe0];
12861
12862 struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
12863};
12864
12865struct mlx5_ifc_create_ipsec_obj_in_bits {
12866 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12867 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12868};
12869
12870enum {
12871 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
12872 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
12873};
12874
12875struct mlx5_ifc_query_ipsec_obj_out_bits {
12876 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12877 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12878};
12879
12880struct mlx5_ifc_modify_ipsec_obj_in_bits {
12881 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12882 struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12883};
12884
12885enum {
12886 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12887};
12888
12889enum {
12890 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0,
12891 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1,
12892 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12893 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12894};
12895
12896#define MLX5_MACSEC_ASO_INC_SN 0x2
12897#define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12898
12899struct mlx5_ifc_macsec_aso_bits {
12900 u8 valid[0x1];
12901 u8 reserved_at_1[0x1];
12902 u8 mode[0x2];
12903 u8 window_size[0x2];
12904 u8 soft_lifetime_arm[0x1];
12905 u8 hard_lifetime_arm[0x1];
12906 u8 remove_flow_enable[0x1];
12907 u8 epn_event_arm[0x1];
12908 u8 reserved_at_a[0x16];
12909
12910 u8 remove_flow_packet_count[0x20];
12911
12912 u8 remove_flow_soft_lifetime[0x20];
12913
12914 u8 reserved_at_60[0x80];
12915
12916 u8 mode_parameter[0x20];
12917
12918 u8 replay_protection_window[8][0x20];
12919};
12920
12921struct mlx5_ifc_macsec_offload_obj_bits {
12922 u8 modify_field_select[0x40];
12923
12924 u8 confidentiality_en[0x1];
12925 u8 reserved_at_41[0x1];
12926 u8 epn_en[0x1];
12927 u8 epn_overlap[0x1];
12928 u8 reserved_at_44[0x2];
12929 u8 confidentiality_offset[0x2];
12930 u8 reserved_at_48[0x4];
12931 u8 aso_return_reg[0x4];
12932 u8 reserved_at_50[0x10];
12933
12934 u8 epn_msb[0x20];
12935
12936 u8 reserved_at_80[0x8];
12937 u8 dekn[0x18];
12938
12939 u8 reserved_at_a0[0x20];
12940
12941 u8 sci[0x40];
12942
12943 u8 reserved_at_100[0x8];
12944 u8 macsec_aso_access_pd[0x18];
12945
12946 u8 reserved_at_120[0x60];
12947
12948 u8 salt[3][0x20];
12949
12950 u8 reserved_at_1e0[0x20];
12951
12952 struct mlx5_ifc_macsec_aso_bits macsec_aso;
12953};
12954
12955struct mlx5_ifc_create_macsec_obj_in_bits {
12956 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12957 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12958};
12959
12960struct mlx5_ifc_modify_macsec_obj_in_bits {
12961 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12962 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12963};
12964
12965enum {
12966 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12967 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12968};
12969
12970struct mlx5_ifc_query_macsec_obj_out_bits {
12971 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12972 struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12973};
12974
12975struct mlx5_ifc_wrapped_dek_bits {
12976 u8 gcm_iv[0x60];
12977
12978 u8 reserved_at_60[0x20];
12979
12980 u8 const0[0x1];
12981 u8 key_size[0x1];
12982 u8 reserved_at_82[0x2];
12983 u8 key2_invalid[0x1];
12984 u8 reserved_at_85[0x3];
12985 u8 pd[0x18];
12986
12987 u8 key_purpose[0x5];
12988 u8 reserved_at_a5[0x13];
12989 u8 kek_id[0x8];
12990
12991 u8 reserved_at_c0[0x40];
12992
12993 u8 key1[0x8][0x20];
12994
12995 u8 key2[0x8][0x20];
12996
12997 u8 reserved_at_300[0x40];
12998
12999 u8 const1[0x1];
13000 u8 reserved_at_341[0x1f];
13001
13002 u8 reserved_at_360[0x20];
13003
13004 u8 auth_tag[0x80];
13005};
13006
13007struct mlx5_ifc_encryption_key_obj_bits {
13008 u8 modify_field_select[0x40];
13009
13010 u8 state[0x8];
13011 u8 sw_wrapped[0x1];
13012 u8 reserved_at_49[0xb];
13013 u8 key_size[0x4];
13014 u8 reserved_at_58[0x4];
13015 u8 key_purpose[0x4];
13016
13017 u8 reserved_at_60[0x8];
13018 u8 pd[0x18];
13019
13020 u8 reserved_at_80[0x100];
13021
13022 u8 opaque[0x40];
13023
13024 u8 reserved_at_1c0[0x40];
13025
13026 u8 key[8][0x80];
13027
13028 u8 sw_wrapped_dek[8][0x80];
13029
13030 u8 reserved_at_a00[0x600];
13031};
13032
13033struct mlx5_ifc_create_encryption_key_in_bits {
13034 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13035 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13036};
13037
13038struct mlx5_ifc_modify_encryption_key_in_bits {
13039 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13040 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
13041};
13042
13043enum {
13044 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0,
13045 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1,
13046 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2,
13047 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3,
13048};
13049
13050struct mlx5_ifc_flow_meter_parameters_bits {
13051 u8 valid[0x1];
13052 u8 bucket_overflow[0x1];
13053 u8 start_color[0x2];
13054 u8 both_buckets_on_green[0x1];
13055 u8 reserved_at_5[0x1];
13056 u8 meter_mode[0x2];
13057 u8 reserved_at_8[0x18];
13058
13059 u8 reserved_at_20[0x20];
13060
13061 u8 reserved_at_40[0x3];
13062 u8 cbs_exponent[0x5];
13063 u8 cbs_mantissa[0x8];
13064 u8 reserved_at_50[0x3];
13065 u8 cir_exponent[0x5];
13066 u8 cir_mantissa[0x8];
13067
13068 u8 reserved_at_60[0x20];
13069
13070 u8 reserved_at_80[0x3];
13071 u8 ebs_exponent[0x5];
13072 u8 ebs_mantissa[0x8];
13073 u8 reserved_at_90[0x3];
13074 u8 eir_exponent[0x5];
13075 u8 eir_mantissa[0x8];
13076
13077 u8 reserved_at_a0[0x60];
13078};
13079
13080struct mlx5_ifc_flow_meter_aso_obj_bits {
13081 u8 modify_field_select[0x40];
13082
13083 u8 reserved_at_40[0x40];
13084
13085 u8 reserved_at_80[0x8];
13086 u8 meter_aso_access_pd[0x18];
13087
13088 u8 reserved_at_a0[0x160];
13089
13090 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
13091};
13092
13093struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
13094 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13095 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
13096};
13097
13098struct mlx5_ifc_int_kek_obj_bits {
13099 u8 modify_field_select[0x40];
13100
13101 u8 state[0x8];
13102 u8 auto_gen[0x1];
13103 u8 reserved_at_49[0xb];
13104 u8 key_size[0x4];
13105 u8 reserved_at_58[0x8];
13106
13107 u8 reserved_at_60[0x8];
13108 u8 pd[0x18];
13109
13110 u8 reserved_at_80[0x180];
13111 u8 key[8][0x80];
13112
13113 u8 reserved_at_600[0x200];
13114};
13115
13116struct mlx5_ifc_create_int_kek_obj_in_bits {
13117 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13118 struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13119};
13120
13121struct mlx5_ifc_create_int_kek_obj_out_bits {
13122 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13123 struct mlx5_ifc_int_kek_obj_bits int_kek_object;
13124};
13125
13126struct mlx5_ifc_sampler_obj_bits {
13127 u8 modify_field_select[0x40];
13128
13129 u8 table_type[0x8];
13130 u8 level[0x8];
13131 u8 reserved_at_50[0xf];
13132 u8 ignore_flow_level[0x1];
13133
13134 u8 sample_ratio[0x20];
13135
13136 u8 reserved_at_80[0x8];
13137 u8 sample_table_id[0x18];
13138
13139 u8 reserved_at_a0[0x8];
13140 u8 default_table_id[0x18];
13141
13142 u8 sw_steering_icm_address_rx[0x40];
13143 u8 sw_steering_icm_address_tx[0x40];
13144
13145 u8 reserved_at_140[0xa0];
13146};
13147
13148struct mlx5_ifc_create_sampler_obj_in_bits {
13149 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13150 struct mlx5_ifc_sampler_obj_bits sampler_object;
13151};
13152
13153struct mlx5_ifc_query_sampler_obj_out_bits {
13154 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13155 struct mlx5_ifc_sampler_obj_bits sampler_object;
13156};
13157
13158enum {
13159 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
13160 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
13161};
13162
13163enum {
13164 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
13165 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
13166 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
13167 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6,
13168};
13169
13170struct mlx5_ifc_tls_static_params_bits {
13171 u8 const_2[0x2];
13172 u8 tls_version[0x4];
13173 u8 const_1[0x2];
13174 u8 reserved_at_8[0x14];
13175 u8 encryption_standard[0x4];
13176
13177 u8 reserved_at_20[0x20];
13178
13179 u8 initial_record_number[0x40];
13180
13181 u8 resync_tcp_sn[0x20];
13182
13183 u8 gcm_iv[0x20];
13184
13185 u8 implicit_iv[0x40];
13186
13187 u8 reserved_at_100[0x8];
13188 u8 dek_index[0x18];
13189
13190 u8 reserved_at_120[0xe0];
13191};
13192
13193struct mlx5_ifc_tls_progress_params_bits {
13194 u8 next_record_tcp_sn[0x20];
13195
13196 u8 hw_resync_tcp_sn[0x20];
13197
13198 u8 record_tracker_state[0x2];
13199 u8 auth_state[0x2];
13200 u8 reserved_at_44[0x4];
13201 u8 hw_offset_record_number[0x18];
13202};
13203
13204enum {
13205 MLX5_MTT_PERM_READ = 1 << 0,
13206 MLX5_MTT_PERM_WRITE = 1 << 1,
13207 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
13208};
13209
13210enum {
13211 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0,
13212 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1,
13213};
13214
13215struct mlx5_ifc_suspend_vhca_in_bits {
13216 u8 opcode[0x10];
13217 u8 uid[0x10];
13218
13219 u8 reserved_at_20[0x10];
13220 u8 op_mod[0x10];
13221
13222 u8 reserved_at_40[0x10];
13223 u8 vhca_id[0x10];
13224
13225 u8 reserved_at_60[0x20];
13226};
13227
13228struct mlx5_ifc_suspend_vhca_out_bits {
13229 u8 status[0x8];
13230 u8 reserved_at_8[0x18];
13231
13232 u8 syndrome[0x20];
13233
13234 u8 reserved_at_40[0x40];
13235};
13236
13237enum {
13238 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0,
13239 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1,
13240};
13241
13242struct mlx5_ifc_resume_vhca_in_bits {
13243 u8 opcode[0x10];
13244 u8 uid[0x10];
13245
13246 u8 reserved_at_20[0x10];
13247 u8 op_mod[0x10];
13248
13249 u8 reserved_at_40[0x10];
13250 u8 vhca_id[0x10];
13251
13252 u8 reserved_at_60[0x20];
13253};
13254
13255struct mlx5_ifc_resume_vhca_out_bits {
13256 u8 status[0x8];
13257 u8 reserved_at_8[0x18];
13258
13259 u8 syndrome[0x20];
13260
13261 u8 reserved_at_40[0x40];
13262};
13263
13264struct mlx5_ifc_query_vhca_migration_state_in_bits {
13265 u8 opcode[0x10];
13266 u8 uid[0x10];
13267
13268 u8 reserved_at_20[0x10];
13269 u8 op_mod[0x10];
13270
13271 u8 incremental[0x1];
13272 u8 chunk[0x1];
13273 u8 reserved_at_42[0xe];
13274 u8 vhca_id[0x10];
13275
13276 u8 reserved_at_60[0x20];
13277};
13278
13279struct mlx5_ifc_query_vhca_migration_state_out_bits {
13280 u8 status[0x8];
13281 u8 reserved_at_8[0x18];
13282
13283 u8 syndrome[0x20];
13284
13285 u8 reserved_at_40[0x40];
13286
13287 u8 required_umem_size[0x20];
13288
13289 u8 reserved_at_a0[0x20];
13290
13291 u8 remaining_total_size[0x40];
13292
13293 u8 reserved_at_100[0x100];
13294};
13295
13296struct mlx5_ifc_save_vhca_state_in_bits {
13297 u8 opcode[0x10];
13298 u8 uid[0x10];
13299
13300 u8 reserved_at_20[0x10];
13301 u8 op_mod[0x10];
13302
13303 u8 incremental[0x1];
13304 u8 set_track[0x1];
13305 u8 reserved_at_42[0xe];
13306 u8 vhca_id[0x10];
13307
13308 u8 reserved_at_60[0x20];
13309
13310 u8 va[0x40];
13311
13312 u8 mkey[0x20];
13313
13314 u8 size[0x20];
13315};
13316
13317struct mlx5_ifc_save_vhca_state_out_bits {
13318 u8 status[0x8];
13319 u8 reserved_at_8[0x18];
13320
13321 u8 syndrome[0x20];
13322
13323 u8 actual_image_size[0x20];
13324
13325 u8 next_required_umem_size[0x20];
13326};
13327
13328struct mlx5_ifc_load_vhca_state_in_bits {
13329 u8 opcode[0x10];
13330 u8 uid[0x10];
13331
13332 u8 reserved_at_20[0x10];
13333 u8 op_mod[0x10];
13334
13335 u8 reserved_at_40[0x10];
13336 u8 vhca_id[0x10];
13337
13338 u8 reserved_at_60[0x20];
13339
13340 u8 va[0x40];
13341
13342 u8 mkey[0x20];
13343
13344 u8 size[0x20];
13345};
13346
13347struct mlx5_ifc_load_vhca_state_out_bits {
13348 u8 status[0x8];
13349 u8 reserved_at_8[0x18];
13350
13351 u8 syndrome[0x20];
13352
13353 u8 reserved_at_40[0x40];
13354};
13355
13356struct mlx5_ifc_adv_rdma_cap_bits {
13357 u8 rdma_transport_manager[0x1];
13358 u8 rdma_transport_manager_other_eswitch[0x1];
13359 u8 reserved_at_2[0x1e];
13360
13361 u8 rcx_type[0x8];
13362 u8 reserved_at_28[0x2];
13363 u8 ps_entry_log_max_value[0x6];
13364 u8 reserved_at_30[0x6];
13365 u8 qp_max_ps_num_entry[0xa];
13366
13367 u8 mp_max_num_queues[0x8];
13368 u8 ps_user_context_max_log_size[0x8];
13369 u8 message_based_qp_and_striding_wq[0x8];
13370 u8 reserved_at_58[0x8];
13371
13372 u8 max_receive_send_message_size_stride[0x10];
13373 u8 reserved_at_70[0x10];
13374
13375 u8 max_receive_send_message_size_byte[0x20];
13376
13377 u8 reserved_at_a0[0x160];
13378
13379 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_rx_flow_table_properties;
13380
13381 struct mlx5_ifc_flow_table_prop_layout_bits rdma_transport_tx_flow_table_properties;
13382
13383 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_support_2;
13384
13385 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_support_2;
13386
13387 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_rx_ft_field_bitmask_support_2;
13388
13389 struct mlx5_ifc_flow_table_fields_supported_2_bits rdma_transport_tx_ft_field_bitmask_support_2;
13390
13391 u8 reserved_at_800[0x3800];
13392};
13393
13394struct mlx5_ifc_adv_virtualization_cap_bits {
13395 u8 reserved_at_0[0x3];
13396 u8 pg_track_log_max_num[0x5];
13397 u8 pg_track_max_num_range[0x8];
13398 u8 pg_track_log_min_addr_space[0x8];
13399 u8 pg_track_log_max_addr_space[0x8];
13400
13401 u8 reserved_at_20[0x3];
13402 u8 pg_track_log_min_msg_size[0x5];
13403 u8 reserved_at_28[0x3];
13404 u8 pg_track_log_max_msg_size[0x5];
13405 u8 reserved_at_30[0x3];
13406 u8 pg_track_log_min_page_size[0x5];
13407 u8 reserved_at_38[0x3];
13408 u8 pg_track_log_max_page_size[0x5];
13409
13410 u8 reserved_at_40[0x7c0];
13411};
13412
13413struct mlx5_ifc_page_track_report_entry_bits {
13414 u8 dirty_address_high[0x20];
13415
13416 u8 dirty_address_low[0x20];
13417};
13418
13419enum {
13420 MLX5_PAGE_TRACK_STATE_TRACKING,
13421 MLX5_PAGE_TRACK_STATE_REPORTING,
13422 MLX5_PAGE_TRACK_STATE_ERROR,
13423};
13424
13425struct mlx5_ifc_page_track_range_bits {
13426 u8 start_address[0x40];
13427
13428 u8 length[0x40];
13429};
13430
13431struct mlx5_ifc_page_track_bits {
13432 u8 modify_field_select[0x40];
13433
13434 u8 reserved_at_40[0x10];
13435 u8 vhca_id[0x10];
13436
13437 u8 reserved_at_60[0x20];
13438
13439 u8 state[0x4];
13440 u8 track_type[0x4];
13441 u8 log_addr_space_size[0x8];
13442 u8 reserved_at_90[0x3];
13443 u8 log_page_size[0x5];
13444 u8 reserved_at_98[0x3];
13445 u8 log_msg_size[0x5];
13446
13447 u8 reserved_at_a0[0x8];
13448 u8 reporting_qpn[0x18];
13449
13450 u8 reserved_at_c0[0x18];
13451 u8 num_ranges[0x8];
13452
13453 u8 reserved_at_e0[0x20];
13454
13455 u8 range_start_address[0x40];
13456
13457 u8 length[0x40];
13458
13459 struct mlx5_ifc_page_track_range_bits track_range[0];
13460};
13461
13462struct mlx5_ifc_create_page_track_obj_in_bits {
13463 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13464 struct mlx5_ifc_page_track_bits obj_context;
13465};
13466
13467struct mlx5_ifc_modify_page_track_obj_in_bits {
13468 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
13469 struct mlx5_ifc_page_track_bits obj_context;
13470};
13471
13472struct mlx5_ifc_query_page_track_obj_out_bits {
13473 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
13474 struct mlx5_ifc_page_track_bits obj_context;
13475};
13476
13477struct mlx5_ifc_msecq_reg_bits {
13478 u8 reserved_at_0[0x20];
13479
13480 u8 reserved_at_20[0x12];
13481 u8 network_option[0x2];
13482 u8 local_ssm_code[0x4];
13483 u8 local_enhanced_ssm_code[0x8];
13484
13485 u8 local_clock_identity[0x40];
13486
13487 u8 reserved_at_80[0x180];
13488};
13489
13490enum {
13491 MLX5_MSEES_FIELD_SELECT_ENABLE = BIT(0),
13492 MLX5_MSEES_FIELD_SELECT_ADMIN_STATUS = BIT(1),
13493 MLX5_MSEES_FIELD_SELECT_ADMIN_FREQ_MEASURE = BIT(2),
13494};
13495
13496enum mlx5_msees_admin_status {
13497 MLX5_MSEES_ADMIN_STATUS_FREE_RUNNING = 0x0,
13498 MLX5_MSEES_ADMIN_STATUS_TRACK = 0x1,
13499};
13500
13501enum mlx5_msees_oper_status {
13502 MLX5_MSEES_OPER_STATUS_FREE_RUNNING = 0x0,
13503 MLX5_MSEES_OPER_STATUS_SELF_TRACK = 0x1,
13504 MLX5_MSEES_OPER_STATUS_OTHER_TRACK = 0x2,
13505 MLX5_MSEES_OPER_STATUS_HOLDOVER = 0x3,
13506 MLX5_MSEES_OPER_STATUS_FAIL_HOLDOVER = 0x4,
13507 MLX5_MSEES_OPER_STATUS_FAIL_FREE_RUNNING = 0x5,
13508};
13509
13510enum mlx5_msees_failure_reason {
13511 MLX5_MSEES_FAILURE_REASON_UNDEFINED_ERROR = 0x0,
13512 MLX5_MSEES_FAILURE_REASON_PORT_DOWN = 0x1,
13513 MLX5_MSEES_FAILURE_REASON_TOO_HIGH_FREQUENCY_DIFF = 0x2,
13514 MLX5_MSEES_FAILURE_REASON_NET_SYNCHRONIZER_DEVICE_ERROR = 0x3,
13515 MLX5_MSEES_FAILURE_REASON_LACK_OF_RESOURCES = 0x4,
13516};
13517
13518struct mlx5_ifc_msees_reg_bits {
13519 u8 reserved_at_0[0x8];
13520 u8 local_port[0x8];
13521 u8 pnat[0x2];
13522 u8 lp_msb[0x2];
13523 u8 reserved_at_14[0xc];
13524
13525 u8 field_select[0x20];
13526
13527 u8 admin_status[0x4];
13528 u8 oper_status[0x4];
13529 u8 ho_acq[0x1];
13530 u8 reserved_at_49[0xc];
13531 u8 admin_freq_measure[0x1];
13532 u8 oper_freq_measure[0x1];
13533 u8 failure_reason[0x9];
13534
13535 u8 frequency_diff[0x20];
13536
13537 u8 reserved_at_80[0x180];
13538};
13539
13540struct mlx5_ifc_mrtcq_reg_bits {
13541 u8 reserved_at_0[0x40];
13542
13543 u8 rt_clock_identity[0x40];
13544
13545 u8 reserved_at_80[0x180];
13546};
13547
13548struct mlx5_ifc_pcie_cong_event_obj_bits {
13549 u8 modify_select_field[0x40];
13550
13551 u8 inbound_event_en[0x1];
13552 u8 outbound_event_en[0x1];
13553 u8 reserved_at_42[0x1e];
13554
13555 u8 reserved_at_60[0x1];
13556 u8 inbound_cong_state[0x3];
13557 u8 reserved_at_64[0x1];
13558 u8 outbound_cong_state[0x3];
13559 u8 reserved_at_68[0x18];
13560
13561 u8 inbound_cong_low_threshold[0x10];
13562 u8 inbound_cong_high_threshold[0x10];
13563
13564 u8 outbound_cong_low_threshold[0x10];
13565 u8 outbound_cong_high_threshold[0x10];
13566
13567 u8 reserved_at_e0[0x340];
13568};
13569
13570struct mlx5_ifc_pcie_cong_event_cmd_in_bits {
13571 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
13572 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13573};
13574
13575struct mlx5_ifc_pcie_cong_event_cmd_out_bits {
13576 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
13577 struct mlx5_ifc_pcie_cong_event_obj_bits cong_obj;
13578};
13579
13580enum mlx5e_pcie_cong_event_mod_field {
13581 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0),
13582 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2),
13583};
13584
13585struct mlx5_ifc_psp_rotate_key_in_bits {
13586 u8 opcode[0x10];
13587 u8 uid[0x10];
13588
13589 u8 reserved_at_20[0x10];
13590 u8 op_mod[0x10];
13591
13592 u8 reserved_at_40[0x40];
13593};
13594
13595struct mlx5_ifc_psp_rotate_key_out_bits {
13596 u8 status[0x8];
13597 u8 reserved_at_8[0x18];
13598
13599 u8 syndrome[0x20];
13600
13601 u8 reserved_at_40[0x40];
13602};
13603
13604enum mlx5_psp_gen_spi_in_key_size {
13605 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0,
13606 MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1,
13607};
13608
13609struct mlx5_ifc_key_spi_bits {
13610 u8 spi[0x20];
13611
13612 u8 reserved_at_20[0x60];
13613
13614 u8 key[8][0x20];
13615};
13616
13617struct mlx5_ifc_psp_gen_spi_in_bits {
13618 u8 opcode[0x10];
13619 u8 uid[0x10];
13620
13621 u8 reserved_at_20[0x10];
13622 u8 op_mod[0x10];
13623
13624 u8 reserved_at_40[0x20];
13625
13626 u8 key_size[0x2];
13627 u8 reserved_at_62[0xe];
13628 u8 num_of_spi[0x10];
13629};
13630
13631struct mlx5_ifc_psp_gen_spi_out_bits {
13632 u8 status[0x8];
13633 u8 reserved_at_8[0x18];
13634
13635 u8 syndrome[0x20];
13636
13637 u8 reserved_at_40[0x10];
13638 u8 num_of_spi[0x10];
13639
13640 u8 reserved_at_60[0x20];
13641
13642 struct mlx5_ifc_key_spi_bits key_spi[];
13643};
13644
13645#endif /* MLX5_IFC_H */