Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39#include <linux/bitfield.h>
40
41#if defined(__LITTLE_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0
43#elif defined(__BIG_ENDIAN)
44#define MLX5_SET_HOST_ENDIANNESS 0x80
45#else
46#error Host endianness not defined
47#endif
48
49/* helper macros */
50#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
51#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
52#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
53#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
54#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
55#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
56#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
57#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
58#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
59#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
60#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
61#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
62#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
63
64#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
65#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
66#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
67#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
68#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
69#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
70#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
71#define MLX5_ADDR_OF(typ, p, fld) ((void *)((u8 *)(p) + MLX5_BYTE_OFF(typ, fld)))
72
73/* insert a value to a struct */
74#define MLX5_SET(typ, p, fld, v) do { \
75 u32 _v = v; \
76 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
77 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
78 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
79 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
80 << __mlx5_dw_bit_off(typ, fld))); \
81} while (0)
82
83#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
85 MLX5_SET(typ, p, fld[idx], v); \
86} while (0)
87
88#define MLX5_SET_TO_ONES(typ, p, fld) do { \
89 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
90 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
91 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
92 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
93 << __mlx5_dw_bit_off(typ, fld))); \
94} while (0)
95
96#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
97__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
98__mlx5_mask(typ, fld))
99
100#define MLX5_GET_PR(typ, p, fld) ({ \
101 u32 ___t = MLX5_GET(typ, p, fld); \
102 pr_debug(#fld " = 0x%x\n", ___t); \
103 ___t; \
104})
105
106#define __MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
108 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
109} while (0)
110
111#define MLX5_SET64(typ, p, fld, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld, v); \
114} while (0)
115
116#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
117 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
118 __MLX5_SET64(typ, p, fld[idx], v); \
119} while (0)
120
121#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
122
123#define MLX5_GET64_PR(typ, p, fld) ({ \
124 u64 ___t = MLX5_GET64(typ, p, fld); \
125 pr_debug(#fld " = 0x%llx\n", ___t); \
126 ___t; \
127})
128
129#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
130__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
131__mlx5_mask16(typ, fld))
132
133#define MLX5_SET16(typ, p, fld, v) do { \
134 u16 _v = v; \
135 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
136 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
137 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
138 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
139 << __mlx5_16_bit_off(typ, fld))); \
140} while (0)
141
142/* Big endian getters */
143#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
144 __mlx5_64_off(typ, fld)))
145
146#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
147 type_t tmp; \
148 switch (sizeof(tmp)) { \
149 case sizeof(u8): \
150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
151 break; \
152 case sizeof(u16): \
153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
154 break; \
155 case sizeof(u32): \
156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
157 break; \
158 case sizeof(u64): \
159 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
160 break; \
161 } \
162 tmp; \
163 })
164
165enum mlx5_inline_modes {
166 MLX5_INLINE_MODE_NONE,
167 MLX5_INLINE_MODE_L2,
168 MLX5_INLINE_MODE_IP,
169 MLX5_INLINE_MODE_TCP_UDP,
170};
171
172enum {
173 MLX5_MAX_COMMANDS = 32,
174 MLX5_CMD_DATA_BLOCK_SIZE = 512,
175 MLX5_PCI_CMD_XPORT = 7,
176 MLX5_MKEY_BSF_OCTO_SIZE = 4,
177 MLX5_MAX_PSVS = 4,
178};
179
180enum {
181 MLX5_EXTENDED_UD_AV = 0x80000000,
182};
183
184enum {
185 MLX5_CQ_STATE_ARMED = 9,
186 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
187 MLX5_CQ_STATE_FIRED = 0xa,
188};
189
190enum {
191 MLX5_STAT_RATE_OFFSET = 5,
192};
193
194enum {
195 MLX5_INLINE_SEG = 0x80000000,
196};
197
198enum {
199 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
200};
201
202enum {
203 MLX5_MIN_PKEY_TABLE_SIZE = 128,
204 MLX5_MAX_LOG_PKEY_TABLE = 5,
205};
206
207enum {
208 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
209};
210
211enum {
212 MLX5_PFAULT_SUBTYPE_WQE = 0,
213 MLX5_PFAULT_SUBTYPE_RDMA = 1,
214 MLX5_PFAULT_SUBTYPE_MEMORY = 2,
215};
216
217enum wqe_page_fault_type {
218 MLX5_WQE_PF_TYPE_RMP = 0,
219 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
220 MLX5_WQE_PF_TYPE_RESP = 2,
221 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
222};
223
224enum {
225 MLX5_PERM_LOCAL_READ = 1 << 2,
226 MLX5_PERM_LOCAL_WRITE = 1 << 3,
227 MLX5_PERM_REMOTE_READ = 1 << 4,
228 MLX5_PERM_REMOTE_WRITE = 1 << 5,
229 MLX5_PERM_ATOMIC = 1 << 6,
230 MLX5_PERM_UMR_EN = 1 << 7,
231};
232
233enum {
234 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
235 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
236 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
237 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
238 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
239};
240
241enum {
242 MLX5_EN_RD = (u64)1,
243 MLX5_EN_WR = (u64)2
244};
245
246enum {
247 MLX5_ADAPTER_PAGE_SHIFT = 12,
248 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
249};
250
251enum {
252 MLX5_BFREGS_PER_UAR = 4,
253 MLX5_MAX_UARS = 1 << 8,
254 MLX5_NON_FP_BFREGS_PER_UAR = 2,
255 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
256 MLX5_NON_FP_BFREGS_PER_UAR,
257 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
258 MLX5_NON_FP_BFREGS_PER_UAR,
259 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
260 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
261 MLX5_MIN_DYN_BFREGS = 512,
262 MLX5_MAX_DYN_BFREGS = 1024,
263};
264
265enum {
266 MLX5_MKEY_MASK_LEN = 1ull << 0,
267 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
268 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
269 MLX5_MKEY_MASK_PD = 1ull << 7,
270 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
271 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
272 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
273 MLX5_MKEY_MASK_KEY = 1ull << 13,
274 MLX5_MKEY_MASK_QPN = 1ull << 14,
275 MLX5_MKEY_MASK_LR = 1ull << 17,
276 MLX5_MKEY_MASK_LW = 1ull << 18,
277 MLX5_MKEY_MASK_RR = 1ull << 19,
278 MLX5_MKEY_MASK_RW = 1ull << 20,
279 MLX5_MKEY_MASK_A = 1ull << 21,
280 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
281 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
282 MLX5_MKEY_MASK_FREE = 1ull << 29,
283 MLX5_MKEY_MASK_PAGE_SIZE_5 = 1ull << 42,
284 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
285};
286
287enum {
288 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
289
290 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
291 MLX5_UMR_CHECK_FREE = (2 << 5),
292
293 MLX5_UMR_INLINE = (1 << 7),
294};
295
296#define MLX5_UMR_FLEX_ALIGNMENT 0x40
297#define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
298#define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
299#define MLX5_UMR_KSM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_ksm))
300
301#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
302
303enum {
304 MLX5_EVENT_QUEUE_TYPE_QP = 0,
305 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
306 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
307 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
308};
309
310/* mlx5 components can subscribe to any one of these events via
311 * mlx5_eq_notifier_register API.
312 */
313enum mlx5_event {
314 /* Special value to subscribe to any event */
315 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
316 /* HW events enum start: comp events are not subscribable */
317 MLX5_EVENT_TYPE_COMP = 0x0,
318 /* HW Async events enum start: subscribable events */
319 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
320 MLX5_EVENT_TYPE_COMM_EST = 0x02,
321 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
322 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
323 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
324
325 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
326 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
327 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
328 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
329 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
330 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
331 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
332
333 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
334 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
335 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
336 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
337 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
338 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
339 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
340 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
341 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
342 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
343
344 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
345 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
346
347 MLX5_EVENT_TYPE_CMD = 0x0a,
348 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
349
350 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
351 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
352
353 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
354 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
355
356 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
357 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
358
359 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
360 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
361
362 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
363
364 MLX5_EVENT_TYPE_MAX = 0x100,
365};
366
367enum mlx5_driver_event {
368 MLX5_DRIVER_EVENT_TYPE_TRAP = 0,
369 MLX5_DRIVER_EVENT_UPLINK_NETDEV,
370 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED,
371 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED,
372 MLX5_DRIVER_EVENT_SF_PEER_DEVLINK,
373 MLX5_DRIVER_EVENT_AFFILIATION_DONE,
374 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED,
375 MLX5_DRIVER_EVENT_ACTIVE_BACKUP_LAG_CHANGE_LOWERSTATE,
376};
377
378enum {
379 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
380 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
381 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2,
382};
383
384enum {
385 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
386 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
387 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
388 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
389};
390
391enum {
392 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
393 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
394 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
395 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
396 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
397 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
398 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
399};
400
401enum {
402 MLX5_ROCE_VERSION_1 = 0,
403 MLX5_ROCE_VERSION_2 = 2,
404};
405
406enum {
407 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
408 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
409};
410
411enum {
412 MLX5_ROCE_L3_TYPE_IPV4 = 0,
413 MLX5_ROCE_L3_TYPE_IPV6 = 1,
414};
415
416enum {
417 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
418 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
419};
420
421enum {
422 MLX5_OPCODE_NOP = 0x00,
423 MLX5_OPCODE_SEND_INVAL = 0x01,
424 MLX5_OPCODE_RDMA_WRITE = 0x08,
425 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
426 MLX5_OPCODE_SEND = 0x0a,
427 MLX5_OPCODE_SEND_IMM = 0x0b,
428 MLX5_OPCODE_LSO = 0x0e,
429 MLX5_OPCODE_RDMA_READ = 0x10,
430 MLX5_OPCODE_ATOMIC_CS = 0x11,
431 MLX5_OPCODE_ATOMIC_FA = 0x12,
432 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
433 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
434 MLX5_OPCODE_BIND_MW = 0x18,
435 MLX5_OPCODE_CONFIG_CMD = 0x1f,
436 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
437
438 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
439 MLX5_RECV_OPCODE_SEND = 0x01,
440 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
441 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
442
443 MLX5_CQE_OPCODE_ERROR = 0x1e,
444 MLX5_CQE_OPCODE_RESIZE = 0x16,
445
446 MLX5_OPCODE_SET_PSV = 0x20,
447 MLX5_OPCODE_GET_PSV = 0x21,
448 MLX5_OPCODE_CHECK_PSV = 0x22,
449 MLX5_OPCODE_DUMP = 0x23,
450 MLX5_OPCODE_RGET_PSV = 0x26,
451 MLX5_OPCODE_RCHECK_PSV = 0x27,
452
453 MLX5_OPCODE_UMR = 0x25,
454
455 MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c,
456
457 MLX5_OPCODE_ACCESS_ASO = 0x2d,
458};
459
460enum {
461 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
462 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
463};
464
465enum {
466 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
467 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
468};
469
470struct mlx5_wqe_tls_static_params_seg {
471 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
472};
473
474struct mlx5_wqe_tls_progress_params_seg {
475 __be32 tis_tir_num;
476 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
477};
478
479enum {
480 MLX5_SET_PORT_RESET_QKEY = 0,
481 MLX5_SET_PORT_GUID0 = 16,
482 MLX5_SET_PORT_NODE_GUID = 17,
483 MLX5_SET_PORT_SYS_GUID = 18,
484 MLX5_SET_PORT_GID_TABLE = 19,
485 MLX5_SET_PORT_PKEY_TABLE = 20,
486};
487
488enum {
489 MLX5_BW_NO_LIMIT = 0,
490 MLX5_100_MBPS_UNIT = 3,
491 MLX5_GBPS_UNIT = 4,
492};
493
494enum {
495 MLX5_MAX_PAGE_SHIFT = 31
496};
497
498enum {
499 /*
500 * Max wqe size for rdma read is 512 bytes, so this
501 * limits our max_sge_rd as the wqe needs to fit:
502 * - ctrl segment (16 bytes)
503 * - rdma segment (16 bytes)
504 * - scatter elements (16 bytes each)
505 */
506 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
507};
508
509enum mlx5_odp_transport_cap_bits {
510 MLX5_ODP_SUPPORT_SEND = 1 << 31,
511 MLX5_ODP_SUPPORT_RECV = 1 << 30,
512 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
513 MLX5_ODP_SUPPORT_READ = 1 << 28,
514};
515
516struct mlx5_odp_caps {
517 char reserved[0x10];
518 struct {
519 __be32 rc_odp_caps;
520 __be32 uc_odp_caps;
521 __be32 ud_odp_caps;
522 } per_transport_caps;
523 char reserved2[0xe4];
524};
525
526struct mlx5_cmd_layout {
527 u8 type;
528 u8 rsvd0[3];
529 __be32 inlen;
530 __be64 in_ptr;
531 __be32 in[4];
532 __be32 out[4];
533 __be64 out_ptr;
534 __be32 outlen;
535 u8 token;
536 u8 sig;
537 u8 rsvd1;
538 u8 status_own;
539};
540
541enum mlx5_rfr_severity_bit_offsets {
542 MLX5_CRR_BIT_OFFSET = 0x6,
543 MLX5_RFR_BIT_OFFSET = 0x7,
544};
545
546struct health_buffer {
547 __be32 assert_var[6];
548 __be32 rsvd0[2];
549 __be32 assert_exit_ptr;
550 __be32 assert_callra;
551 __be32 rsvd1[1];
552 __be32 time;
553 __be32 fw_ver;
554 __be32 hw_id;
555 u8 rfr_severity;
556 u8 rsvd2[3];
557 u8 irisc_index;
558 u8 synd;
559 __be16 ext_synd;
560};
561
562enum mlx5_initializing_bit_offsets {
563 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
564};
565
566enum mlx5_cmd_addr_l_sz_offset {
567 MLX5_NIC_IFC_OFFSET = 8,
568};
569
570struct mlx5_init_seg {
571 __be32 fw_rev;
572 __be32 cmdif_rev_fw_sub;
573 __be32 rsvd0[2];
574 __be32 cmdq_addr_h;
575 __be32 cmdq_addr_l_sz;
576 __be32 cmd_dbell;
577 __be32 rsvd1[120];
578 __be32 initializing;
579 struct health_buffer health;
580 __be32 rsvd2[878];
581 __be32 cmd_exec_to;
582 __be32 cmd_q_init_to;
583 __be32 internal_timer_h;
584 __be32 internal_timer_l;
585 __be32 rsvd3[2];
586 __be32 health_counter;
587 __be32 rsvd4[11];
588 __be32 real_time_h;
589 __be32 real_time_l;
590 __be32 rsvd5[1006];
591 __be64 ieee1588_clk;
592 __be32 ieee1588_clk_type;
593 __be32 clr_intx;
594};
595
596struct mlx5_eqe_comp {
597 __be32 reserved[6];
598 __be32 cqn;
599};
600
601struct mlx5_eqe_qp_srq {
602 __be32 reserved1[5];
603 u8 type;
604 u8 reserved2[3];
605 __be32 qp_srq_n;
606};
607
608struct mlx5_eqe_cq_err {
609 __be32 cqn;
610 u8 reserved1[7];
611 u8 syndrome;
612};
613
614struct mlx5_eqe_xrq_err {
615 __be32 reserved1[5];
616 __be32 type_xrqn;
617 __be32 reserved2;
618};
619
620struct mlx5_eqe_port_state {
621 u8 reserved0[8];
622 u8 port;
623};
624
625struct mlx5_eqe_gpio {
626 __be32 reserved0[2];
627 __be64 gpio_event;
628};
629
630struct mlx5_eqe_congestion {
631 u8 type;
632 u8 rsvd0;
633 u8 congestion_level;
634};
635
636struct mlx5_eqe_stall_vl {
637 u8 rsvd0[3];
638 u8 port_vl;
639};
640
641struct mlx5_eqe_cmd {
642 __be32 vector;
643 __be32 rsvd[6];
644};
645
646struct mlx5_eqe_page_req {
647 __be16 ec_function;
648 __be16 func_id;
649 __be32 num_pages;
650 __be32 rsvd1[5];
651};
652
653#define MEMORY_SCHEME_PAGE_FAULT_GRANULARITY 4096
654struct mlx5_eqe_page_fault {
655 union {
656 struct {
657 __be32 bytes_committed;
658 u16 reserved1;
659 __be16 wqe_index;
660 u16 reserved2;
661 __be16 packet_length;
662 __be32 token;
663 u8 reserved4[8];
664 __be32 pftype_wq;
665 } __packed wqe;
666 struct {
667 __be32 bytes_committed;
668 __be32 r_key;
669 u16 reserved1;
670 __be16 packet_length;
671 __be32 rdma_op_len;
672 __be64 rdma_va;
673 __be32 pftype_token;
674 } __packed rdma;
675 struct {
676 u8 flags;
677 u8 reserved1;
678 __be16 post_demand_fault_pages;
679 __be16 pre_demand_fault_pages;
680 __be16 token47_32;
681 __be32 token31_0;
682 /*
683 * FW changed from specifying the fault size in byte
684 * count to 4k pages granularity. The size specified
685 * in pages uses bits 31:12, to keep backward
686 * compatibility.
687 */
688 __be32 demand_fault_pages;
689 __be32 mkey;
690 __be64 va;
691 } __packed memory;
692 } __packed;
693} __packed;
694
695struct mlx5_eqe_vport_change {
696 u8 rsvd0[2];
697 __be16 vport_num;
698 __be32 rsvd1[6];
699} __packed;
700
701struct mlx5_eqe_port_module {
702 u8 reserved_at_0[1];
703 u8 module;
704 u8 reserved_at_2[1];
705 u8 module_status;
706 u8 reserved_at_4[2];
707 u8 error_type;
708} __packed;
709
710struct mlx5_eqe_pps {
711 u8 rsvd0[3];
712 u8 pin;
713 u8 rsvd1[4];
714 union {
715 struct {
716 __be32 time_sec;
717 __be32 time_nsec;
718 };
719 struct {
720 __be64 time_stamp;
721 };
722 };
723 u8 rsvd2[12];
724} __packed;
725
726struct mlx5_eqe_dct {
727 __be32 reserved[6];
728 __be32 dctn;
729};
730
731struct mlx5_eqe_temp_warning {
732 __be64 sensor_warning_msb;
733 __be64 sensor_warning_lsb;
734} __packed;
735
736struct mlx5_eqe_obj_change {
737 u8 rsvd0[2];
738 __be16 obj_type;
739 __be32 obj_id;
740} __packed;
741
742#define SYNC_RST_STATE_MASK 0xf
743
744enum sync_rst_state_type {
745 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0,
746 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1,
747 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2,
748 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3,
749};
750
751struct mlx5_eqe_sync_fw_update {
752 u8 reserved_at_0[3];
753 u8 sync_rst_state;
754};
755
756struct mlx5_eqe_vhca_state {
757 __be16 ec_function;
758 __be16 function_id;
759} __packed;
760
761union ev_data {
762 __be32 raw[7];
763 struct mlx5_eqe_cmd cmd;
764 struct mlx5_eqe_comp comp;
765 struct mlx5_eqe_qp_srq qp_srq;
766 struct mlx5_eqe_cq_err cq_err;
767 struct mlx5_eqe_port_state port;
768 struct mlx5_eqe_gpio gpio;
769 struct mlx5_eqe_congestion cong;
770 struct mlx5_eqe_stall_vl stall_vl;
771 struct mlx5_eqe_page_req req_pages;
772 struct mlx5_eqe_page_fault page_fault;
773 struct mlx5_eqe_vport_change vport_change;
774 struct mlx5_eqe_port_module port_module;
775 struct mlx5_eqe_pps pps;
776 struct mlx5_eqe_dct dct;
777 struct mlx5_eqe_temp_warning temp_warning;
778 struct mlx5_eqe_xrq_err xrq_err;
779 struct mlx5_eqe_sync_fw_update sync_fw_update;
780 struct mlx5_eqe_vhca_state vhca_state;
781 struct mlx5_eqe_obj_change obj_change;
782} __packed;
783
784struct mlx5_eqe {
785 u8 rsvd0;
786 u8 type;
787 u8 rsvd1;
788 u8 sub_type;
789 __be32 rsvd2[7];
790 union ev_data data;
791 __be16 rsvd3;
792 u8 signature;
793 u8 owner;
794} __packed;
795
796struct mlx5_cmd_prot_block {
797 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
798 u8 rsvd0[48];
799 __be64 next;
800 __be32 block_num;
801 u8 rsvd1;
802 u8 token;
803 u8 ctrl_sig;
804 u8 sig;
805};
806
807enum {
808 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
809};
810
811struct mlx5_err_cqe {
812 u8 rsvd0[32];
813 __be32 srqn;
814 u8 rsvd1[18];
815 u8 vendor_err_synd;
816 u8 syndrome;
817 __be32 s_wqe_opcode_qpn;
818 __be16 wqe_counter;
819 u8 signature;
820 u8 op_own;
821};
822
823struct mlx5_cqe64 {
824 u8 tls_outer_l3_tunneled;
825 u8 rsvd0;
826 __be16 wqe_id;
827 union {
828 struct {
829 u8 tcppsh_abort_dupack;
830 u8 min_ttl;
831 __be16 tcp_win;
832 __be32 ack_seq_num;
833 } lro;
834 struct {
835 u8 reserved0:1;
836 u8 match:1;
837 u8 flush:1;
838 u8 reserved3:5;
839 u8 header_size;
840 __be16 header_entry_index;
841 __be32 data_offset;
842 } shampo;
843 };
844 __be32 rss_hash_result;
845 u8 rss_hash_type;
846 u8 ml_path;
847 u8 rsvd20[2];
848 __be16 check_sum;
849 __be16 slid;
850 __be32 flags_rqpn;
851 u8 hds_ip_ext;
852 u8 l4_l3_hdr_type;
853 __be16 vlan_info;
854 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
855 union {
856 __be32 immediate;
857 __be32 inval_rkey;
858 __be32 pkey;
859 __be32 ft_metadata;
860 };
861 u8 rsvd40[4];
862 __be32 byte_cnt;
863 __be32 timestamp_h;
864 __be32 timestamp_l;
865 __be32 sop_drop_qpn;
866 __be16 wqe_counter;
867 union {
868 u8 signature;
869 u8 validity_iteration_count;
870 };
871 u8 op_own;
872};
873
874struct mlx5_mini_cqe8 {
875 union {
876 __be32 rx_hash_result;
877 struct {
878 __be16 checksum;
879 __be16 stridx;
880 };
881 struct {
882 __be16 wqe_counter;
883 u8 s_wqe_opcode;
884 u8 reserved;
885 } s_wqe_info;
886 };
887 __be32 byte_cnt;
888};
889
890enum {
891 MLX5_NO_INLINE_DATA,
892 MLX5_INLINE_DATA32_SEG,
893 MLX5_INLINE_DATA64_SEG,
894 MLX5_COMPRESSED,
895};
896
897enum {
898 MLX5_CQE_FORMAT_CSUM = 0x1,
899 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
900};
901
902enum {
903 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
904 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
905};
906
907#define MLX5_MINI_CQE_ARRAY_SIZE 8
908
909static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
910{
911 return (cqe->op_own >> 2) & 0x3;
912}
913
914static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
915{
916 return cqe->op_own >> 4;
917}
918
919static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
920{
921 /* num_of_mini_cqes is zero based */
922 return get_cqe_opcode(cqe) + 1;
923}
924
925static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
926{
927 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
928}
929
930static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
931{
932 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
933}
934
935static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
936{
937 return cqe->tls_outer_l3_tunneled & 0x1;
938}
939
940static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
941{
942 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
943}
944
945static inline bool cqe_has_vlan(const struct mlx5_cqe64 *cqe)
946{
947 return cqe->l4_l3_hdr_type & 0x1;
948}
949
950static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
951{
952 u32 hi, lo;
953
954 hi = be32_to_cpu(cqe->timestamp_h);
955 lo = be32_to_cpu(cqe->timestamp_l);
956
957 return (u64)lo | ((u64)hi << 32);
958}
959
960static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe)
961{
962 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF;
963}
964
965#define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3
966#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9
967#define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16
968#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6
969#define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13
970
971struct mpwrq_cqe_bc {
972 __be16 filler_consumed_strides;
973 __be16 byte_cnt;
974};
975
976static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
977{
978 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
979
980 return be16_to_cpu(bc->byte_cnt);
981}
982
983static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
984{
985 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
986}
987
988static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
989{
990 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
991
992 return mpwrq_get_cqe_bc_consumed_strides(bc);
993}
994
995static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
996{
997 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
998
999 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
1000}
1001
1002static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
1003{
1004 return be16_to_cpu(cqe->wqe_counter);
1005}
1006
1007enum {
1008 CQE_L4_HDR_TYPE_NONE = 0x0,
1009 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
1010 CQE_L4_HDR_TYPE_UDP = 0x2,
1011 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
1012 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
1013};
1014
1015enum {
1016 CQE_RSS_HTYPE_IP = GENMASK(3, 2),
1017 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
1018 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
1019 */
1020 CQE_RSS_IP_NONE = 0x0,
1021 CQE_RSS_IPV4 = 0x1,
1022 CQE_RSS_IPV6 = 0x2,
1023 CQE_RSS_RESERVED = 0x3,
1024
1025 CQE_RSS_HTYPE_L4 = GENMASK(7, 6),
1026 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
1027 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
1028 */
1029 CQE_RSS_L4_NONE = 0x0,
1030 CQE_RSS_L4_TCP = 0x1,
1031 CQE_RSS_L4_UDP = 0x2,
1032 CQE_RSS_L4_IPSEC = 0x3,
1033};
1034
1035enum {
1036 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
1037 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
1038 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
1039};
1040
1041enum {
1042 CQE_L2_OK = 1 << 0,
1043 CQE_L3_OK = 1 << 1,
1044 CQE_L4_OK = 1 << 2,
1045};
1046
1047enum {
1048 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0,
1049 CQE_TLS_OFFLOAD_DECRYPTED = 0x1,
1050 CQE_TLS_OFFLOAD_RESYNC = 0x2,
1051 CQE_TLS_OFFLOAD_ERROR = 0x3,
1052};
1053
1054struct mlx5_sig_err_cqe {
1055 u8 rsvd0[16];
1056 __be32 expected_trans_sig;
1057 __be32 actual_trans_sig;
1058 __be32 expected_reftag;
1059 __be32 actual_reftag;
1060 __be16 syndrome;
1061 u8 rsvd22[2];
1062 __be32 mkey;
1063 __be64 err_offset;
1064 u8 rsvd30[8];
1065 __be32 qpn;
1066 u8 rsvd38[2];
1067 u8 signature;
1068 u8 op_own;
1069};
1070
1071struct mlx5_wqe_srq_next_seg {
1072 u8 rsvd0[2];
1073 __be16 next_wqe_index;
1074 u8 signature;
1075 u8 rsvd1[11];
1076};
1077
1078union mlx5_ext_cqe {
1079 struct ib_grh grh;
1080 u8 inl[64];
1081};
1082
1083struct mlx5_cqe128 {
1084 union mlx5_ext_cqe inl_grh;
1085 struct mlx5_cqe64 cqe64;
1086};
1087
1088enum {
1089 MLX5_MKEY_STATUS_FREE = 1 << 6,
1090};
1091
1092enum {
1093 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1094 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1095 MLX5_MKEY_BSF_EN = 1 << 30,
1096};
1097
1098struct mlx5_mkey_seg {
1099 /* This is a two bit field occupying bits 31-30.
1100 * bit 31 is always 0,
1101 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
1102 */
1103 u8 status;
1104 u8 pcie_control;
1105 u8 flags;
1106 u8 version;
1107 __be32 qpn_mkey7_0;
1108 u8 rsvd1[4];
1109 __be32 flags_pd;
1110 __be64 start_addr;
1111 __be64 len;
1112 __be32 bsfs_octo_size;
1113 u8 rsvd2[16];
1114 __be32 xlt_oct_size;
1115 u8 rsvd3[3];
1116 u8 log2_page_size;
1117 u8 rsvd4[4];
1118};
1119
1120#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1121
1122enum {
1123 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1124};
1125
1126enum {
1127 VPORT_STATE_DOWN = 0x0,
1128 VPORT_STATE_UP = 0x1,
1129};
1130
1131enum {
1132 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
1133 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
1134 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
1135};
1136
1137enum {
1138 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1,
1139 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3,
1140};
1141
1142enum {
1143 MLX5_L3_PROT_TYPE_IPV4 = 0,
1144 MLX5_L3_PROT_TYPE_IPV6 = 1,
1145};
1146
1147enum {
1148 MLX5_L4_PROT_TYPE_TCP = 0,
1149 MLX5_L4_PROT_TYPE_UDP = 1,
1150};
1151
1152enum {
1153 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1154 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1155 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1156 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1157 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1158};
1159
1160enum {
1161 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1162 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1163 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1164 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1165 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1166 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
1167 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6,
1168};
1169
1170enum {
1171 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1172 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1173};
1174
1175enum {
1176 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1177 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1178 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1179};
1180
1181enum mlx5_list_type {
1182 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1183 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1184 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1185};
1186
1187enum {
1188 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1189 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1190};
1191
1192enum mlx5_wol_mode {
1193 MLX5_WOL_DISABLE = 0,
1194 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1195 MLX5_WOL_MAGIC = 1 << 2,
1196 MLX5_WOL_ARP = 1 << 3,
1197 MLX5_WOL_BROADCAST = 1 << 4,
1198 MLX5_WOL_MULTICAST = 1 << 5,
1199 MLX5_WOL_UNICAST = 1 << 6,
1200 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1201};
1202
1203enum mlx5_mpls_supported_fields {
1204 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1205 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1206 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1207 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1208};
1209
1210enum mlx5_flex_parser_protos {
1211 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1212 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1213 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1214 MLX5_FLEX_PROTO_ICMP = 1 << 8,
1215 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9,
1216};
1217
1218/* MLX5 DEV CAPs */
1219
1220/* TODO: EAT.ME */
1221enum mlx5_cap_mode {
1222 HCA_CAP_OPMOD_GET_MAX = 0,
1223 HCA_CAP_OPMOD_GET_CUR = 1,
1224};
1225
1226/* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1227 * capability memory.
1228 */
1229enum mlx5_cap_type {
1230 MLX5_CAP_GENERAL = 0,
1231 MLX5_CAP_ETHERNET_OFFLOADS,
1232 MLX5_CAP_ODP,
1233 MLX5_CAP_ATOMIC,
1234 MLX5_CAP_ROCE,
1235 MLX5_CAP_IPOIB_OFFLOADS,
1236 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1237 MLX5_CAP_FLOW_TABLE,
1238 MLX5_CAP_ESWITCH_FLOW_TABLE,
1239 MLX5_CAP_ESWITCH,
1240 MLX5_CAP_QOS = 0xc,
1241 MLX5_CAP_DEBUG,
1242 MLX5_CAP_RESERVED_14,
1243 MLX5_CAP_DEV_MEM,
1244 MLX5_CAP_RESERVED_16,
1245 MLX5_CAP_TLS,
1246 MLX5_CAP_VDPA_EMULATION = 0x13,
1247 MLX5_CAP_DEV_EVENT = 0x14,
1248 MLX5_CAP_IPSEC,
1249 MLX5_CAP_CRYPTO = 0x1a,
1250 MLX5_CAP_SHAMPO = 0x1d,
1251 MLX5_CAP_PSP = 0x1e,
1252 MLX5_CAP_MACSEC = 0x1f,
1253 MLX5_CAP_GENERAL_2 = 0x20,
1254 MLX5_CAP_PORT_SELECTION = 0x25,
1255 MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1256 MLX5_CAP_ADV_RDMA = 0x28,
1257 /* NUM OF CAP Types */
1258 MLX5_CAP_NUM
1259};
1260
1261enum mlx5_pcam_reg_groups {
1262 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1263};
1264
1265enum mlx5_pcam_feature_groups {
1266 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1267};
1268
1269enum mlx5_mcam_reg_groups {
1270 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1271 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1272 MLX5_MCAM_REGS_0x9180_0x91FF = 0x3,
1273 MLX5_MCAM_REGS_NUM = 0x4,
1274};
1275
1276enum mlx5_mcam_feature_groups {
1277 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1278};
1279
1280enum mlx5_qcam_reg_groups {
1281 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1282};
1283
1284enum mlx5_qcam_feature_groups {
1285 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1286};
1287
1288/* GET Dev Caps macros */
1289#define MLX5_CAP_GEN(mdev, cap) \
1290 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1291
1292#define MLX5_CAP_GEN_64(mdev, cap) \
1293 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1294
1295#define MLX5_CAP_GEN_MAX(mdev, cap) \
1296 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1297
1298#define MLX5_CAP_GEN_2(mdev, cap) \
1299 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1300
1301#define MLX5_CAP_GEN_2_64(mdev, cap) \
1302 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1303
1304#define MLX5_CAP_GEN_2_MAX(mdev, cap) \
1305 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1306
1307#define MLX5_CAP_ETH(mdev, cap) \
1308 MLX5_GET(per_protocol_networking_offload_caps,\
1309 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1310
1311#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1312 MLX5_GET(per_protocol_networking_offload_caps,\
1313 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1314
1315#define MLX5_CAP_ROCE(mdev, cap) \
1316 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1317
1318#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1319 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1320
1321#define MLX5_CAP_ATOMIC(mdev, cap) \
1322 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1323
1324#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1325 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1326
1327#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1328 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1329
1330#define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1331 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1332
1333#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1334 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1335
1336#define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1337 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1338
1339#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1340 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1341
1342#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1343 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1344
1345#define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1346 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1347
1348#define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1349 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1350
1351#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_RX(mdev, cap) \
1352 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_rx_flow_table_properties.cap)
1353
1354#define MLX5_CAP_FLOWTABLE_RDMA_TRANSPORT_TX(mdev, cap) \
1355 MLX5_CAP_ADV_RDMA(mdev, rdma_transport_tx_flow_table_properties.cap)
1356
1357#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1358 MLX5_GET(flow_table_eswitch_cap, \
1359 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1360
1361#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1362 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1363
1364#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1365 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1366
1367#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1368 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1369
1370#define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1371 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1372
1373#define MLX5_CAP_NIC_RX_FT_FIELD_SUPPORT_2(mdev, cap) \
1374 MLX5_CAP_FLOWTABLE(mdev, ft_field_support_2_nic_receive.cap)
1375
1376#define MLX5_CAP_ESW(mdev, cap) \
1377 MLX5_GET(e_switch_cap, \
1378 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1379
1380#define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1381 MLX5_GET64(flow_table_eswitch_cap, \
1382 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1383
1384#define MLX5_CAP_PORT_SELECTION(mdev, cap) \
1385 MLX5_GET(port_selection_cap, \
1386 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1387
1388#define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \
1389 MLX5_GET(port_selection_cap, \
1390 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1391
1392#define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1393 MLX5_GET(adv_virtualization_cap, \
1394 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1395
1396#define MLX5_CAP_ADV_RDMA(mdev, cap) \
1397 MLX5_GET(adv_rdma_cap, \
1398 mdev->caps.hca[MLX5_CAP_ADV_RDMA]->cur, cap)
1399
1400#define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1401 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1402
1403#define MLX5_CAP_PORT_SELECTION_FT_FIELD_SUPPORT_2(mdev, cap) \
1404 MLX5_CAP_PORT_SELECTION(mdev, ft_field_support_2_port_selection.cap)
1405
1406#define MLX5_CAP_ODP(mdev, cap)\
1407 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1408
1409#define MLX5_CAP_ODP_SCHEME(mdev, cap) \
1410 (MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1411 mem_page_fault) ? \
1412 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1413 memory_page_fault_scheme_cap.cap) : \
1414 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, \
1415 transport_page_fault_scheme_cap.cap))
1416
1417#define MLX5_CAP_ODP_MAX(mdev, cap)\
1418 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1419
1420#define MLX5_CAP_QOS(mdev, cap)\
1421 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1422
1423#define MLX5_CAP_DEBUG(mdev, cap)\
1424 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1425
1426#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1427 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1428
1429#define MLX5_CAP_PCAM_REG(mdev, reg) \
1430 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1431
1432#define MLX5_CAP_MCAM_REG(mdev, reg) \
1433 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1434 mng_access_reg_cap_mask.access_regs.reg)
1435
1436#define MLX5_CAP_MCAM_REG2(mdev, reg) \
1437 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1438 mng_access_reg_cap_mask.access_regs2.reg)
1439
1440#define MLX5_CAP_MCAM_REG3(mdev, reg) \
1441 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \
1442 mng_access_reg_cap_mask.access_regs3.reg)
1443
1444#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1445 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1446
1447#define MLX5_CAP_QCAM_REG(mdev, fld) \
1448 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1449
1450#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1451 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1452
1453#define MLX5_CAP_FPGA(mdev, cap) \
1454 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1455
1456#define MLX5_CAP64_FPGA(mdev, cap) \
1457 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1458
1459#define MLX5_CAP_DEV_MEM(mdev, cap)\
1460 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1461
1462#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1463 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1464
1465#define MLX5_CAP_TLS(mdev, cap) \
1466 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1467
1468#define MLX5_CAP_DEV_EVENT(mdev, cap)\
1469 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1470
1471#define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1472 MLX5_GET(virtio_emulation_cap, \
1473 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1474
1475#define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1476 MLX5_GET64(virtio_emulation_cap, \
1477 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1478
1479#define MLX5_CAP_IPSEC(mdev, cap)\
1480 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1481
1482#define MLX5_CAP_CRYPTO(mdev, cap)\
1483 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1484
1485#define MLX5_CAP_MACSEC(mdev, cap)\
1486 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1487
1488#define MLX5_CAP_SHAMPO(mdev, cap) \
1489 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap)
1490
1491#define MLX5_CAP_PSP(mdev, cap)\
1492 MLX5_GET(psp_cap, (mdev)->caps.hca[MLX5_CAP_PSP]->cur, cap)
1493
1494enum {
1495 MLX5_CMD_STAT_OK = 0x0,
1496 MLX5_CMD_STAT_INT_ERR = 0x1,
1497 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1498 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1499 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1500 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1501 MLX5_CMD_STAT_RES_BUSY = 0x6,
1502 MLX5_CMD_STAT_NOT_READY = 0x7,
1503 MLX5_CMD_STAT_LIM_ERR = 0x8,
1504 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1505 MLX5_CMD_STAT_IX_ERR = 0xa,
1506 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1507 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1508 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1509 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1510 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1511 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1512};
1513
1514enum {
1515 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1516 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1517 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1518 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1519 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1520 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1521 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1522 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1523 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1524 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1525 MLX5_PHYSICAL_LAYER_RECOVERY_GROUP = 0x1a,
1526 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1527 MLX5_INFINIBAND_EXTENDED_PORT_COUNTERS_GROUP = 0x21,
1528 MLX5_RS_FEC_HISTOGRAM_GROUP = 0x23,
1529};
1530
1531enum {
1532 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1533};
1534
1535static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1536{
1537 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1538 return 0;
1539 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1540}
1541
1542#define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 6
1543#define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 4
1544#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1545#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1546#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1547#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1548 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1549 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1550
1551#endif /* MLX5_DEVICE_H */