Linux kernel mirror (for testing)
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linux
1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd
4 * http://www.samsung.com
5 */
6
7#ifndef __LINUX_MFD_SEC_RTC_H
8#define __LINUX_MFD_SEC_RTC_H
9
10enum s5m_rtc_reg {
11 S5M_RTC_SEC,
12 S5M_RTC_MIN,
13 S5M_RTC_HOUR,
14 S5M_RTC_WEEKDAY,
15 S5M_RTC_DATE,
16 S5M_RTC_MONTH,
17 S5M_RTC_YEAR1,
18 S5M_RTC_YEAR2,
19 S5M_ALARM0_SEC,
20 S5M_ALARM0_MIN,
21 S5M_ALARM0_HOUR,
22 S5M_ALARM0_WEEKDAY,
23 S5M_ALARM0_DATE,
24 S5M_ALARM0_MONTH,
25 S5M_ALARM0_YEAR1,
26 S5M_ALARM0_YEAR2,
27 S5M_ALARM1_SEC,
28 S5M_ALARM1_MIN,
29 S5M_ALARM1_HOUR,
30 S5M_ALARM1_WEEKDAY,
31 S5M_ALARM1_DATE,
32 S5M_ALARM1_MONTH,
33 S5M_ALARM1_YEAR1,
34 S5M_ALARM1_YEAR2,
35 S5M_ALARM0_CONF,
36 S5M_ALARM1_CONF,
37 S5M_RTC_STATUS,
38 S5M_WTSR_SMPL_CNTL,
39 S5M_RTC_UDR_CON,
40
41 S5M_RTC_REG_MAX,
42};
43
44enum s2mps_rtc_reg {
45 S2MPS_RTC_CTRL,
46 S2MPS_WTSR_SMPL_CNTL,
47 S2MPS_RTC_UDR_CON,
48 S2MPS_RSVD,
49 S2MPS_RTC_SEC,
50 S2MPS_RTC_MIN,
51 S2MPS_RTC_HOUR,
52 S2MPS_RTC_WEEKDAY,
53 S2MPS_RTC_DATE,
54 S2MPS_RTC_MONTH,
55 S2MPS_RTC_YEAR,
56 S2MPS_ALARM0_SEC,
57 S2MPS_ALARM0_MIN,
58 S2MPS_ALARM0_HOUR,
59 S2MPS_ALARM0_WEEKDAY,
60 S2MPS_ALARM0_DATE,
61 S2MPS_ALARM0_MONTH,
62 S2MPS_ALARM0_YEAR,
63 S2MPS_ALARM1_SEC,
64 S2MPS_ALARM1_MIN,
65 S2MPS_ALARM1_HOUR,
66 S2MPS_ALARM1_WEEKDAY,
67 S2MPS_ALARM1_DATE,
68 S2MPS_ALARM1_MONTH,
69 S2MPS_ALARM1_YEAR,
70 S2MPS_OFFSRC,
71
72 S2MPS_RTC_REG_MAX,
73};
74
75enum s2mpg10_rtc_reg {
76 S2MPG10_RTC_CTRL,
77 S2MPG10_RTC_UPDATE,
78 S2MPG10_RTC_SMPL,
79 S2MPG10_RTC_WTSR,
80 S2MPG10_RTC_CAP_SEL,
81 S2MPG10_RTC_MSEC,
82 S2MPG10_RTC_SEC,
83 S2MPG10_RTC_MIN,
84 S2MPG10_RTC_HOUR,
85 S2MPG10_RTC_WEEK,
86 S2MPG10_RTC_DAY,
87 S2MPG10_RTC_MON,
88 S2MPG10_RTC_YEAR,
89 S2MPG10_RTC_A0SEC,
90 S2MPG10_RTC_A0MIN,
91 S2MPG10_RTC_A0HOUR,
92 S2MPG10_RTC_A0WEEK,
93 S2MPG10_RTC_A0DAY,
94 S2MPG10_RTC_A0MON,
95 S2MPG10_RTC_A0YEAR,
96 S2MPG10_RTC_A1SEC,
97 S2MPG10_RTC_A1MIN,
98 S2MPG10_RTC_A1HOUR,
99 S2MPG10_RTC_A1WEEK,
100 S2MPG10_RTC_A1DAY,
101 S2MPG10_RTC_A1MON,
102 S2MPG10_RTC_A1YEAR,
103 S2MPG10_RTC_OSC_CTRL,
104};
105
106#define RTC_I2C_ADDR (0x0C >> 1)
107
108#define HOUR_12 (1 << 7)
109#define HOUR_AMPM (1 << 6)
110#define HOUR_PM (1 << 5)
111#define S5M_ALARM0_STATUS (1 << 1)
112#define S5M_ALARM1_STATUS (1 << 2)
113#define S5M_UPDATE_AD (1 << 0)
114
115#define S2MPS_ALARM0_STATUS (1 << 2)
116#define S2MPS_ALARM1_STATUS (1 << 1)
117
118/* RTC Control Register */
119#define BCD_EN_SHIFT 0
120#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
121#define MODEL24_SHIFT 1
122#define MODEL24_MASK (1 << MODEL24_SHIFT)
123/* RTC Update Register1 */
124#define S5M_RTC_UDR_SHIFT 0
125#define S5M_RTC_UDR_MASK (1 << S5M_RTC_UDR_SHIFT)
126#define S2MPS_RTC_WUDR_SHIFT 4
127#define S2MPS_RTC_WUDR_MASK (1 << S2MPS_RTC_WUDR_SHIFT)
128#define S2MPS15_RTC_AUDR_SHIFT 4
129#define S2MPS15_RTC_AUDR_MASK (1 << S2MPS15_RTC_AUDR_SHIFT)
130#define S2MPS13_RTC_AUDR_SHIFT 1
131#define S2MPS13_RTC_AUDR_MASK (1 << S2MPS13_RTC_AUDR_SHIFT)
132#define S2MPS15_RTC_WUDR_SHIFT 1
133#define S2MPS15_RTC_WUDR_MASK (1 << S2MPS15_RTC_WUDR_SHIFT)
134#define S2MPS_RTC_RUDR_SHIFT 0
135#define S2MPS_RTC_RUDR_MASK (1 << S2MPS_RTC_RUDR_SHIFT)
136#define RTC_TCON_SHIFT 1
137#define RTC_TCON_MASK (1 << RTC_TCON_SHIFT)
138#define S5M_RTC_TIME_EN_SHIFT 3
139#define S5M_RTC_TIME_EN_MASK (1 << S5M_RTC_TIME_EN_SHIFT)
140/*
141 * UDR_T field in S5M_RTC_UDR_CON register determines the time needed
142 * for updating alarm and time registers. Default is 7.32 ms.
143 */
144#define S5M_RTC_UDR_T_SHIFT 6
145#define S5M_RTC_UDR_T_MASK (0x3 << S5M_RTC_UDR_T_SHIFT)
146#define S5M_RTC_UDR_T_7320_US (0x0 << S5M_RTC_UDR_T_SHIFT)
147#define S5M_RTC_UDR_T_1830_US (0x1 << S5M_RTC_UDR_T_SHIFT)
148#define S5M_RTC_UDR_T_3660_US (0x2 << S5M_RTC_UDR_T_SHIFT)
149#define S5M_RTC_UDR_T_450_US (0x3 << S5M_RTC_UDR_T_SHIFT)
150
151/* RTC Hour register */
152#define HOUR_PM_SHIFT 6
153#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
154/* RTC Alarm Enable */
155#define ALARM_ENABLE_SHIFT 7
156#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
157
158/* WTSR & SMPL registers */
159#define SMPL_ENABLE_SHIFT 7
160#define SMPL_ENABLE_MASK (1 << SMPL_ENABLE_SHIFT)
161
162#define WTSR_ENABLE_SHIFT 6
163#define WTSR_ENABLE_MASK (1 << WTSR_ENABLE_SHIFT)
164
165#define S2MPG10_WTSR_COLDTIMER GENMASK(6, 5)
166#define S2MPG10_WTSR_COLDRST BIT(4)
167#define S2MPG10_WTSR_WTSRT GENMASK(3, 1)
168#define S2MPG10_WTSR_WTSR_EN BIT(0)
169
170#endif /* __LINUX_MFD_SEC_RTC_H */