tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / mfd / rohm-bd71828.h
at master 15 kB view raw
1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* Copyright (C) 2019 ROHM Semiconductors */ 3 4#ifndef __LINUX_MFD_BD71828_H__ 5#define __LINUX_MFD_BD71828_H__ 6 7#include <linux/bits.h> 8#include <linux/mfd/rohm-generic.h> 9#include <linux/mfd/rohm-shared.h> 10 11/* Regulator IDs */ 12enum { 13 BD71828_BUCK1, 14 BD71828_BUCK2, 15 BD71828_BUCK3, 16 BD71828_BUCK4, 17 BD71828_BUCK5, 18 BD71828_BUCK6, 19 BD71828_BUCK7, 20 BD71828_LDO1, 21 BD71828_LDO2, 22 BD71828_LDO3, 23 BD71828_LDO4, 24 BD71828_LDO5, 25 BD71828_LDO6, 26 BD71828_LDO_SNVS, 27 BD71828_REGULATOR_AMOUNT, 28}; 29 30#define BD71828_BUCK1267_VOLTS 0x100 31#define BD71828_BUCK3_VOLTS 0x20 32#define BD71828_BUCK4_VOLTS 0x40 33#define BD71828_BUCK5_VOLTS 0x20 34#define BD71828_LDO_VOLTS 0x40 35/* LDO6 is fixed 1.8V voltage */ 36#define BD71828_LDO_6_VOLTAGE 1800000 37 38/* Registers and masks*/ 39 40/* MODE control */ 41#define BD71828_REG_PS_CTRL_1 0x04 42#define BD71828_REG_PS_CTRL_2 0x05 43#define BD71828_REG_PS_CTRL_3 0x06 44 45#define BD71828_MASK_STATE_HBNT BIT(1) 46 47#define BD71828_MASK_RUN_LVL_CTRL 0x30 48 49/* Regulator control masks */ 50 51#define BD71828_MASK_RAMP_DELAY 0x6 52 53#define BD71828_MASK_RUN_EN 0x08 54#define BD71828_MASK_SUSP_EN 0x04 55#define BD71828_MASK_IDLE_EN 0x02 56#define BD71828_MASK_LPSR_EN 0x01 57 58#define BD71828_MASK_RUN0_EN 0x01 59#define BD71828_MASK_RUN1_EN 0x02 60#define BD71828_MASK_RUN2_EN 0x04 61#define BD71828_MASK_RUN3_EN 0x08 62 63#define BD71828_MASK_DVS_BUCK1_CTRL 0x10 64#define BD71828_DVS_BUCK1_CTRL_I2C 0 65#define BD71828_DVS_BUCK1_USE_RUNLVL 0x10 66 67#define BD71828_MASK_DVS_BUCK2_CTRL 0x20 68#define BD71828_DVS_BUCK2_CTRL_I2C 0 69#define BD71828_DVS_BUCK2_USE_RUNLVL 0x20 70 71#define BD71828_MASK_DVS_BUCK6_CTRL 0x40 72#define BD71828_DVS_BUCK6_CTRL_I2C 0 73#define BD71828_DVS_BUCK6_USE_RUNLVL 0x40 74 75#define BD71828_MASK_DVS_BUCK7_CTRL 0x80 76#define BD71828_DVS_BUCK7_CTRL_I2C 0 77#define BD71828_DVS_BUCK7_USE_RUNLVL 0x80 78 79#define BD71828_MASK_BUCK1267_VOLT 0xff 80#define BD71828_MASK_BUCK3_VOLT 0x1f 81#define BD71828_MASK_BUCK4_VOLT 0x3f 82#define BD71828_MASK_BUCK5_VOLT 0x1f 83#define BD71828_MASK_LDO_VOLT 0x3f 84 85/* Regulator control regs */ 86#define BD71828_REG_BUCK1_EN 0x08 87#define BD71828_REG_BUCK1_CTRL 0x09 88#define BD71828_REG_BUCK1_MODE 0x0a 89#define BD71828_REG_BUCK1_IDLE_VOLT 0x0b 90#define BD71828_REG_BUCK1_SUSP_VOLT 0x0c 91#define BD71828_REG_BUCK1_VOLT 0x0d 92 93#define BD71828_REG_BUCK2_EN 0x12 94#define BD71828_REG_BUCK2_CTRL 0x13 95#define BD71828_REG_BUCK2_MODE 0x14 96#define BD71828_REG_BUCK2_IDLE_VOLT 0x15 97#define BD71828_REG_BUCK2_SUSP_VOLT 0x16 98#define BD71828_REG_BUCK2_VOLT 0x17 99 100#define BD71828_REG_BUCK3_EN 0x1c 101#define BD71828_REG_BUCK3_MODE 0x1d 102#define BD71828_REG_BUCK3_VOLT 0x1e 103 104#define BD71828_REG_BUCK4_EN 0x1f 105#define BD71828_REG_BUCK4_MODE 0x20 106#define BD71828_REG_BUCK4_VOLT 0x21 107 108#define BD71828_REG_BUCK5_EN 0x22 109#define BD71828_REG_BUCK5_MODE 0x23 110#define BD71828_REG_BUCK5_VOLT 0x24 111 112#define BD71828_REG_BUCK6_EN 0x25 113#define BD71828_REG_BUCK6_CTRL 0x26 114#define BD71828_REG_BUCK6_MODE 0x27 115#define BD71828_REG_BUCK6_IDLE_VOLT 0x28 116#define BD71828_REG_BUCK6_SUSP_VOLT 0x29 117#define BD71828_REG_BUCK6_VOLT 0x2a 118 119#define BD71828_REG_BUCK7_EN 0x2f 120#define BD71828_REG_BUCK7_CTRL 0x30 121#define BD71828_REG_BUCK7_MODE 0x31 122#define BD71828_REG_BUCK7_IDLE_VOLT 0x32 123#define BD71828_REG_BUCK7_SUSP_VOLT 0x33 124#define BD71828_REG_BUCK7_VOLT 0x34 125 126#define BD71828_REG_LDO1_EN 0x39 127#define BD71828_REG_LDO1_VOLT 0x3a 128#define BD71828_REG_LDO2_EN 0x3b 129#define BD71828_REG_LDO2_VOLT 0x3c 130#define BD71828_REG_LDO3_EN 0x3d 131#define BD71828_REG_LDO3_VOLT 0x3e 132#define BD71828_REG_LDO4_EN 0x3f 133#define BD71828_REG_LDO4_VOLT 0x40 134#define BD71828_REG_LDO5_EN 0x41 135#define BD71828_REG_LDO5_VOLT 0x43 136#define BD71828_REG_LDO5_VOLT_OPT 0x42 137#define BD71828_REG_LDO6_EN 0x44 138#define BD71828_REG_LDO7_EN 0x45 139#define BD71828_REG_LDO7_VOLT 0x46 140 141/* GPIO */ 142 143#define BD71828_GPIO_DRIVE_MASK 0x2 144#define BD71828_GPIO_OPEN_DRAIN 0x0 145#define BD71828_GPIO_PUSH_PULL 0x2 146#define BD71828_GPIO_OUT_HI 0x1 147#define BD71828_GPIO_OUT_LO 0x0 148#define BD71828_GPIO_OUT_MASK 0x1 149 150#define BD71828_REG_GPIO_CTRL1 0x47 151#define BD71828_REG_GPIO_CTRL2 0x48 152#define BD71828_REG_GPIO_CTRL3 0x49 153#define BD71828_REG_IO_STAT 0xed 154 155/* clk */ 156#define BD71828_REG_OUT32K 0x4b 157 158/* RTC */ 159#define BD71828_REG_RTC_SEC 0x4c 160#define BD71828_REG_RTC_MINUTE 0x4d 161#define BD71828_REG_RTC_HOUR 0x4e 162#define BD71828_REG_RTC_WEEK 0x4f 163#define BD71828_REG_RTC_DAY 0x50 164#define BD71828_REG_RTC_MONTH 0x51 165#define BD71828_REG_RTC_YEAR 0x52 166 167#define BD71828_REG_RTC_ALM0_SEC 0x53 168#define BD71828_REG_RTC_ALM_START BD71828_REG_RTC_ALM0_SEC 169#define BD71828_REG_RTC_ALM0_MINUTE 0x54 170#define BD71828_REG_RTC_ALM0_HOUR 0x55 171#define BD71828_REG_RTC_ALM0_WEEK 0x56 172#define BD71828_REG_RTC_ALM0_DAY 0x57 173#define BD71828_REG_RTC_ALM0_MONTH 0x58 174#define BD71828_REG_RTC_ALM0_YEAR 0x59 175#define BD71828_REG_RTC_ALM0_MASK 0x61 176 177#define BD71828_REG_RTC_ALM1_SEC 0x5a 178#define BD71828_REG_RTC_ALM1_MINUTE 0x5b 179#define BD71828_REG_RTC_ALM1_HOUR 0x5c 180#define BD71828_REG_RTC_ALM1_WEEK 0x5d 181#define BD71828_REG_RTC_ALM1_DAY 0x5e 182#define BD71828_REG_RTC_ALM1_MONTH 0x5f 183#define BD71828_REG_RTC_ALM1_YEAR 0x60 184#define BD71828_REG_RTC_ALM1_MASK 0x62 185 186#define BD71828_REG_RTC_ALM2 0x63 187#define BD71828_REG_RTC_START BD71828_REG_RTC_SEC 188 189/* Charger/Battey */ 190#define BD71828_REG_CHG_STATE 0x65 191#define BD71828_REG_CHG_FULL 0xd2 192#define BD71828_REG_CHG_EN 0x6F 193#define BD71828_REG_DCIN_STAT 0x68 194#define BD71828_MASK_DCIN_DET 0x01 195#define BD71828_REG_VDCIN_U 0x9c 196#define BD71828_MASK_CHG_EN 0x01 197#define BD71828_CHG_MASK_DCIN_U 0x0f 198#define BD71828_REG_BAT_STAT 0x67 199#define BD71828_REG_BAT_TEMP 0x6c 200#define BD71828_MASK_BAT_TEMP 0x07 201#define BD71828_BAT_TEMP_OPEN 0x07 202#define BD71828_MASK_BAT_DET 0x20 203#define BD71828_MASK_BAT_DET_DONE 0x10 204#define BD71828_REG_CHG_STATE 0x65 205#define BD71828_REG_VBAT_U 0x8c 206#define BD71828_MASK_VBAT_U 0x0f 207#define BD71828_REG_VBAT_REX_AVG_U 0x92 208 209#define BD71828_REG_OCV_PWRON_U 0x8A 210 211#define BD71828_REG_VBAT_MIN_AVG_U 0x8e 212#define BD71828_REG_VBAT_MIN_AVG_L 0x8f 213 214#define BD71828_REG_CC_CNT3 0xb5 215#define BD71828_REG_CC_CNT2 0xb6 216#define BD71828_REG_CC_CNT1 0xb7 217#define BD71828_REG_CC_CNT0 0xb8 218#define BD71828_REG_CC_CURCD_AVG_U 0xb2 219#define BD71828_MASK_CC_CURCD_AVG_U 0x3f 220#define BD71828_MASK_CC_CUR_DIR 0x80 221#define BD71828_REG_VM_BTMP_U 0xa1 222#define BD71828_REG_VM_BTMP_L 0xa2 223#define BD71828_MASK_VM_BTMP_U 0x0f 224#define BD71828_REG_COULOMB_CTRL 0xc4 225#define BD71828_REG_COULOMB_CTRL2 0xd2 226#define BD71828_MASK_REX_CC_CLR 0x01 227#define BD71828_MASK_FULL_CC_CLR 0x10 228#define BD71828_REG_CC_CNT_FULL3 0xbd 229#define BD71828_REG_CC_CNT_CHG3 0xc1 230 231#define BD71828_REG_VBAT_INITIAL1_U 0x86 232#define BD71828_REG_VBAT_INITIAL1_L 0x87 233 234#define BD71828_REG_VBAT_INITIAL2_U 0x88 235#define BD71828_REG_VBAT_INITIAL2_L 0x89 236 237#define BD71828_REG_IBAT_U 0xb0 238#define BD71828_REG_IBAT_L 0xb1 239 240#define BD71828_REG_IBAT_AVG_U 0xb2 241#define BD71828_REG_IBAT_AVG_L 0xb3 242 243#define BD71828_REG_VSYS_AVG_U 0x96 244#define BD71828_REG_VSYS_AVG_L 0x97 245#define BD71828_REG_VSYS_MIN_AVG_U 0x98 246#define BD71828_REG_VSYS_MIN_AVG_L 0x99 247#define BD71828_REG_CHG_SET1 0x75 248#define BD71828_REG_ALM_VBAT_LIMIT_U 0xaa 249#define BD71828_REG_BATCAP_MON_LIMIT_U 0xcc 250#define BD71828_REG_CONF 0x64 251 252#define BD71828_REG_DCIN_CLPS 0x71 253 254#define BD71828_REG_MEAS_CLEAR 0xaf 255 256/* LEDs */ 257#define BD71828_REG_LED_CTRL 0x4A 258#define BD71828_MASK_LED_AMBER 0x80 259#define BD71828_MASK_LED_GREEN 0x40 260#define BD71828_LED_ON 0xff 261#define BD71828_LED_OFF 0x0 262 263/* IRQ registers */ 264#define BD71828_REG_INT_MASK_BUCK 0xd3 265#define BD71828_REG_INT_MASK_DCIN1 0xd4 266#define BD71828_REG_INT_MASK_DCIN2 0xd5 267#define BD71828_REG_INT_MASK_VSYS 0xd6 268#define BD71828_REG_INT_MASK_CHG 0xd7 269#define BD71828_REG_INT_MASK_BAT 0xd8 270#define BD71828_REG_INT_MASK_BAT_MON1 0xd9 271#define BD71828_REG_INT_MASK_BAT_MON2 0xda 272#define BD71828_REG_INT_MASK_BAT_MON3 0xdb 273#define BD71828_REG_INT_MASK_BAT_MON4 0xdc 274#define BD71828_REG_INT_MASK_TEMP 0xdd 275#define BD71828_REG_INT_MASK_RTC 0xde 276 277#define BD71828_REG_INT_MAIN 0xdf 278#define BD71828_REG_INT_BUCK 0xe0 279#define BD71828_REG_INT_DCIN1 0xe1 280#define BD71828_REG_INT_DCIN2 0xe2 281#define BD71828_REG_INT_VSYS 0xe3 282#define BD71828_REG_INT_CHG 0xe4 283#define BD71828_REG_INT_BAT 0xe5 284#define BD71828_REG_INT_BAT_MON1 0xe6 285#define BD71828_REG_INT_BAT_MON2 0xe7 286#define BD71828_REG_INT_BAT_MON3 0xe8 287#define BD71828_REG_INT_BAT_MON4 0xe9 288#define BD71828_REG_INT_TEMP 0xea 289#define BD71828_REG_INT_RTC 0xeb 290#define BD71828_REG_INT_UPDATE 0xec 291 292#define BD71828_MAX_REGISTER BD71828_REG_IO_STAT 293 294/* Masks for main IRQ register bits */ 295enum { 296 BD71828_INT_BUCK, 297#define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK) 298 BD71828_INT_DCIN, 299#define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN) 300 BD71828_INT_VSYS, 301#define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS) 302 BD71828_INT_CHG, 303#define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG) 304 BD71828_INT_BAT, 305#define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT) 306 BD71828_INT_BAT_MON, 307#define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON) 308 BD71828_INT_TEMP, 309#define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP) 310 BD71828_INT_RTC, 311#define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC) 312}; 313 314/* Interrupts */ 315enum { 316 /* BUCK reg interrupts */ 317 BD71828_INT_BUCK1_OCP, 318 BD71828_INT_BUCK2_OCP, 319 BD71828_INT_BUCK3_OCP, 320 BD71828_INT_BUCK4_OCP, 321 BD71828_INT_BUCK5_OCP, 322 BD71828_INT_BUCK6_OCP, 323 BD71828_INT_BUCK7_OCP, 324 BD71828_INT_PGFAULT, 325 /* DCIN1 interrupts */ 326 BD71828_INT_DCIN_DET, 327 BD71828_INT_DCIN_RMV, 328 BD71828_INT_CLPS_OUT, 329 BD71828_INT_CLPS_IN, 330 /* DCIN2 interrupts */ 331 BD71828_INT_DCIN_MON_RES, 332 BD71828_INT_DCIN_MON_DET, 333 BD71828_INT_LONGPUSH, 334 BD71828_INT_MIDPUSH, 335 BD71828_INT_SHORTPUSH, 336 BD71828_INT_PUSH, 337 BD71828_INT_WDOG, 338 BD71828_INT_SWRESET, 339 /* Vsys */ 340 BD71828_INT_VSYS_UV_RES, 341 BD71828_INT_VSYS_UV_DET, 342 BD71828_INT_VSYS_LOW_RES, 343 BD71828_INT_VSYS_LOW_DET, 344 BD71828_INT_VSYS_HALL_IN, 345 BD71828_INT_VSYS_HALL_TOGGLE, 346 BD71828_INT_VSYS_MON_RES, 347 BD71828_INT_VSYS_MON_DET, 348 /* Charger */ 349 BD71828_INT_CHG_DCIN_ILIM, 350 BD71828_INT_CHG_TOPOFF_TO_DONE, 351 BD71828_INT_CHG_WDG_TEMP, 352 BD71828_INT_CHG_WDG_TIME, 353 BD71828_INT_CHG_RECHARGE_RES, 354 BD71828_INT_CHG_RECHARGE_DET, 355 BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 356 BD71828_INT_CHG_STATE_TRANSITION, 357 /* Battery */ 358 BD71828_INT_BAT_TEMP_NORMAL, 359 BD71828_INT_BAT_TEMP_ERANGE, 360 BD71828_INT_BAT_TEMP_WARN, 361 BD71828_INT_BAT_REMOVED, 362 BD71828_INT_BAT_DETECTED, 363 BD71828_INT_THERM_REMOVED, 364 BD71828_INT_THERM_DETECTED, 365 /* Battery Mon 1 */ 366 BD71828_INT_BAT_DEAD, 367 BD71828_INT_BAT_SHORTC_RES, 368 BD71828_INT_BAT_SHORTC_DET, 369 BD71828_INT_BAT_LOW_VOLT_RES, 370 BD71828_INT_BAT_LOW_VOLT_DET, 371 BD71828_INT_BAT_OVER_VOLT_RES, 372 BD71828_INT_BAT_OVER_VOLT_DET, 373 /* Battery Mon 2 */ 374 BD71828_INT_BAT_MON_RES, 375 BD71828_INT_BAT_MON_DET, 376 /* Battery Mon 3 (Coulomb counter) */ 377 BD71828_INT_BAT_CC_MON1, 378 BD71828_INT_BAT_CC_MON2, 379 BD71828_INT_BAT_CC_MON3, 380 /* Battery Mon 4 */ 381 BD71828_INT_BAT_OVER_CURR_1_RES, 382 BD71828_INT_BAT_OVER_CURR_1_DET, 383 BD71828_INT_BAT_OVER_CURR_2_RES, 384 BD71828_INT_BAT_OVER_CURR_2_DET, 385 BD71828_INT_BAT_OVER_CURR_3_RES, 386 BD71828_INT_BAT_OVER_CURR_3_DET, 387 /* Temperature */ 388 BD71828_INT_TEMP_BAT_LOW_RES, 389 BD71828_INT_TEMP_BAT_LOW_DET, 390 BD71828_INT_TEMP_BAT_HI_RES, 391 BD71828_INT_TEMP_BAT_HI_DET, 392 BD71828_INT_TEMP_CHIP_OVER_125_RES, 393 BD71828_INT_TEMP_CHIP_OVER_125_DET, 394 BD71828_INT_TEMP_CHIP_OVER_VF_DET, 395 BD71828_INT_TEMP_CHIP_OVER_VF_RES, 396 /* RTC Alarm */ 397 BD71828_INT_RTC0, 398 BD71828_INT_RTC1, 399 BD71828_INT_RTC2, 400}; 401 402#define BD71828_INT_BUCK1_OCP_MASK 0x1 403#define BD71828_INT_BUCK2_OCP_MASK 0x2 404#define BD71828_INT_BUCK3_OCP_MASK 0x4 405#define BD71828_INT_BUCK4_OCP_MASK 0x8 406#define BD71828_INT_BUCK5_OCP_MASK 0x10 407#define BD71828_INT_BUCK6_OCP_MASK 0x20 408#define BD71828_INT_BUCK7_OCP_MASK 0x40 409#define BD71828_INT_PGFAULT_MASK 0x80 410 411#define BD71828_INT_DCIN_DET_MASK 0x1 412#define BD71828_INT_DCIN_RMV_MASK 0x2 413#define BD71828_INT_CLPS_OUT_MASK 0x4 414#define BD71828_INT_CLPS_IN_MASK 0x8 415 /* DCIN2 interrupts */ 416#define BD71828_INT_DCIN_MON_RES_MASK 0x1 417#define BD71828_INT_DCIN_MON_DET_MASK 0x2 418#define BD71828_INT_LONGPUSH_MASK 0x4 419#define BD71828_INT_MIDPUSH_MASK 0x8 420#define BD71828_INT_SHORTPUSH_MASK 0x10 421#define BD71828_INT_PUSH_MASK 0x20 422#define BD71828_INT_WDOG_MASK 0x40 423#define BD71828_INT_SWRESET_MASK 0x80 424 /* Vsys */ 425#define BD71828_INT_VSYS_UV_RES_MASK 0x1 426#define BD71828_INT_VSYS_UV_DET_MASK 0x2 427#define BD71828_INT_VSYS_LOW_RES_MASK 0x4 428#define BD71828_INT_VSYS_LOW_DET_MASK 0x8 429#define BD71828_INT_VSYS_HALL_IN_MASK 0x10 430#define BD71828_INT_VSYS_HALL_TOGGLE_MASK 0x20 431#define BD71828_INT_VSYS_MON_RES_MASK 0x40 432#define BD71828_INT_VSYS_MON_DET_MASK 0x80 433 /* Charger */ 434#define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1 435#define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK 0x2 436#define BD71828_INT_CHG_WDG_TEMP_MASK 0x4 437#define BD71828_INT_CHG_WDG_TIME_MASK 0x8 438#define BD71828_INT_CHG_RECHARGE_RES_MASK 0x10 439#define BD71828_INT_CHG_RECHARGE_DET_MASK 0x20 440#define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40 441#define BD71828_INT_CHG_STATE_TRANSITION_MASK 0x80 442 /* Battery */ 443#define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1 444#define BD71828_INT_BAT_TEMP_ERANGE_MASK 0x2 445#define BD71828_INT_BAT_TEMP_WARN_MASK 0x4 446#define BD71828_INT_BAT_REMOVED_MASK 0x10 447#define BD71828_INT_BAT_DETECTED_MASK 0x20 448#define BD71828_INT_THERM_REMOVED_MASK 0x40 449#define BD71828_INT_THERM_DETECTED_MASK 0x80 450 /* Battery Mon 1 */ 451#define BD71828_INT_BAT_DEAD_MASK 0x2 452#define BD71828_INT_BAT_SHORTC_RES_MASK 0x4 453#define BD71828_INT_BAT_SHORTC_DET_MASK 0x8 454#define BD71828_INT_BAT_LOW_VOLT_RES_MASK 0x10 455#define BD71828_INT_BAT_LOW_VOLT_DET_MASK 0x20 456#define BD71828_INT_BAT_OVER_VOLT_RES_MASK 0x40 457#define BD71828_INT_BAT_OVER_VOLT_DET_MASK 0x80 458 /* Battery Mon 2 */ 459#define BD71828_INT_BAT_MON_RES_MASK 0x1 460#define BD71828_INT_BAT_MON_DET_MASK 0x2 461 /* Battery Mon 3 (Coulomb counter) */ 462#define BD71828_INT_BAT_CC_MON1_MASK 0x1 463#define BD71828_INT_BAT_CC_MON2_MASK 0x2 464#define BD71828_INT_BAT_CC_MON3_MASK 0x4 465 /* Battery Mon 4 */ 466#define BD71828_INT_BAT_OVER_CURR_1_RES_MASK 0x1 467#define BD71828_INT_BAT_OVER_CURR_1_DET_MASK 0x2 468#define BD71828_INT_BAT_OVER_CURR_2_RES_MASK 0x4 469#define BD71828_INT_BAT_OVER_CURR_2_DET_MASK 0x8 470#define BD71828_INT_BAT_OVER_CURR_3_RES_MASK 0x10 471#define BD71828_INT_BAT_OVER_CURR_3_DET_MASK 0x20 472 /* Temperature */ 473#define BD71828_INT_TEMP_BAT_LOW_RES_MASK 0x1 474#define BD71828_INT_TEMP_BAT_LOW_DET_MASK 0x2 475#define BD71828_INT_TEMP_BAT_HI_RES_MASK 0x4 476#define BD71828_INT_TEMP_BAT_HI_DET_MASK 0x8 477#define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK 0x10 478#define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK 0x20 479#define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK 0x40 480#define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK 0x80 481 /* RTC Alarm */ 482#define BD71828_INT_RTC0_MASK 0x1 483#define BD71828_INT_RTC1_MASK 0x2 484#define BD71828_INT_RTC2_MASK 0x4 485 486#define BD71828_OUT_TYPE_MASK 0x2 487#define BD71828_OUT_TYPE_OPEN_DRAIN 0x0 488#define BD71828_OUT_TYPE_CMOS 0x2 489 490#endif /* __LINUX_MFD_BD71828_H__ */