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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * TI/National Semiconductor LP3943 Device
4 *
5 * Copyright 2013 Texas Instruments
6 *
7 * Author: Milo Kim <milo.kim@ti.com>
8 */
9
10#ifndef __MFD_LP3943_H__
11#define __MFD_LP3943_H__
12
13#include <linux/gpio.h>
14#include <linux/regmap.h>
15
16/* Registers */
17#define LP3943_REG_GPIO_A 0x00
18#define LP3943_REG_GPIO_B 0x01
19#define LP3943_REG_PRESCALE0 0x02
20#define LP3943_REG_PWM0 0x03
21#define LP3943_REG_PRESCALE1 0x04
22#define LP3943_REG_PWM1 0x05
23#define LP3943_REG_MUX0 0x06
24#define LP3943_REG_MUX1 0x07
25#define LP3943_REG_MUX2 0x08
26#define LP3943_REG_MUX3 0x09
27
28/* Bit description for LP3943_REG_MUX0 ~ 3 */
29#define LP3943_GPIO_IN 0x00
30#define LP3943_GPIO_OUT_HIGH 0x00
31#define LP3943_GPIO_OUT_LOW 0x01
32#define LP3943_DIM_PWM0 0x02
33#define LP3943_DIM_PWM1 0x03
34
35#define LP3943_NUM_PWMS 2
36
37enum lp3943_pwm_output {
38 LP3943_PWM_OUT0,
39 LP3943_PWM_OUT1,
40 LP3943_PWM_OUT2,
41 LP3943_PWM_OUT3,
42 LP3943_PWM_OUT4,
43 LP3943_PWM_OUT5,
44 LP3943_PWM_OUT6,
45 LP3943_PWM_OUT7,
46 LP3943_PWM_OUT8,
47 LP3943_PWM_OUT9,
48 LP3943_PWM_OUT10,
49 LP3943_PWM_OUT11,
50 LP3943_PWM_OUT12,
51 LP3943_PWM_OUT13,
52 LP3943_PWM_OUT14,
53 LP3943_PWM_OUT15,
54};
55
56/*
57 * struct lp3943_pwm_map
58 * @output: Output pins which are mapped to each PWM channel
59 * @num_outputs: Number of outputs
60 */
61struct lp3943_pwm_map {
62 enum lp3943_pwm_output *output;
63 int num_outputs;
64};
65
66/*
67 * struct lp3943_platform_data
68 * @pwms: Output channel definitions for PWM channel 0 and 1
69 */
70struct lp3943_platform_data {
71 struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS];
72};
73
74/*
75 * struct lp3943_reg_cfg
76 * @reg: Register address
77 * @mask: Register bit mask to be updated
78 * @shift: Register bit shift
79 */
80struct lp3943_reg_cfg {
81 u8 reg;
82 u8 mask;
83 u8 shift;
84};
85
86/*
87 * struct lp3943
88 * @dev: Parent device pointer
89 * @regmap: Used for I2C communication on accessing registers
90 * @pdata: LP3943 platform specific data
91 * @mux_cfg: Register configuration for pin MUX
92 * @pin_used: Bit mask for output pin used.
93 * This bitmask is used for pin assignment management.
94 * 1 = pin used, 0 = available.
95 * Only LSB 16 bits are used, but it is unsigned long type
96 * for atomic bitwise operations.
97 */
98struct lp3943 {
99 struct device *dev;
100 struct regmap *regmap;
101 struct lp3943_platform_data *pdata;
102 const struct lp3943_reg_cfg *mux_cfg;
103 unsigned long pin_used;
104};
105
106int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read);
107int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data);
108int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data);
109#endif