tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom
kernel / include / linux / bnxt / hsi.h
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1/* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2014-2018 Broadcom Limited 5 * Copyright (c) 2018-2025 Broadcom Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation. 10 * 11 * DO NOT MODIFY!!! This file is automatically generated. 12 */ 13 14#ifndef _BNXT_HSI_H_ 15#define _BNXT_HSI_H_ 16 17/* hwrm_cmd_hdr (size:128b/16B) */ 18struct hwrm_cmd_hdr { 19 __le16 req_type; 20 __le16 cmpl_ring; 21 __le16 seq_id; 22 __le16 target_id; 23 __le64 resp_addr; 24}; 25 26/* hwrm_resp_hdr (size:64b/8B) */ 27struct hwrm_resp_hdr { 28 __le16 error_code; 29 __le16 req_type; 30 __le16 seq_id; 31 __le16 resp_len; 32}; 33 34#define CMD_DISCR_TLV_ENCAP 0x8000UL 35#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 36 37 38#define TLV_TYPE_HWRM_REQUEST 0x1UL 39#define TLV_TYPE_HWRM_RESPONSE 0x2UL 40#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 41#define TLV_TYPE_QUERY_ROCE_CC_GEN1 0x4UL 42#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 0x5UL 43#define TLV_TYPE_QUERY_ROCE_CC_GEN2 0x6UL 44#define TLV_TYPE_MODIFY_ROCE_CC_GEN2 0x7UL 45#define TLV_TYPE_QUERY_ROCE_CC_GEN1_EXT 0x8UL 46#define TLV_TYPE_MODIFY_ROCE_CC_GEN1_EXT 0x9UL 47#define TLV_TYPE_QUERY_ROCE_CC_GEN2_EXT 0xaUL 48#define TLV_TYPE_MODIFY_ROCE_CC_GEN2_EXT 0xbUL 49#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL 50#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 51#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 52#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 53#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS 0x8006UL 54#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY 0x8007UL 55#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 56#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY 0x8009UL 57#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 0x800aUL 58#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS 59 60 61/* tlv (size:64b/8B) */ 62struct tlv { 63 __le16 cmd_discr; 64 u8 reserved_8b; 65 u8 flags; 66 #define TLV_FLAGS_MORE 0x1UL 67 #define TLV_FLAGS_MORE_LAST 0x0UL 68 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 69 #define TLV_FLAGS_REQUIRED 0x2UL 70 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 71 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 72 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 73 __le16 tlv_type; 74 __le16 length; 75}; 76 77/* input (size:128b/16B) */ 78struct input { 79 __le16 req_type; 80 __le16 cmpl_ring; 81 __le16 seq_id; 82 __le16 target_id; 83 __le64 resp_addr; 84}; 85 86/* output (size:64b/8B) */ 87struct output { 88 __le16 error_code; 89 __le16 req_type; 90 __le16 seq_id; 91 __le16 resp_len; 92}; 93 94/* hwrm_short_input (size:128b/16B) */ 95struct hwrm_short_input { 96 __le16 req_type; 97 __le16 signature; 98 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 99 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 100 __le16 target_id; 101 #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL 102 #define SHORT_REQ_TARGET_ID_TOOLS 0xfffdUL 103 #define SHORT_REQ_TARGET_ID_LAST SHORT_REQ_TARGET_ID_TOOLS 104 __le16 size; 105 __le64 req_addr; 106}; 107 108/* cmd_nums (size:64b/8B) */ 109struct cmd_nums { 110 __le16 req_type; 111 #define HWRM_VER_GET 0x0UL 112 #define HWRM_FUNC_ECHO_RESPONSE 0xbUL 113 #define HWRM_ERROR_RECOVERY_QCFG 0xcUL 114 #define HWRM_FUNC_DRV_IF_CHANGE 0xdUL 115 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 116 #define HWRM_FUNC_VF_CFG 0xfUL 117 #define HWRM_RESERVED1 0x10UL 118 #define HWRM_FUNC_RESET 0x11UL 119 #define HWRM_FUNC_GETFID 0x12UL 120 #define HWRM_FUNC_VF_ALLOC 0x13UL 121 #define HWRM_FUNC_VF_FREE 0x14UL 122 #define HWRM_FUNC_QCAPS 0x15UL 123 #define HWRM_FUNC_QCFG 0x16UL 124 #define HWRM_FUNC_CFG 0x17UL 125 #define HWRM_FUNC_QSTATS 0x18UL 126 #define HWRM_FUNC_CLR_STATS 0x19UL 127 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 128 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 129 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 130 #define HWRM_FUNC_DRV_RGTR 0x1dUL 131 #define HWRM_FUNC_DRV_QVER 0x1eUL 132 #define HWRM_FUNC_BUF_RGTR 0x1fUL 133 #define HWRM_PORT_PHY_CFG 0x20UL 134 #define HWRM_PORT_MAC_CFG 0x21UL 135 #define HWRM_PORT_TS_QUERY 0x22UL 136 #define HWRM_PORT_QSTATS 0x23UL 137 #define HWRM_PORT_LPBK_QSTATS 0x24UL 138 #define HWRM_PORT_CLR_STATS 0x25UL 139 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 140 #define HWRM_PORT_PHY_QCFG 0x27UL 141 #define HWRM_PORT_MAC_QCFG 0x28UL 142 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 143 #define HWRM_PORT_PHY_QCAPS 0x2aUL 144 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 145 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 146 #define HWRM_PORT_LED_CFG 0x2dUL 147 #define HWRM_PORT_LED_QCFG 0x2eUL 148 #define HWRM_PORT_LED_QCAPS 0x2fUL 149 #define HWRM_QUEUE_QPORTCFG 0x30UL 150 #define HWRM_QUEUE_QCFG 0x31UL 151 #define HWRM_QUEUE_CFG 0x32UL 152 #define HWRM_FUNC_VLAN_CFG 0x33UL 153 #define HWRM_FUNC_VLAN_QCFG 0x34UL 154 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 155 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 156 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 157 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 158 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 159 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 160 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 161 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 162 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 163 #define HWRM_VNIC_ALLOC 0x40UL 164 #define HWRM_VNIC_FREE 0x41UL 165 #define HWRM_VNIC_CFG 0x42UL 166 #define HWRM_VNIC_QCFG 0x43UL 167 #define HWRM_VNIC_TPA_CFG 0x44UL 168 #define HWRM_VNIC_TPA_QCFG 0x45UL 169 #define HWRM_VNIC_RSS_CFG 0x46UL 170 #define HWRM_VNIC_RSS_QCFG 0x47UL 171 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 172 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 173 #define HWRM_VNIC_QCAPS 0x4aUL 174 #define HWRM_VNIC_UPDATE 0x4bUL 175 #define HWRM_RING_ALLOC 0x50UL 176 #define HWRM_RING_FREE 0x51UL 177 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 178 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 179 #define HWRM_RING_AGGINT_QCAPS 0x54UL 180 #define HWRM_RING_SCHQ_ALLOC 0x55UL 181 #define HWRM_RING_SCHQ_CFG 0x56UL 182 #define HWRM_RING_SCHQ_FREE 0x57UL 183 #define HWRM_RING_RESET 0x5eUL 184 #define HWRM_RING_GRP_ALLOC 0x60UL 185 #define HWRM_RING_GRP_FREE 0x61UL 186 #define HWRM_RING_CFG 0x62UL 187 #define HWRM_RING_QCFG 0x63UL 188 #define HWRM_RESERVED5 0x64UL 189 #define HWRM_RESERVED6 0x65UL 190 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 191 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 192 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 193 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 194 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 195 #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 196 #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 197 #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 198 #define HWRM_QUEUE_GLOBAL_CFG 0x86UL 199 #define HWRM_QUEUE_GLOBAL_QCFG 0x87UL 200 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_QCFG 0x88UL 201 #define HWRM_QUEUE_ADPTV_QOS_RX_FEATURE_CFG 0x89UL 202 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_QCFG 0x8aUL 203 #define HWRM_QUEUE_ADPTV_QOS_TX_FEATURE_CFG 0x8bUL 204 #define HWRM_QUEUE_QCAPS 0x8cUL 205 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_QCFG 0x8dUL 206 #define HWRM_QUEUE_ADPTV_QOS_RX_TUNING_CFG 0x8eUL 207 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_QCFG 0x8fUL 208 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 209 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 210 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 211 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 212 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 213 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 214 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 215 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 216 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 217 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 218 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 219 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 220 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 221 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 222 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 223 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 224 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 225 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 226 #define HWRM_QUEUE_ADPTV_QOS_TX_TUNING_CFG 0xa3UL 227 #define HWRM_STAT_CTX_ENG_QUERY 0xafUL 228 #define HWRM_STAT_CTX_ALLOC 0xb0UL 229 #define HWRM_STAT_CTX_FREE 0xb1UL 230 #define HWRM_STAT_CTX_QUERY 0xb2UL 231 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 232 #define HWRM_PORT_QSTATS_EXT 0xb4UL 233 #define HWRM_PORT_PHY_MDIO_WRITE 0xb5UL 234 #define HWRM_PORT_PHY_MDIO_READ 0xb6UL 235 #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE 0xb7UL 236 #define HWRM_PORT_PHY_MDIO_BUS_RELEASE 0xb8UL 237 #define HWRM_PORT_QSTATS_EXT_PFC_WD 0xb9UL 238 #define HWRM_RESERVED7 0xbaUL 239 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 240 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 241 #define HWRM_PORT_ECN_QSTATS 0xbdUL 242 #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 243 #define HWRM_FW_LIVEPATCH 0xbfUL 244 #define HWRM_FW_RESET 0xc0UL 245 #define HWRM_FW_QSTATUS 0xc1UL 246 #define HWRM_FW_HEALTH_CHECK 0xc2UL 247 #define HWRM_FW_SYNC 0xc3UL 248 #define HWRM_FW_STATE_QCAPS 0xc4UL 249 #define HWRM_FW_STATE_QUIESCE 0xc5UL 250 #define HWRM_FW_STATE_BACKUP 0xc6UL 251 #define HWRM_FW_STATE_RESTORE 0xc7UL 252 #define HWRM_FW_SET_TIME 0xc8UL 253 #define HWRM_FW_GET_TIME 0xc9UL 254 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 255 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 256 #define HWRM_FW_IPC_MAILBOX 0xccUL 257 #define HWRM_FW_ECN_CFG 0xcdUL 258 #define HWRM_FW_ECN_QCFG 0xceUL 259 #define HWRM_FW_SECURE_CFG 0xcfUL 260 #define HWRM_EXEC_FWD_RESP 0xd0UL 261 #define HWRM_REJECT_FWD_RESP 0xd1UL 262 #define HWRM_FWD_RESP 0xd2UL 263 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 264 #define HWRM_OEM_CMD 0xd4UL 265 #define HWRM_PORT_PRBS_TEST 0xd5UL 266 #define HWRM_PORT_SFP_SIDEBAND_CFG 0xd6UL 267 #define HWRM_PORT_SFP_SIDEBAND_QCFG 0xd7UL 268 #define HWRM_FW_STATE_UNQUIESCE 0xd8UL 269 #define HWRM_PORT_DSC_DUMP 0xd9UL 270 #define HWRM_PORT_EP_TX_QCFG 0xdaUL 271 #define HWRM_PORT_EP_TX_CFG 0xdbUL 272 #define HWRM_PORT_CFG 0xdcUL 273 #define HWRM_PORT_QCFG 0xddUL 274 #define HWRM_PORT_MAC_QCAPS 0xdfUL 275 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 276 #define HWRM_REG_POWER_QUERY 0xe1UL 277 #define HWRM_CORE_FREQUENCY_QUERY 0xe2UL 278 #define HWRM_REG_POWER_HISTOGRAM 0xe3UL 279 #define HWRM_MONITOR_PAX_HISTOGRAM_START 0xe4UL 280 #define HWRM_MONITOR_PAX_HISTOGRAM_COLLECT 0xe5UL 281 #define HWRM_STAT_QUERY_ROCE_STATS 0xe6UL 282 #define HWRM_STAT_QUERY_ROCE_STATS_EXT 0xe7UL 283 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 284 #define HWRM_WOL_FILTER_FREE 0xf1UL 285 #define HWRM_WOL_FILTER_QCFG 0xf2UL 286 #define HWRM_WOL_REASON_QCFG 0xf3UL 287 #define HWRM_CFA_METER_QCAPS 0xf4UL 288 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 289 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 290 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 291 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 292 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 293 #define HWRM_CFA_METER_INSTANCE_CFG 0xfaUL 294 #define HWRM_CFA_VFR_ALLOC 0xfdUL 295 #define HWRM_CFA_VFR_FREE 0xfeUL 296 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 297 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 298 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 299 #define HWRM_CFA_FLOW_ALLOC 0x103UL 300 #define HWRM_CFA_FLOW_FREE 0x104UL 301 #define HWRM_CFA_FLOW_FLUSH 0x105UL 302 #define HWRM_CFA_FLOW_STATS 0x106UL 303 #define HWRM_CFA_FLOW_INFO 0x107UL 304 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 305 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 306 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 307 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 308 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 309 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 310 #define HWRM_CFA_PAIR_FREE 0x10eUL 311 #define HWRM_CFA_PAIR_INFO 0x10fUL 312 #define HWRM_FW_IPC_MSG 0x110UL 313 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 314 #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE 0x112UL 315 #define HWRM_CFA_FLOW_AGING_TIMER_RESET 0x113UL 316 #define HWRM_CFA_FLOW_AGING_CFG 0x114UL 317 #define HWRM_CFA_FLOW_AGING_QCFG 0x115UL 318 #define HWRM_CFA_FLOW_AGING_QCAPS 0x116UL 319 #define HWRM_CFA_CTX_MEM_RGTR 0x117UL 320 #define HWRM_CFA_CTX_MEM_UNRGTR 0x118UL 321 #define HWRM_CFA_CTX_MEM_QCTX 0x119UL 322 #define HWRM_CFA_CTX_MEM_QCAPS 0x11aUL 323 #define HWRM_CFA_COUNTER_QCAPS 0x11bUL 324 #define HWRM_CFA_COUNTER_CFG 0x11cUL 325 #define HWRM_CFA_COUNTER_QCFG 0x11dUL 326 #define HWRM_CFA_COUNTER_QSTATS 0x11eUL 327 #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG 0x11fUL 328 #define HWRM_CFA_EEM_QCAPS 0x120UL 329 #define HWRM_CFA_EEM_CFG 0x121UL 330 #define HWRM_CFA_EEM_QCFG 0x122UL 331 #define HWRM_CFA_EEM_OP 0x123UL 332 #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS 0x124UL 333 #define HWRM_CFA_TFLIB 0x125UL 334 #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR 0x126UL 335 #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR 0x127UL 336 #define HWRM_CFA_TLS_FILTER_ALLOC 0x128UL 337 #define HWRM_CFA_TLS_FILTER_FREE 0x129UL 338 #define HWRM_CFA_RELEASE_AFM_FUNC 0x12aUL 339 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 340 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 341 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 342 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 343 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 344 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 345 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 346 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 347 #define HWRM_ENGINE_CKV_KEY_LABEL_CFG 0x136UL 348 #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG 0x137UL 349 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 350 #define HWRM_ENGINE_QG_QUERY 0x13dUL 351 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 352 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 353 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 354 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 355 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 356 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 357 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 358 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 359 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 360 #define HWRM_ENGINE_SG_QUERY 0x147UL 361 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 362 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 363 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 364 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 365 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 366 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 367 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 368 #define HWRM_ENGINE_STATS_QUERY 0x157UL 369 #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR 0x158UL 370 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 371 #define HWRM_ENGINE_RQ_FREE 0x15fUL 372 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 373 #define HWRM_ENGINE_CQ_FREE 0x161UL 374 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 375 #define HWRM_ENGINE_NQ_FREE 0x163UL 376 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 377 #define HWRM_ENGINE_FUNC_QCFG 0x165UL 378 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 379 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 380 #define HWRM_FUNC_BACKING_STORE_QCAPS 0x192UL 381 #define HWRM_FUNC_BACKING_STORE_CFG 0x193UL 382 #define HWRM_FUNC_BACKING_STORE_QCFG 0x194UL 383 #define HWRM_FUNC_VF_BW_CFG 0x195UL 384 #define HWRM_FUNC_VF_BW_QCFG 0x196UL 385 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 386 #define HWRM_FUNC_QSTATS_EXT 0x198UL 387 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 388 #define HWRM_FUNC_SPD_CFG 0x19aUL 389 #define HWRM_FUNC_SPD_QCFG 0x19bUL 390 #define HWRM_FUNC_PTP_PIN_QCFG 0x19cUL 391 #define HWRM_FUNC_PTP_PIN_CFG 0x19dUL 392 #define HWRM_FUNC_PTP_CFG 0x19eUL 393 #define HWRM_FUNC_PTP_TS_QUERY 0x19fUL 394 #define HWRM_FUNC_PTP_EXT_CFG 0x1a0UL 395 #define HWRM_FUNC_PTP_EXT_QCFG 0x1a1UL 396 #define HWRM_FUNC_KEY_CTX_ALLOC 0x1a2UL 397 #define HWRM_FUNC_BACKING_STORE_CFG_V2 0x1a3UL 398 #define HWRM_FUNC_BACKING_STORE_QCFG_V2 0x1a4UL 399 #define HWRM_FUNC_DBR_PACING_CFG 0x1a5UL 400 #define HWRM_FUNC_DBR_PACING_QCFG 0x1a6UL 401 #define HWRM_FUNC_DBR_PACING_BROADCAST_EVENT 0x1a7UL 402 #define HWRM_FUNC_BACKING_STORE_QCAPS_V2 0x1a8UL 403 #define HWRM_FUNC_DBR_PACING_NQLIST_QUERY 0x1a9UL 404 #define HWRM_FUNC_DBR_RECOVERY_COMPLETED 0x1aaUL 405 #define HWRM_FUNC_SYNCE_CFG 0x1abUL 406 #define HWRM_FUNC_SYNCE_QCFG 0x1acUL 407 #define HWRM_FUNC_KEY_CTX_FREE 0x1adUL 408 #define HWRM_FUNC_LAG_MODE_CFG 0x1aeUL 409 #define HWRM_FUNC_LAG_MODE_QCFG 0x1afUL 410 #define HWRM_FUNC_LAG_CREATE 0x1b0UL 411 #define HWRM_FUNC_LAG_UPDATE 0x1b1UL 412 #define HWRM_FUNC_LAG_FREE 0x1b2UL 413 #define HWRM_FUNC_LAG_QCFG 0x1b3UL 414 #define HWRM_FUNC_TTX_PACING_RATE_PROF_QUERY 0x1c3UL 415 #define HWRM_FUNC_TTX_PACING_RATE_QUERY 0x1c4UL 416 #define HWRM_SELFTEST_QLIST 0x200UL 417 #define HWRM_SELFTEST_EXEC 0x201UL 418 #define HWRM_SELFTEST_IRQ 0x202UL 419 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 420 #define HWRM_PCIE_QSTATS 0x204UL 421 #define HWRM_MFG_FRU_WRITE_CONTROL 0x205UL 422 #define HWRM_MFG_TIMERS_QUERY 0x206UL 423 #define HWRM_MFG_OTP_CFG 0x207UL 424 #define HWRM_MFG_OTP_QCFG 0x208UL 425 #define HWRM_MFG_HDMA_TEST 0x209UL 426 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 427 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 428 #define HWRM_MFG_SOC_IMAGE 0x20cUL 429 #define HWRM_MFG_SOC_QSTATUS 0x20dUL 430 #define HWRM_MFG_PARAM_CRITICAL_DATA_FINALIZE 0x20eUL 431 #define HWRM_MFG_PARAM_CRITICAL_DATA_READ 0x20fUL 432 #define HWRM_MFG_PARAM_CRITICAL_DATA_HEALTH 0x210UL 433 #define HWRM_MFG_PRVSN_EXPORT_CSR 0x211UL 434 #define HWRM_MFG_PRVSN_IMPORT_CERT 0x212UL 435 #define HWRM_MFG_PRVSN_GET_STATE 0x213UL 436 #define HWRM_MFG_GET_NVM_MEASUREMENT 0x214UL 437 #define HWRM_MFG_PSOC_QSTATUS 0x215UL 438 #define HWRM_MFG_SELFTEST_QLIST 0x216UL 439 #define HWRM_MFG_SELFTEST_EXEC 0x217UL 440 #define HWRM_STAT_GENERIC_QSTATS 0x218UL 441 #define HWRM_MFG_PRVSN_EXPORT_CERT 0x219UL 442 #define HWRM_STAT_DB_ERROR_QSTATS 0x21aUL 443 #define HWRM_MFG_TESTS 0x21bUL 444 #define HWRM_MFG_WRITE_CERT_NVM 0x21cUL 445 #define HWRM_PORT_POE_CFG 0x230UL 446 #define HWRM_PORT_POE_QCFG 0x231UL 447 #define HWRM_PORT_PHY_FDRSTAT 0x232UL 448 #define HWRM_UDCC_QCAPS 0x258UL 449 #define HWRM_UDCC_CFG 0x259UL 450 #define HWRM_UDCC_QCFG 0x25aUL 451 #define HWRM_UDCC_SESSION_CFG 0x25bUL 452 #define HWRM_UDCC_SESSION_QCFG 0x25cUL 453 #define HWRM_UDCC_SESSION_QUERY 0x25dUL 454 #define HWRM_UDCC_COMP_CFG 0x25eUL 455 #define HWRM_UDCC_COMP_QCFG 0x25fUL 456 #define HWRM_UDCC_COMP_QUERY 0x260UL 457 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS 0x261UL 458 #define HWRM_QUEUE_PFCWD_TIMEOUT_CFG 0x262UL 459 #define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG 0x263UL 460 #define HWRM_QUEUE_ADPTV_QOS_RX_QCFG 0x264UL 461 #define HWRM_QUEUE_ADPTV_QOS_TX_QCFG 0x265UL 462 #define HWRM_TF 0x2bcUL 463 #define HWRM_TF_VERSION_GET 0x2bdUL 464 #define HWRM_TF_SESSION_OPEN 0x2c6UL 465 #define HWRM_TF_SESSION_REGISTER 0x2c8UL 466 #define HWRM_TF_SESSION_UNREGISTER 0x2c9UL 467 #define HWRM_TF_SESSION_CLOSE 0x2caUL 468 #define HWRM_TF_SESSION_QCFG 0x2cbUL 469 #define HWRM_TF_SESSION_RESC_QCAPS 0x2ccUL 470 #define HWRM_TF_SESSION_RESC_ALLOC 0x2cdUL 471 #define HWRM_TF_SESSION_RESC_FREE 0x2ceUL 472 #define HWRM_TF_SESSION_RESC_FLUSH 0x2cfUL 473 #define HWRM_TF_SESSION_RESC_INFO 0x2d0UL 474 #define HWRM_TF_SESSION_HOTUP_STATE_SET 0x2d1UL 475 #define HWRM_TF_SESSION_HOTUP_STATE_GET 0x2d2UL 476 #define HWRM_TF_TBL_TYPE_GET 0x2daUL 477 #define HWRM_TF_TBL_TYPE_SET 0x2dbUL 478 #define HWRM_TF_TBL_TYPE_BULK_GET 0x2dcUL 479 #define HWRM_TF_EM_INSERT 0x2eaUL 480 #define HWRM_TF_EM_DELETE 0x2ebUL 481 #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 482 #define HWRM_TF_EM_MOVE 0x2edUL 483 #define HWRM_TF_TCAM_SET 0x2f8UL 484 #define HWRM_TF_TCAM_GET 0x2f9UL 485 #define HWRM_TF_TCAM_MOVE 0x2faUL 486 #define HWRM_TF_TCAM_FREE 0x2fbUL 487 #define HWRM_TF_GLOBAL_CFG_SET 0x2fcUL 488 #define HWRM_TF_GLOBAL_CFG_GET 0x2fdUL 489 #define HWRM_TF_IF_TBL_SET 0x2feUL 490 #define HWRM_TF_IF_TBL_GET 0x2ffUL 491 #define HWRM_TF_RESC_USAGE_SET 0x300UL 492 #define HWRM_TF_RESC_USAGE_QUERY 0x301UL 493 #define HWRM_TF_TBL_TYPE_ALLOC 0x302UL 494 #define HWRM_TF_TBL_TYPE_FREE 0x303UL 495 #define HWRM_TFC_TBL_SCOPE_QCAPS 0x380UL 496 #define HWRM_TFC_TBL_SCOPE_ID_ALLOC 0x381UL 497 #define HWRM_TFC_TBL_SCOPE_CONFIG 0x382UL 498 #define HWRM_TFC_TBL_SCOPE_DECONFIG 0x383UL 499 #define HWRM_TFC_TBL_SCOPE_FID_ADD 0x384UL 500 #define HWRM_TFC_TBL_SCOPE_FID_REM 0x385UL 501 #define HWRM_TFC_TBL_SCOPE_POOL_ALLOC 0x386UL 502 #define HWRM_TFC_TBL_SCOPE_POOL_FREE 0x387UL 503 #define HWRM_TFC_SESSION_ID_ALLOC 0x388UL 504 #define HWRM_TFC_SESSION_FID_ADD 0x389UL 505 #define HWRM_TFC_SESSION_FID_REM 0x38aUL 506 #define HWRM_TFC_IDENT_ALLOC 0x38bUL 507 #define HWRM_TFC_IDENT_FREE 0x38cUL 508 #define HWRM_TFC_IDX_TBL_ALLOC 0x38dUL 509 #define HWRM_TFC_IDX_TBL_ALLOC_SET 0x38eUL 510 #define HWRM_TFC_IDX_TBL_SET 0x38fUL 511 #define HWRM_TFC_IDX_TBL_GET 0x390UL 512 #define HWRM_TFC_IDX_TBL_FREE 0x391UL 513 #define HWRM_TFC_GLOBAL_ID_ALLOC 0x392UL 514 #define HWRM_TFC_TCAM_SET 0x393UL 515 #define HWRM_TFC_TCAM_GET 0x394UL 516 #define HWRM_TFC_TCAM_ALLOC 0x395UL 517 #define HWRM_TFC_TCAM_ALLOC_SET 0x396UL 518 #define HWRM_TFC_TCAM_FREE 0x397UL 519 #define HWRM_TFC_IF_TBL_SET 0x398UL 520 #define HWRM_TFC_IF_TBL_GET 0x399UL 521 #define HWRM_TFC_TBL_SCOPE_CONFIG_GET 0x39aUL 522 #define HWRM_TFC_RESC_USAGE_QUERY 0x39bUL 523 #define HWRM_TFC_GLOBAL_ID_FREE 0x39cUL 524 #define HWRM_TFC_TCAM_PRI_UPDATE 0x39dUL 525 #define HWRM_TFC_HOT_UPGRADE_PROCESS 0x3a0UL 526 #define HWRM_SV 0x400UL 527 #define HWRM_DBG_SERDES_TEST 0xff0eUL 528 #define HWRM_DBG_LOG_BUFFER_FLUSH 0xff0fUL 529 #define HWRM_DBG_READ_DIRECT 0xff10UL 530 #define HWRM_DBG_READ_INDIRECT 0xff11UL 531 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 532 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 533 #define HWRM_DBG_DUMP 0xff14UL 534 #define HWRM_DBG_ERASE_NVM 0xff15UL 535 #define HWRM_DBG_CFG 0xff16UL 536 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 537 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 538 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 539 #define HWRM_DBG_FW_CLI 0xff1aUL 540 #define HWRM_DBG_I2C_CMD 0xff1bUL 541 #define HWRM_DBG_RING_INFO_GET 0xff1cUL 542 #define HWRM_DBG_CRASHDUMP_HEADER 0xff1dUL 543 #define HWRM_DBG_CRASHDUMP_ERASE 0xff1eUL 544 #define HWRM_DBG_DRV_TRACE 0xff1fUL 545 #define HWRM_DBG_QCAPS 0xff20UL 546 #define HWRM_DBG_QCFG 0xff21UL 547 #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG 0xff22UL 548 #define HWRM_DBG_USEQ_ALLOC 0xff23UL 549 #define HWRM_DBG_USEQ_FREE 0xff24UL 550 #define HWRM_DBG_USEQ_FLUSH 0xff25UL 551 #define HWRM_DBG_USEQ_QCAPS 0xff26UL 552 #define HWRM_DBG_USEQ_CW_CFG 0xff27UL 553 #define HWRM_DBG_USEQ_SCHED_CFG 0xff28UL 554 #define HWRM_DBG_USEQ_RUN 0xff29UL 555 #define HWRM_DBG_USEQ_DELIVERY_REQ 0xff2aUL 556 #define HWRM_DBG_USEQ_RESP_HDR 0xff2bUL 557 #define HWRM_DBG_COREDUMP_CAPTURE 0xff2cUL 558 #define HWRM_DBG_PTRACE 0xff2dUL 559 #define HWRM_DBG_SIM_CABLE_STATE 0xff2eUL 560 #define HWRM_DBG_TOKEN_QUERY_AUTH_IDS 0xff2fUL 561 #define HWRM_DBG_TOKEN_CFG 0xff30UL 562 #define HWRM_NVM_GET_VPD_FIELD_INFO 0xffeaUL 563 #define HWRM_NVM_SET_VPD_FIELD_INFO 0xffebUL 564 #define HWRM_NVM_DEFRAG 0xffecUL 565 #define HWRM_NVM_REQ_ARBITRATION 0xffedUL 566 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 567 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 568 #define HWRM_NVM_FLUSH 0xfff0UL 569 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 570 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 571 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 572 #define HWRM_NVM_MODIFY 0xfff4UL 573 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 574 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 575 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 576 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 577 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 578 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 579 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 580 #define HWRM_NVM_RAW_DUMP 0xfffcUL 581 #define HWRM_NVM_READ 0xfffdUL 582 #define HWRM_NVM_WRITE 0xfffeUL 583 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 584 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 585 __le16 unused_0[3]; 586}; 587 588/* ret_codes (size:64b/8B) */ 589struct ret_codes { 590 __le16 error_code; 591 #define HWRM_ERR_CODE_SUCCESS 0x0UL 592 #define HWRM_ERR_CODE_FAIL 0x1UL 593 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 594 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 595 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 596 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 597 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 598 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 599 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 600 #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR 0x9UL 601 #define HWRM_ERR_CODE_HOT_RESET_PROGRESS 0xaUL 602 #define HWRM_ERR_CODE_HOT_RESET_FAIL 0xbUL 603 #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL 604 #define HWRM_ERR_CODE_KEY_HASH_COLLISION 0xdUL 605 #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS 0xeUL 606 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 607 #define HWRM_ERR_CODE_BUSY 0x10UL 608 #define HWRM_ERR_CODE_RESOURCE_LOCKED 0x11UL 609 #define HWRM_ERR_CODE_PF_UNAVAILABLE 0x12UL 610 #define HWRM_ERR_CODE_ENTITY_NOT_PRESENT 0x13UL 611 #define HWRM_ERR_CODE_SECURE_SOC_ERROR 0x14UL 612 #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE 0x8000UL 613 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 614 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 615 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 616 __le16 unused_0[3]; 617}; 618 619/* hwrm_err_output (size:128b/16B) */ 620struct hwrm_err_output { 621 __le16 error_code; 622 __le16 req_type; 623 __le16 seq_id; 624 __le16 resp_len; 625 __le32 opaque_0; 626 __le16 opaque_1; 627 u8 cmd_err; 628 u8 valid; 629}; 630#define HWRM_NA_SIGNATURE ((__le32)(-1)) 631#define HWRM_MAX_REQ_LEN 128 632#define HWRM_MAX_RESP_LEN 704 633#define HW_HASH_INDEX_SIZE 0x80 634#define HW_HASH_KEY_SIZE 40 635#define HWRM_RESP_VALID_KEY 1 636#define HWRM_TARGET_ID_BONO 0xFFF8 637#define HWRM_TARGET_ID_KONG 0xFFF9 638#define HWRM_TARGET_ID_APE 0xFFFA 639#define HWRM_TARGET_ID_TOOLS 0xFFFD 640#define HWRM_VERSION_MAJOR 1 641#define HWRM_VERSION_MINOR 10 642#define HWRM_VERSION_UPDATE 3 643#define HWRM_VERSION_RSVD 133 644#define HWRM_VERSION_STR "1.10.3.133" 645 646/* hwrm_ver_get_input (size:192b/24B) */ 647struct hwrm_ver_get_input { 648 __le16 req_type; 649 __le16 cmpl_ring; 650 __le16 seq_id; 651 __le16 target_id; 652 __le64 resp_addr; 653 u8 hwrm_intf_maj; 654 u8 hwrm_intf_min; 655 u8 hwrm_intf_upd; 656 u8 unused_0[5]; 657}; 658 659/* hwrm_ver_get_output (size:1408b/176B) */ 660struct hwrm_ver_get_output { 661 __le16 error_code; 662 __le16 req_type; 663 __le16 seq_id; 664 __le16 resp_len; 665 u8 hwrm_intf_maj_8b; 666 u8 hwrm_intf_min_8b; 667 u8 hwrm_intf_upd_8b; 668 u8 hwrm_intf_rsvd_8b; 669 u8 hwrm_fw_maj_8b; 670 u8 hwrm_fw_min_8b; 671 u8 hwrm_fw_bld_8b; 672 u8 hwrm_fw_rsvd_8b; 673 u8 mgmt_fw_maj_8b; 674 u8 mgmt_fw_min_8b; 675 u8 mgmt_fw_bld_8b; 676 u8 mgmt_fw_rsvd_8b; 677 u8 netctrl_fw_maj_8b; 678 u8 netctrl_fw_min_8b; 679 u8 netctrl_fw_bld_8b; 680 u8 netctrl_fw_rsvd_8b; 681 __le32 dev_caps_cfg; 682 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 683 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 684 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 685 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 686 #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED 0x10UL 687 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED 0x20UL 688 #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED 0x40UL 689 #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED 0x80UL 690 #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED 0x100UL 691 #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED 0x200UL 692 #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED 0x400UL 693 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED 0x800UL 694 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED 0x1000UL 695 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED 0x2000UL 696 #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED 0x4000UL 697 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE 0x8000UL 698 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE 0x10000UL 699 #define VER_GET_RESP_DEV_CAPS_CFG_DEBUG_TOKEN_SUPPORTED 0x20000UL 700 u8 roce_fw_maj_8b; 701 u8 roce_fw_min_8b; 702 u8 roce_fw_bld_8b; 703 u8 roce_fw_rsvd_8b; 704 char hwrm_fw_name[16]; 705 char mgmt_fw_name[16]; 706 char netctrl_fw_name[16]; 707 char active_pkg_name[16]; 708 char roce_fw_name[16]; 709 __le16 chip_num; 710 u8 chip_rev; 711 u8 chip_metal; 712 u8 chip_bond_id; 713 u8 chip_platform_type; 714 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 715 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 716 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 717 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 718 __le16 max_req_win_len; 719 __le16 max_resp_len; 720 __le16 def_req_timeout; 721 u8 flags; 722 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 723 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 724 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 725 u8 unused_0[2]; 726 u8 always_1; 727 __le16 hwrm_intf_major; 728 __le16 hwrm_intf_minor; 729 __le16 hwrm_intf_build; 730 __le16 hwrm_intf_patch; 731 __le16 hwrm_fw_major; 732 __le16 hwrm_fw_minor; 733 __le16 hwrm_fw_build; 734 __le16 hwrm_fw_patch; 735 __le16 mgmt_fw_major; 736 __le16 mgmt_fw_minor; 737 __le16 mgmt_fw_build; 738 __le16 mgmt_fw_patch; 739 __le16 netctrl_fw_major; 740 __le16 netctrl_fw_minor; 741 __le16 netctrl_fw_build; 742 __le16 netctrl_fw_patch; 743 __le16 roce_fw_major; 744 __le16 roce_fw_minor; 745 __le16 roce_fw_build; 746 __le16 roce_fw_patch; 747 __le16 max_ext_req_len; 748 __le16 max_req_timeout; 749 u8 unused_1[3]; 750 u8 valid; 751}; 752 753/* eject_cmpl (size:128b/16B) */ 754struct eject_cmpl { 755 __le16 type; 756 #define EJECT_CMPL_TYPE_MASK 0x3fUL 757 #define EJECT_CMPL_TYPE_SFT 0 758 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 759 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 760 #define EJECT_CMPL_FLAGS_MASK 0xffc0UL 761 #define EJECT_CMPL_FLAGS_SFT 6 762 #define EJECT_CMPL_FLAGS_ERROR 0x40UL 763 __le16 len; 764 __le32 opaque; 765 __le16 v; 766 #define EJECT_CMPL_V 0x1UL 767 #define EJECT_CMPL_ERRORS_MASK 0xfffeUL 768 #define EJECT_CMPL_ERRORS_SFT 1 769 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK 0xeUL 770 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1 771 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0UL << 1) 772 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1UL << 1) 773 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3UL << 1) 774 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH (0x5UL << 1) 775 #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH 776 __le16 reserved16; 777 __le32 unused_2; 778}; 779 780/* hwrm_cmpl (size:128b/16B) */ 781struct hwrm_cmpl { 782 __le16 type; 783 #define CMPL_TYPE_MASK 0x3fUL 784 #define CMPL_TYPE_SFT 0 785 #define CMPL_TYPE_HWRM_DONE 0x20UL 786 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 787 __le16 sequence_id; 788 __le32 unused_1; 789 __le32 v; 790 #define CMPL_V 0x1UL 791 __le32 unused_3; 792}; 793 794/* hwrm_fwd_req_cmpl (size:128b/16B) */ 795struct hwrm_fwd_req_cmpl { 796 __le16 req_len_type; 797 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 798 #define FWD_REQ_CMPL_TYPE_SFT 0 799 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 800 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 801 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 802 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 803 __le16 source_id; 804 __le32 unused0; 805 __le32 req_buf_addr_v[2]; 806 #define FWD_REQ_CMPL_V 0x1UL 807 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 808 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 809}; 810 811/* hwrm_fwd_resp_cmpl (size:128b/16B) */ 812struct hwrm_fwd_resp_cmpl { 813 __le16 type; 814 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 815 #define FWD_RESP_CMPL_TYPE_SFT 0 816 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 817 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 818 __le16 source_id; 819 __le16 resp_len; 820 __le16 unused_1; 821 __le32 resp_buf_addr_v[2]; 822 #define FWD_RESP_CMPL_V 0x1UL 823 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 824 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 825}; 826 827/* hwrm_async_event_cmpl (size:128b/16B) */ 828struct hwrm_async_event_cmpl { 829 __le16 type; 830 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 831 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 832 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 833 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 834 __le16 event_id; 835 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 836 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 837 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 838 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 839 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 840 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 841 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 842 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 843 #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY 0x8UL 844 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY 0x9UL 845 #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG 0xaUL 846 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 847 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 848 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 849 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 850 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 851 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 852 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 853 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 854 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 855 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 856 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE 0x35UL 857 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED 0x36UL 858 #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION 0x37UL 859 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 860 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 861 #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE 0x3aUL 862 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE 0x3bUL 863 #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE 0x3cUL 864 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE 0x3dUL 865 #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE 0x3eUL 866 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 867 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 868 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 869 #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST 0x42UL 870 #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_UPDATE 0x43UL 871 #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP 0x44UL 872 #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT 0x45UL 873 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_THRESHOLD 0x46UL 874 #define ASYNC_EVENT_CMPL_EVENT_ID_RSS_CHANGE 0x47UL 875 #define ASYNC_EVENT_CMPL_EVENT_ID_DOORBELL_PACING_NQ_UPDATE 0x48UL 876 #define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL 877 #define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR 0x4aUL 878 #define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE 0x4bUL 879 #define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 880 #define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE 0x4dUL 881 #define ASYNC_EVENT_CMPL_EVENT_ID_REPRESENTOR_PAIR_CHANGE 0x4eUL 882 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_STAT_CHANGE 0x4fUL 883 #define ASYNC_EVENT_CMPL_EVENT_ID_HOST_COREDUMP 0x50UL 884 #define ASYNC_EVENT_CMPL_EVENT_ID_ADPTV_QOS 0x51UL 885 #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x52UL 886 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 887 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 888 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 889 __le32 event_data2; 890 u8 opaque_v; 891 #define ASYNC_EVENT_CMPL_V 0x1UL 892 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 893 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 894 u8 timestamp_lo; 895 __le16 timestamp_hi; 896 __le32 event_data1; 897}; 898 899/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 900struct hwrm_async_event_cmpl_link_status_change { 901 __le16 type; 902 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 903 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 904 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 905 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 906 __le16 event_id; 907 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 908 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 909 __le32 event_data2; 910 u8 opaque_v; 911 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 912 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 913 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 914 u8 timestamp_lo; 915 __le16 timestamp_hi; 916 __le32 event_data1; 917 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 918 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 919 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 920 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 921 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 922 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 923 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 924 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 925 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK 0xff00000UL 926 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT 20 927}; 928 929/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 930struct hwrm_async_event_cmpl_port_conn_not_allowed { 931 __le16 type; 932 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 933 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 934 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 935 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 936 __le16 event_id; 937 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 938 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 939 __le32 event_data2; 940 u8 opaque_v; 941 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 942 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 943 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 944 u8 timestamp_lo; 945 __le16 timestamp_hi; 946 __le32 event_data1; 947 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 948 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 949 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 950 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 951 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 952 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 953 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 954 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 955 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 956}; 957 958/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 959struct hwrm_async_event_cmpl_link_speed_cfg_change { 960 __le16 type; 961 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 962 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 963 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 964 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 965 __le16 event_id; 966 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 967 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 968 __le32 event_data2; 969 u8 opaque_v; 970 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 971 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 972 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 973 u8 timestamp_lo; 974 __le16 timestamp_hi; 975 __le32 event_data1; 976 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 977 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 978 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 979 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 980}; 981 982/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */ 983struct hwrm_async_event_cmpl_reset_notify { 984 __le16 type; 985 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK 0x3fUL 986 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT 0 987 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 988 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT 989 __le16 event_id; 990 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 991 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 992 __le32 event_data2; 993 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 994 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 995 u8 opaque_v; 996 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 997 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL 998 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1 999 u8 timestamp_lo; 1000 __le16 timestamp_hi; 1001 __le32 event_data1; 1002 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK 0xffUL 1003 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT 0 1004 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE 0x1UL 1005 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 0x2UL 1006 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN 1007 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK 0xff00UL 1008 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT 8 1009 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 1010 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 1011 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 1012 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 1013 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION (0x5UL << 8) 1014 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION 1015 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 1016 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 1017}; 1018 1019/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */ 1020struct hwrm_async_event_cmpl_error_recovery { 1021 __le16 type; 1022 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK 0x3fUL 1023 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0 1024 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1025 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT 1026 __le16 event_id; 1027 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL 1028 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 1029 __le32 event_data2; 1030 u8 opaque_v; 1031 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V 0x1UL 1032 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL 1033 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1 1034 u8 timestamp_lo; 1035 __le16 timestamp_hi; 1036 __le32 event_data1; 1037 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK 0xffUL 1038 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT 0 1039 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC 0x1UL 1040 #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED 0x2UL 1041}; 1042 1043/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */ 1044struct hwrm_async_event_cmpl_ring_monitor_msg { 1045 __le16 type; 1046 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK 0x3fUL 1047 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT 0 1048 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1049 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT 1050 __le16 event_id; 1051 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL 1052 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 1053 __le32 event_data2; 1054 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL 1055 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0 1056 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX 0x0UL 1057 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX 0x1UL 1058 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 0x2UL 1059 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL 1060 u8 opaque_v; 1061 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V 0x1UL 1062 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL 1063 #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1 1064 u8 timestamp_lo; 1065 __le16 timestamp_hi; 1066 __le32 event_data1; 1067}; 1068 1069/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 1070struct hwrm_async_event_cmpl_vf_cfg_change { 1071 __le16 type; 1072 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 1073 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 1074 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1075 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 1076 __le16 event_id; 1077 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 1078 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 1079 __le32 event_data2; 1080 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL 1081 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0 1082 u8 opaque_v; 1083 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 1084 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 1085 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 1086 u8 timestamp_lo; 1087 __le16 timestamp_hi; 1088 __le32 event_data1; 1089 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 1090 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 1091 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 1092 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 1093 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE 0x10UL 1094 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TF_OWNERSHIP_RELEASE 0x20UL 1095}; 1096 1097/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */ 1098struct hwrm_async_event_cmpl_default_vnic_change { 1099 __le16 type; 1100 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK 0x3fUL 1101 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT 0 1102 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1103 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT 1104 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK 0xffc0UL 1105 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT 6 1106 __le16 event_id; 1107 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL 1108 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 1109 __le32 event_data2; 1110 u8 opaque_v; 1111 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V 0x1UL 1112 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL 1113 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1 1114 u8 timestamp_lo; 1115 __le16 timestamp_hi; 1116 __le32 event_data1; 1117 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK 0x3UL 1118 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT 0 1119 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC 0x1UL 1120 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 0x2UL 1121 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE 1122 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK 0x3fcUL 1123 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT 2 1124 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK 0x3fffc00UL 1125 #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT 10 1126}; 1127 1128/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */ 1129struct hwrm_async_event_cmpl_hw_flow_aged { 1130 __le16 type; 1131 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK 0x3fUL 1132 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0 1133 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1134 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT 1135 __le16 event_id; 1136 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL 1137 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 1138 __le32 event_data2; 1139 u8 opaque_v; 1140 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V 0x1UL 1141 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL 1142 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1 1143 u8 timestamp_lo; 1144 __le16 timestamp_hi; 1145 __le32 event_data1; 1146 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK 0x7fffffffUL 1147 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT 0 1148 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION 0x80000000UL 1149 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX (0x0UL << 31) 1150 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX (0x1UL << 31) 1151 #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX 1152}; 1153 1154/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */ 1155struct hwrm_async_event_cmpl_eem_cache_flush_req { 1156 __le16 type; 1157 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK 0x3fUL 1158 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT 0 1159 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1160 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT 1161 __le16 event_id; 1162 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL 1163 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 1164 __le32 event_data2; 1165 u8 opaque_v; 1166 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V 0x1UL 1167 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL 1168 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1 1169 u8 timestamp_lo; 1170 __le16 timestamp_hi; 1171 __le32 event_data1; 1172}; 1173 1174/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */ 1175struct hwrm_async_event_cmpl_eem_cache_flush_done { 1176 __le16 type; 1177 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK 0x3fUL 1178 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT 0 1179 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1180 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT 1181 __le16 event_id; 1182 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL 1183 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 1184 __le32 event_data2; 1185 u8 opaque_v; 1186 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V 0x1UL 1187 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL 1188 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1 1189 u8 timestamp_lo; 1190 __le16 timestamp_hi; 1191 __le32 event_data1; 1192 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL 1193 #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0 1194}; 1195 1196/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */ 1197struct hwrm_async_event_cmpl_deferred_response { 1198 __le16 type; 1199 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK 0x3fUL 1200 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT 0 1201 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1202 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT 1203 __le16 event_id; 1204 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL 1205 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 1206 __le32 event_data2; 1207 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL 1208 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0 1209 u8 opaque_v; 1210 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V 0x1UL 1211 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL 1212 #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1 1213 u8 timestamp_lo; 1214 __le16 timestamp_hi; 1215 __le32 event_data1; 1216}; 1217 1218/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */ 1219struct hwrm_async_event_cmpl_echo_request { 1220 __le16 type; 1221 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK 0x3fUL 1222 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT 0 1223 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1224 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT 1225 __le16 event_id; 1226 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL 1227 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 1228 __le32 event_data2; 1229 u8 opaque_v; 1230 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V 0x1UL 1231 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL 1232 #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1 1233 u8 timestamp_lo; 1234 __le16 timestamp_hi; 1235 __le32 event_data1; 1236}; 1237 1238/* hwrm_async_event_cmpl_phc_update (size:128b/16B) */ 1239struct hwrm_async_event_cmpl_phc_update { 1240 __le16 type; 1241 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_MASK 0x3fUL 1242 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_SFT 0 1243 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1244 #define ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_TYPE_HWRM_ASYNC_EVENT 1245 __le16 event_id; 1246 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 0x43UL 1247 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_ID_PHC_UPDATE 1248 __le32 event_data2; 1249 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL 1250 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_MASTER_FID_SFT 0 1251 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_MASK 0xffff0000UL 1252 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA2_PHC_SEC_FID_SFT 16 1253 u8 opaque_v; 1254 #define ASYNC_EVENT_CMPL_PHC_UPDATE_V 0x1UL 1255 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_MASK 0xfeUL 1256 #define ASYNC_EVENT_CMPL_PHC_UPDATE_OPAQUE_SFT 1 1257 u8 timestamp_lo; 1258 __le16 timestamp_hi; 1259 __le32 event_data1; 1260 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_MASK 0xfUL 1261 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_SFT 0 1262 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_MASTER 0x1UL 1263 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_SECONDARY 0x2UL 1264 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_FAILOVER 0x3UL 1265 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 0x4UL 1266 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_LAST ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_FLAGS_PHC_RTC_UPDATE 1267 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_MASK 0xffff0UL 1268 #define ASYNC_EVENT_CMPL_PHC_UPDATE_EVENT_DATA1_PHC_TIME_MSB_SFT 4 1269}; 1270 1271/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */ 1272struct hwrm_async_event_cmpl_pps_timestamp { 1273 __le16 type; 1274 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK 0x3fUL 1275 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT 0 1276 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1277 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT 1278 __le16 event_id; 1279 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL 1280 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 1281 __le32 event_data2; 1282 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE 0x1UL 1283 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL 0x0UL 1284 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 0x1UL 1285 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL 1286 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK 0xeUL 1287 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT 1 1288 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL 1289 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4 1290 u8 opaque_v; 1291 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V 0x1UL 1292 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL 1293 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1 1294 u8 timestamp_lo; 1295 __le16 timestamp_hi; 1296 __le32 event_data1; 1297 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL 1298 #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0 1299}; 1300 1301/* hwrm_async_event_cmpl_error_report (size:128b/16B) */ 1302struct hwrm_async_event_cmpl_error_report { 1303 __le16 type; 1304 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK 0x3fUL 1305 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT 0 1306 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1307 #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT 1308 __le16 event_id; 1309 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL 1310 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 1311 __le32 event_data2; 1312 u8 opaque_v; 1313 #define ASYNC_EVENT_CMPL_ERROR_REPORT_V 0x1UL 1314 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL 1315 #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1 1316 u8 timestamp_lo; 1317 __le16 timestamp_hi; 1318 __le32 event_data1; 1319 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1320 #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0 1321}; 1322 1323/* hwrm_async_event_cmpl_dbg_buf_producer (size:128b/16B) */ 1324struct hwrm_async_event_cmpl_dbg_buf_producer { 1325 __le16 type; 1326 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_MASK 0x3fUL 1327 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_SFT 0 1328 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1329 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_TYPE_HWRM_ASYNC_EVENT 1330 __le16 event_id; 1331 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 0x4cUL 1332 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_ID_DBG_BUF_PRODUCER 1333 __le32 event_data2; 1334 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_MASK 0xffffffffUL 1335 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA2_CURR_OFF_SFT 0 1336 u8 opaque_v; 1337 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_V 0x1UL 1338 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_MASK 0xfeUL 1339 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_OPAQUE_SFT 1 1340 u8 timestamp_lo; 1341 __le16 timestamp_hi; 1342 __le32 event_data1; 1343 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_MASK 0xffffUL 1344 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SFT 0 1345 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT_TRACE 0x0UL 1346 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_SRT2_TRACE 0x1UL 1347 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT_TRACE 0x2UL 1348 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CRT2_TRACE 0x3UL 1349 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP0_TRACE 0x4UL 1350 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_L2_HWRM_TRACE 0x5UL 1351 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ROCE_HWRM_TRACE 0x6UL 1352 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA0_TRACE 0x7UL 1353 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA1_TRACE 0x8UL 1354 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_CA2_TRACE 0x9UL 1355 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_RIGP1_TRACE 0xaUL 1356 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 1357 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 0xcUL 1358 #define ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_LAST ASYNC_EVENT_CMPL_DBG_BUF_PRODUCER_EVENT_DATA1_TYPE_ERR_QPC_TRACE 1359}; 1360 1361/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */ 1362struct hwrm_async_event_cmpl_hwrm_error { 1363 __le16 type; 1364 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK 0x3fUL 1365 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0 1366 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1367 #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT 1368 __le16 event_id; 1369 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL 1370 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 1371 __le32 event_data2; 1372 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK 0xffUL 1373 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0 1374 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING 0x0UL 1375 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL 0x1UL 1376 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 0x2UL 1377 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL 1378 u8 opaque_v; 1379 #define ASYNC_EVENT_CMPL_HWRM_ERROR_V 0x1UL 1380 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL 1381 #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1 1382 u8 timestamp_lo; 1383 __le16 timestamp_hi; 1384 __le32 event_data1; 1385 #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP 0x1UL 1386}; 1387 1388/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */ 1389struct hwrm_async_event_cmpl_error_report_base { 1390 __le16 type; 1391 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK 0x3fUL 1392 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT 0 1393 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1394 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT 1395 __le16 event_id; 1396 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL 1397 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 1398 __le32 event_data2; 1399 u8 opaque_v; 1400 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V 0x1UL 1401 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL 1402 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1 1403 u8 timestamp_lo; 1404 __le16 timestamp_hi; 1405 __le32 event_data1; 1406 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1407 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT 0 1408 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED 0x0UL 1409 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1410 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1411 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM 0x3UL 1412 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1413 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_THERMAL_THRESHOLD 0x5UL 1414 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1415 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DUP_UDCC_SES 0x7UL 1416 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DB_DROP 0x8UL 1417 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MD_TEMP 0x9UL 1418 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 0xaUL 1419 #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_VNIC_ERR 1420}; 1421 1422/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */ 1423struct hwrm_async_event_cmpl_error_report_pause_storm { 1424 __le16 type; 1425 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK 0x3fUL 1426 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT 0 1427 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1428 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT 1429 __le16 event_id; 1430 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL 1431 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 1432 __le32 event_data2; 1433 u8 opaque_v; 1434 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V 0x1UL 1435 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL 1436 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1 1437 u8 timestamp_lo; 1438 __le16 timestamp_hi; 1439 __le32 event_data1; 1440 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1441 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT 0 1442 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 0x1UL 1443 #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM 1444}; 1445 1446/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */ 1447struct hwrm_async_event_cmpl_error_report_invalid_signal { 1448 __le16 type; 1449 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK 0x3fUL 1450 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT 0 1451 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1452 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT 1453 __le16 event_id; 1454 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL 1455 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 1456 __le32 event_data2; 1457 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL 1458 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0 1459 u8 opaque_v; 1460 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V 0x1UL 1461 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL 1462 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1 1463 u8 timestamp_lo; 1464 __le16 timestamp_hi; 1465 __le32 event_data1; 1466 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1467 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1468 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 0x2UL 1469 #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL 1470}; 1471 1472/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */ 1473struct hwrm_async_event_cmpl_error_report_nvm { 1474 __le16 type; 1475 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK 0x3fUL 1476 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT 0 1477 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1478 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT 1479 __le16 event_id; 1480 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL 1481 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 1482 __le32 event_data2; 1483 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL 1484 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0 1485 u8 opaque_v; 1486 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V 0x1UL 1487 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL 1488 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1 1489 u8 timestamp_lo; 1490 __le16 timestamp_hi; 1491 __le32 event_data1; 1492 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1493 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT 0 1494 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 0x3UL 1495 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR 1496 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK 0xff00UL 1497 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT 8 1498 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE (0x1UL << 8) 1499 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE (0x2UL << 8) 1500 #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE 1501}; 1502 1503/* hwrm_async_event_cmpl_error_report_doorbell_drop_threshold (size:128b/16B) */ 1504struct hwrm_async_event_cmpl_error_report_doorbell_drop_threshold { 1505 __le16 type; 1506 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_MASK 0x3fUL 1507 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_SFT 0 1508 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1509 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_TYPE_HWRM_ASYNC_EVENT 1510 __le16 event_id; 1511 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 0x45UL 1512 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_ID_ERROR_REPORT 1513 __le32 event_data2; 1514 u8 opaque_v; 1515 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_V 0x1UL 1516 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_MASK 0xfeUL 1517 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_OPAQUE_SFT 1 1518 u8 timestamp_lo; 1519 __le16 timestamp_hi; 1520 __le32 event_data1; 1521 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1522 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_SFT 0 1523 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 0x4UL 1524 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD 1525 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK 0xffffff00UL 1526 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT 8 1527}; 1528 1529/* hwrm_async_event_cmpl_error_report_thermal (size:128b/16B) */ 1530struct hwrm_async_event_cmpl_error_report_thermal { 1531 __le16 type; 1532 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_MASK 0x3fUL 1533 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_SFT 0 1534 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1535 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_TYPE_HWRM_ASYNC_EVENT 1536 __le16 event_id; 1537 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 0x45UL 1538 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_ID_ERROR_REPORT 1539 __le32 event_data2; 1540 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK 0xffUL 1541 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_SFT 0 1542 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK 0xff00UL 1543 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT 8 1544 u8 opaque_v; 1545 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_V 0x1UL 1546 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_MASK 0xfeUL 1547 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_OPAQUE_SFT 1 1548 u8 timestamp_lo; 1549 __le16 timestamp_hi; 1550 __le32 event_data1; 1551 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1552 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_SFT 0 1553 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 0x5UL 1554 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_ERROR_TYPE_THERMAL_EVENT 1555 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK 0x700UL 1556 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SFT 8 1557 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_WARN (0x0UL << 8) 1558 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_CRITICAL (0x1UL << 8) 1559 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_FATAL (0x2UL << 8) 1560 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN (0x3UL << 8) 1561 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_SHUTDOWN 1562 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR 0x800UL 1563 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_DECREASING (0x0UL << 11) 1564 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING (0x1UL << 11) 1565 #define ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING 1566}; 1567 1568/* hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported (size:128b/16B) */ 1569struct hwrm_async_event_cmpl_error_report_dual_data_rate_not_supported { 1570 __le16 type; 1571 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_MASK 0x3fUL 1572 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_SFT 0 1573 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 1574 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_TYPE_HWRM_ASYNC_EVENT 1575 __le16 event_id; 1576 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 0x45UL 1577 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_ID_ERROR_REPORT 1578 __le32 event_data2; 1579 u8 opaque_v; 1580 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_V 0x1UL 1581 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_MASK 0xfeUL 1582 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_OPAQUE_SFT 1 1583 u8 timestamp_lo; 1584 __le16 timestamp_hi; 1585 __le32 event_data1; 1586 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL 1587 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_SFT 0 1588 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 0x6UL 1589 #define ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_LAST ASYNC_EVENT_CMPL_ERROR_REPORT_DUAL_DATA_RATE_NOT_SUPPORTED_EVENT_DATA1_ERROR_TYPE_DUAL_DATA_RATE_NOT_SUPPORTED 1590}; 1591 1592/* hwrm_func_reset_input (size:192b/24B) */ 1593struct hwrm_func_reset_input { 1594 __le16 req_type; 1595 __le16 cmpl_ring; 1596 __le16 seq_id; 1597 __le16 target_id; 1598 __le64 resp_addr; 1599 __le32 enables; 1600 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 1601 __le16 vf_id; 1602 u8 func_reset_level; 1603 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 1604 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 1605 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 1606 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 1607 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 1608 u8 unused_0; 1609}; 1610 1611/* hwrm_func_reset_output (size:128b/16B) */ 1612struct hwrm_func_reset_output { 1613 __le16 error_code; 1614 __le16 req_type; 1615 __le16 seq_id; 1616 __le16 resp_len; 1617 u8 unused_0[7]; 1618 u8 valid; 1619}; 1620 1621/* hwrm_func_getfid_input (size:192b/24B) */ 1622struct hwrm_func_getfid_input { 1623 __le16 req_type; 1624 __le16 cmpl_ring; 1625 __le16 seq_id; 1626 __le16 target_id; 1627 __le64 resp_addr; 1628 __le32 enables; 1629 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 1630 __le16 pci_id; 1631 u8 unused_0[2]; 1632}; 1633 1634/* hwrm_func_getfid_output (size:128b/16B) */ 1635struct hwrm_func_getfid_output { 1636 __le16 error_code; 1637 __le16 req_type; 1638 __le16 seq_id; 1639 __le16 resp_len; 1640 __le16 fid; 1641 u8 unused_0[5]; 1642 u8 valid; 1643}; 1644 1645/* hwrm_func_vf_alloc_input (size:192b/24B) */ 1646struct hwrm_func_vf_alloc_input { 1647 __le16 req_type; 1648 __le16 cmpl_ring; 1649 __le16 seq_id; 1650 __le16 target_id; 1651 __le64 resp_addr; 1652 __le32 enables; 1653 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 1654 __le16 first_vf_id; 1655 __le16 num_vfs; 1656}; 1657 1658/* hwrm_func_vf_alloc_output (size:128b/16B) */ 1659struct hwrm_func_vf_alloc_output { 1660 __le16 error_code; 1661 __le16 req_type; 1662 __le16 seq_id; 1663 __le16 resp_len; 1664 __le16 first_vf_id; 1665 u8 unused_0[5]; 1666 u8 valid; 1667}; 1668 1669/* hwrm_func_vf_free_input (size:192b/24B) */ 1670struct hwrm_func_vf_free_input { 1671 __le16 req_type; 1672 __le16 cmpl_ring; 1673 __le16 seq_id; 1674 __le16 target_id; 1675 __le64 resp_addr; 1676 __le32 enables; 1677 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 1678 __le16 first_vf_id; 1679 __le16 num_vfs; 1680}; 1681 1682/* hwrm_func_vf_free_output (size:128b/16B) */ 1683struct hwrm_func_vf_free_output { 1684 __le16 error_code; 1685 __le16 req_type; 1686 __le16 seq_id; 1687 __le16 resp_len; 1688 u8 unused_0[7]; 1689 u8 valid; 1690}; 1691 1692/* hwrm_func_vf_cfg_input (size:576b/72B) */ 1693struct hwrm_func_vf_cfg_input { 1694 __le16 req_type; 1695 __le16 cmpl_ring; 1696 __le16 seq_id; 1697 __le16 target_id; 1698 __le64 resp_addr; 1699 __le32 enables; 1700 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 1701 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 1702 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 1703 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 1704 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 1705 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 1706 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 1707 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 1708 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 1709 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 1710 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 1711 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 1712 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_TX_KEY_CTXS 0x1000UL 1713 #define FUNC_VF_CFG_REQ_ENABLES_NUM_KTLS_RX_KEY_CTXS 0x2000UL 1714 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_TX_KEY_CTXS 0x4000UL 1715 #define FUNC_VF_CFG_REQ_ENABLES_NUM_QUIC_RX_KEY_CTXS 0x8000UL 1716 __le16 mtu; 1717 __le16 guest_vlan; 1718 __le16 async_event_cr; 1719 u8 dflt_mac_addr[6]; 1720 __le32 flags; 1721 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 1722 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 1723 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 1724 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 1725 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 1726 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 1727 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 1728 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 1729 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x100UL 1730 #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x200UL 1731 __le16 num_rsscos_ctxs; 1732 __le16 num_cmpl_rings; 1733 __le16 num_tx_rings; 1734 __le16 num_rx_rings; 1735 __le16 num_l2_ctxs; 1736 __le16 num_vnics; 1737 __le16 num_stat_ctxs; 1738 __le16 num_hw_ring_grps; 1739 __le32 num_ktls_tx_key_ctxs; 1740 __le32 num_ktls_rx_key_ctxs; 1741 __le16 num_msix; 1742 u8 unused[2]; 1743 __le32 num_quic_tx_key_ctxs; 1744 __le32 num_quic_rx_key_ctxs; 1745}; 1746 1747/* hwrm_func_vf_cfg_output (size:128b/16B) */ 1748struct hwrm_func_vf_cfg_output { 1749 __le16 error_code; 1750 __le16 req_type; 1751 __le16 seq_id; 1752 __le16 resp_len; 1753 u8 unused_0[7]; 1754 u8 valid; 1755}; 1756 1757/* hwrm_func_qcaps_input (size:192b/24B) */ 1758struct hwrm_func_qcaps_input { 1759 __le16 req_type; 1760 __le16 cmpl_ring; 1761 __le16 seq_id; 1762 __le16 target_id; 1763 __le64 resp_addr; 1764 __le16 fid; 1765 u8 unused_0[6]; 1766}; 1767 1768/* hwrm_func_qcaps_output (size:1152b/144B) */ 1769struct hwrm_func_qcaps_output { 1770 __le16 error_code; 1771 __le16 req_type; 1772 __le16 seq_id; 1773 __le16 resp_len; 1774 __le16 fid; 1775 __le16 port_id; 1776 __le32 flags; 1777 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 1778 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 1779 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 1780 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 1781 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 1782 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 1783 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 1784 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 1785 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 1786 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 1787 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 1788 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 1789 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 1790 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 1791 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 1792 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 1793 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 1794 #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED 0x20000UL 1795 #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED 0x40000UL 1796 #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED 0x80000UL 1797 #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE 0x100000UL 1798 #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC 0x200000UL 1799 #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE 0x400000UL 1800 #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE 0x800000UL 1801 #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED 0x1000000UL 1802 #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD 0x2000000UL 1803 #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED 0x4000000UL 1804 #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED 0x8000000UL 1805 #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED 0x10000000UL 1806 #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED 0x20000000UL 1807 #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED 0x40000000UL 1808 #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED 0x80000000UL 1809 u8 mac_address[6]; 1810 __le16 max_rsscos_ctx; 1811 __le16 max_cmpl_rings; 1812 __le16 max_tx_rings; 1813 __le16 max_rx_rings; 1814 __le16 max_l2_ctxs; 1815 __le16 max_vnics; 1816 __le16 first_vf_id; 1817 __le16 max_vfs; 1818 __le16 max_stat_ctx; 1819 __le32 max_encap_records; 1820 __le32 max_decap_records; 1821 __le32 max_tx_em_flows; 1822 __le32 max_tx_wm_flows; 1823 __le32 max_rx_em_flows; 1824 __le32 max_rx_wm_flows; 1825 __le32 max_mcast_filters; 1826 __le32 max_flow_id; 1827 __le32 max_hw_ring_grps; 1828 __le16 max_sp_tx_rings; 1829 __le16 max_msix_vfs; 1830 __le32 flags_ext; 1831 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED 0x1UL 1832 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED 0x2UL 1833 #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED 0x4UL 1834 #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT 0x8UL 1835 #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT 0x10UL 1836 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1837 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1838 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1839 #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1840 #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1841 #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1842 #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1843 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE 0x1000UL 1844 #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED 0x2000UL 1845 #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED 0x4000UL 1846 #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED 0x8000UL 1847 #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED 0x10000UL 1848 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED 0x20000UL 1849 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED 0x40000UL 1850 #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED 0x80000UL 1851 #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED 0x100000UL 1852 #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED 0x200000UL 1853 #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED 0x400000UL 1854 #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL 0x800000UL 1855 #define FUNC_QCAPS_RESP_FLAGS_EXT_MIN_BW_SUPPORTED 0x1000000UL 1856 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_COAL_CMPL_CAP 0x2000000UL 1857 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_SUPPORTED 0x4000000UL 1858 #define FUNC_QCAPS_RESP_FLAGS_EXT_BS_V2_REQUIRED 0x8000000UL 1859 #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_64BIT_RTC_SUPPORTED 0x10000000UL 1860 #define FUNC_QCAPS_RESP_FLAGS_EXT_DBR_PACING_SUPPORTED 0x20000000UL 1861 #define FUNC_QCAPS_RESP_FLAGS_EXT_HW_DBR_DROP_RECOV_SUPPORTED 0x40000000UL 1862 #define FUNC_QCAPS_RESP_FLAGS_EXT_DISABLE_CQ_OVERFLOW_DETECTION_SUPPORTED 0x80000000UL 1863 u8 max_schqs; 1864 u8 mpc_chnls_cap; 1865 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL 1866 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE 0x2UL 1867 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA 0x4UL 1868 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA 0x8UL 1869 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE 0x10UL 1870 __le16 max_key_ctxs_alloc; 1871 __le32 flags_ext2; 1872 #define FUNC_QCAPS_RESP_FLAGS_EXT2_RX_ALL_PKTS_TIMESTAMPS_SUPPORTED 0x1UL 1873 #define FUNC_QCAPS_RESP_FLAGS_EXT2_QUIC_SUPPORTED 0x2UL 1874 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KDNET_SUPPORTED 0x4UL 1875 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_EXT_SUPPORTED 0x8UL 1876 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_DBR_DROP_RECOVERY_SUPPORTED 0x10UL 1877 #define FUNC_QCAPS_RESP_FLAGS_EXT2_GENERIC_STATS_SUPPORTED 0x20UL 1878 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDP_GSO_SUPPORTED 0x40UL 1879 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SYNCE_SUPPORTED 0x80UL 1880 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DBR_PACING_V0_SUPPORTED 0x100UL 1881 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TX_PKT_TS_CMPL_SUPPORTED 0x200UL 1882 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HW_LAG_SUPPORTED 0x400UL 1883 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ON_CHIP_CTX_SUPPORTED 0x800UL 1884 #define FUNC_QCAPS_RESP_FLAGS_EXT2_STEERING_TAG_SUPPORTED 0x1000UL 1885 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ENHANCED_VF_SCALE_SUPPORTED 0x2000UL 1886 #define FUNC_QCAPS_RESP_FLAGS_EXT2_KEY_XID_PARTITION_SUPPORTED 0x4000UL 1887 #define FUNC_QCAPS_RESP_FLAGS_EXT2_CONCURRENT_KTLS_QUIC_SUPPORTED 0x8000UL 1888 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_CROSS_TC_CAP_SUPPORTED 0x10000UL 1889 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_CAP_SUPPORTED 0x20000UL 1890 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SCHQ_PER_TC_RESERVATION_SUPPORTED 0x40000UL 1891 #define FUNC_QCAPS_RESP_FLAGS_EXT2_DB_ERROR_STATS_SUPPORTED 0x80000UL 1892 #define FUNC_QCAPS_RESP_FLAGS_EXT2_ROCE_VF_RESOURCE_MGMT_SUPPORTED 0x100000UL 1893 #define FUNC_QCAPS_RESP_FLAGS_EXT2_UDCC_SUPPORTED 0x200000UL 1894 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_SO_TXTIME_SUPPORTED 0x400000UL 1895 #define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED 0x800000UL 1896 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED 0x1000000UL 1897 #define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED 0x2000000UL 1898 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED 0x4000000UL 1899 #define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED 0x8000000UL 1900 #define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED 0x10000000UL 1901 #define FUNC_QCAPS_RESP_FLAGS_EXT2_TIMED_TX_PACING_SUPPORTED 0x20000000UL 1902 #define FUNC_QCAPS_RESP_FLAGS_EXT2_VF_STAT_EJECTION_SUPPORTED 0x40000000UL 1903 #define FUNC_QCAPS_RESP_FLAGS_EXT2_HOST_COREDUMP_SUPPORTED 0x80000000UL 1904 __le16 tunnel_disable_flag; 1905 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN 0x1UL 1906 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE 0x2UL 1907 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NVGRE 0x4UL 1908 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_L2GRE 0x8UL 1909 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_GRE 0x10UL 1910 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_IPINIP 0x20UL 1911 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_MPLS 0x40UL 1912 #define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_PPPOE 0x80UL 1913 __le16 xid_partition_cap; 1914 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_TX_CK 0x1UL 1915 #define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK 0x2UL 1916 u8 device_serial_number[8]; 1917 __le16 ctxs_per_partition; 1918 __le16 max_tso_segs; 1919 __le32 roce_vf_max_av; 1920 __le32 roce_vf_max_cq; 1921 __le32 roce_vf_max_mrw; 1922 __le32 roce_vf_max_qp; 1923 __le32 roce_vf_max_srq; 1924 __le32 roce_vf_max_gid; 1925 __le32 flags_ext3; 1926 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RM_RSV_WHILE_ALLOC_CAP 0x1UL 1927 #define FUNC_QCAPS_RESP_FLAGS_EXT3_REQUIRE_L2_FILTER 0x2UL 1928 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MAX_ROCE_VFS_SUPPORTED 0x4UL 1929 #define FUNC_QCAPS_RESP_FLAGS_EXT3_RX_RATE_PROFILE_SEL_SUPPORTED 0x8UL 1930 #define FUNC_QCAPS_RESP_FLAGS_EXT3_BIDI_OPT_SUPPORTED 0x10UL 1931 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MIRROR_ON_ROCE_SUPPORTED 0x20UL 1932 #define FUNC_QCAPS_RESP_FLAGS_EXT3_ROCE_VF_DYN_ALLOC_SUPPORT 0x40UL 1933 #define FUNC_QCAPS_RESP_FLAGS_EXT3_CHANGE_UDP_SRCPORT_SUPPORT 0x80UL 1934 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_COMPLIANCE_SUPPORTED 0x100UL 1935 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MULTI_L2_DB_SUPPORTED 0x200UL 1936 #define FUNC_QCAPS_RESP_FLAGS_EXT3_PCIE_SECURE_ATS_SUPPORTED 0x400UL 1937 #define FUNC_QCAPS_RESP_FLAGS_EXT3_MBUF_STATS_SUPPORTED 0x800UL 1938 __le16 max_roce_vfs; 1939 __le16 max_crypto_rx_flow_filters; 1940 u8 unused_3[3]; 1941 u8 valid; 1942}; 1943 1944/* hwrm_func_qcfg_input (size:192b/24B) */ 1945struct hwrm_func_qcfg_input { 1946 __le16 req_type; 1947 __le16 cmpl_ring; 1948 __le16 seq_id; 1949 __le16 target_id; 1950 __le64 resp_addr; 1951 __le16 fid; 1952 u8 unused_0[6]; 1953}; 1954 1955/* hwrm_func_qcfg_output (size:1408b/176B) */ 1956struct hwrm_func_qcfg_output { 1957 __le16 error_code; 1958 __le16 req_type; 1959 __le16 seq_id; 1960 __le16 resp_len; 1961 __le16 fid; 1962 __le16 port_id; 1963 __le16 vlan; 1964 __le16 flags; 1965 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 1966 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 1967 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 1968 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 1969 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 1970 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 1971 #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF 0x40UL 1972 #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED 0x80UL 1973 #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x100UL 1974 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1975 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1976 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1977 #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1978 #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT 0x2000UL 1979 #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV 0x4000UL 1980 #define FUNC_QCFG_RESP_FLAGS_ROCE_VNIC_ID_VALID 0x8000UL 1981 u8 mac_address[6]; 1982 __le16 pci_id; 1983 __le16 alloc_rsscos_ctx; 1984 __le16 alloc_cmpl_rings; 1985 __le16 alloc_tx_rings; 1986 __le16 alloc_rx_rings; 1987 __le16 alloc_l2_ctx; 1988 __le16 alloc_vnics; 1989 __le16 admin_mtu; 1990 __le16 mru; 1991 __le16 stat_ctx_id; 1992 u8 port_partition_type; 1993 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 1994 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 1995 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 1996 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 1997 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 1998 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL 1999 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 2000 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 2001 u8 port_pf_cnt; 2002 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 2003 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 2004 __le16 dflt_vnic_id; 2005 __le16 max_mtu_configured; 2006 __le32 min_bw; 2007 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2008 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 2009 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 2010 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 2011 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 2012 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 2013 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2014 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 2015 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2016 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2017 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2018 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2019 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2020 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2021 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 2022 __le32 max_bw; 2023 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2024 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 2025 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 2026 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 2027 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 2028 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 2029 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2030 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 2031 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2032 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2033 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2034 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2035 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2036 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2037 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 2038 u8 evb_mode; 2039 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 2040 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 2041 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 2042 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 2043 u8 options; 2044 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2045 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 2046 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2047 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2048 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 2049 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2050 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT 2 2051 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2052 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2053 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2054 #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO 2055 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xf0UL 2056 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 4 2057 __le16 alloc_vfs; 2058 __le32 alloc_mcast_filters; 2059 __le32 alloc_hw_ring_grps; 2060 __le16 alloc_sp_tx_rings; 2061 __le16 alloc_stat_ctx; 2062 __le16 alloc_msix; 2063 __le16 registered_vfs; 2064 __le16 l2_doorbell_bar_size_kb; 2065 u8 active_endpoints; 2066 u8 always_1; 2067 __le32 reset_addr_poll; 2068 __le16 legacy_l2_db_size_kb; 2069 __le16 svif_info; 2070 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK 0x7fffUL 2071 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT 0 2072 #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID 0x8000UL 2073 u8 mpc_chnls; 2074 #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED 0x1UL 2075 #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED 0x2UL 2076 #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED 0x4UL 2077 #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED 0x8UL 2078 #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED 0x10UL 2079 u8 db_page_size; 2080 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4KB 0x0UL 2081 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_8KB 0x1UL 2082 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_16KB 0x2UL 2083 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_32KB 0x3UL 2084 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_64KB 0x4UL 2085 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_128KB 0x5UL 2086 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_256KB 0x6UL 2087 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_512KB 0x7UL 2088 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_1MB 0x8UL 2089 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_2MB 0x9UL 2090 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 0xaUL 2091 #define FUNC_QCFG_RESP_DB_PAGE_SIZE_LAST FUNC_QCFG_RESP_DB_PAGE_SIZE_4MB 2092 __le16 roce_vnic_id; 2093 __le32 partition_min_bw; 2094 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2095 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT 0 2096 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE 0x10000000UL 2097 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2098 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2099 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES 2100 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2101 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2102 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2103 #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2104 __le32 partition_max_bw; 2105 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2106 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT 0 2107 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE 0x10000000UL 2108 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2109 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2110 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES 2111 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2112 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2113 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2114 #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2115 __le16 host_mtu; 2116 __le16 flags2; 2117 #define FUNC_QCFG_RESP_FLAGS2_SRIOV_DSCP_INSERT_ENABLED 0x1UL 2118 __le16 stag_vid; 2119 u8 port_kdnet_mode; 2120 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_DISABLED 0x0UL 2121 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 0x1UL 2122 #define FUNC_QCFG_RESP_PORT_KDNET_MODE_LAST FUNC_QCFG_RESP_PORT_KDNET_MODE_ENABLED 2123 u8 kdnet_pcie_function; 2124 __le16 port_kdnet_fid; 2125 u8 unused_5; 2126 u8 roce_bidi_opt_mode; 2127 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DISABLED 0x1UL 2128 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_DEDICATED 0x2UL 2129 #define FUNC_QCFG_RESP_ROCE_BIDI_OPT_MODE_SHARED 0x4UL 2130 __le32 num_ktls_tx_key_ctxs; 2131 __le32 num_ktls_rx_key_ctxs; 2132 u8 lag_id; 2133 u8 parif; 2134 u8 fw_lag_id; 2135 u8 unused_6; 2136 __le32 num_quic_tx_key_ctxs; 2137 __le32 num_quic_rx_key_ctxs; 2138 __le32 roce_max_av_per_vf; 2139 __le32 roce_max_cq_per_vf; 2140 __le32 roce_max_mrw_per_vf; 2141 __le32 roce_max_qp_per_vf; 2142 __le32 roce_max_srq_per_vf; 2143 __le32 roce_max_gid_per_vf; 2144 __le16 xid_partition_cfg; 2145 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_TX_CK 0x1UL 2146 #define FUNC_QCFG_RESP_XID_PARTITION_CFG_RX_CK 0x2UL 2147 __le16 mirror_vnic_id; 2148 u8 max_link_width; 2149 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_UNKNOWN 0x0UL 2150 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X1 0x1UL 2151 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X2 0x2UL 2152 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X4 0x4UL 2153 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X8 0x8UL 2154 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 0x10UL 2155 #define FUNC_QCFG_RESP_MAX_LINK_WIDTH_LAST FUNC_QCFG_RESP_MAX_LINK_WIDTH_X16 2156 u8 max_link_speed; 2157 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_UNKNOWN 0x0UL 2158 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G1 0x1UL 2159 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G2 0x2UL 2160 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G3 0x3UL 2161 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G4 0x4UL 2162 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 0x5UL 2163 #define FUNC_QCFG_RESP_MAX_LINK_SPEED_LAST FUNC_QCFG_RESP_MAX_LINK_SPEED_G5 2164 u8 negotiated_link_width; 2165 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_UNKNOWN 0x0UL 2166 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X1 0x1UL 2167 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X2 0x2UL 2168 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X4 0x4UL 2169 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X8 0x8UL 2170 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 0x10UL 2171 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_WIDTH_X16 2172 u8 negotiated_link_speed; 2173 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_UNKNOWN 0x0UL 2174 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G1 0x1UL 2175 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G2 0x2UL 2176 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G3 0x3UL 2177 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G4 0x4UL 2178 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 0x5UL 2179 #define FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_LAST FUNC_QCFG_RESP_NEGOTIATED_LINK_SPEED_G5 2180 u8 unused_7[2]; 2181 u8 pcie_compliance; 2182 u8 unused_8; 2183 __le16 l2_db_multi_page_size_kb; 2184 u8 unused_9[5]; 2185 u8 valid; 2186}; 2187 2188/* hwrm_func_cfg_input (size:1280b/160B) */ 2189struct hwrm_func_cfg_input { 2190 __le16 req_type; 2191 __le16 cmpl_ring; 2192 __le16 seq_id; 2193 __le16 target_id; 2194 __le64 resp_addr; 2195 __le16 fid; 2196 __le16 num_msix; 2197 __le32 flags; 2198 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 2199 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 2200 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 2201 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 2202 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 2203 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 2204 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 2205 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 2206 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 2207 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 2208 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 2209 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 2210 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 2211 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 2212 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 2213 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 2214 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE 0x200000UL 2215 #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC 0x400000UL 2216 #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST 0x800000UL 2217 #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE 0x1000000UL 2218 #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS 0x2000000UL 2219 #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS 0x4000000UL 2220 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE 0x8000000UL 2221 #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE 0x10000000UL 2222 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE 0x20000000UL 2223 #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE 0x40000000UL 2224 __le32 enables; 2225 #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU 0x1UL 2226 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 2227 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 2228 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 2229 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 2230 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 2231 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 2232 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 2233 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 2234 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 2235 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 2236 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 2237 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 2238 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 2239 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 2240 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 2241 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 2242 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 2243 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 2244 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 2245 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 2246 #define FUNC_CFG_REQ_ENABLES_NUM_MSIX 0x200000UL 2247 #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE 0x400000UL 2248 #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT 0x800000UL 2249 #define FUNC_CFG_REQ_ENABLES_SCHQ_ID 0x1000000UL 2250 #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS 0x2000000UL 2251 #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW 0x4000000UL 2252 #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW 0x8000000UL 2253 #define FUNC_CFG_REQ_ENABLES_TPID 0x10000000UL 2254 #define FUNC_CFG_REQ_ENABLES_HOST_MTU 0x20000000UL 2255 #define FUNC_CFG_REQ_ENABLES_KTLS_TX_KEY_CTXS 0x40000000UL 2256 #define FUNC_CFG_REQ_ENABLES_KTLS_RX_KEY_CTXS 0x80000000UL 2257 __le16 admin_mtu; 2258 __le16 mru; 2259 __le16 num_rsscos_ctxs; 2260 __le16 num_cmpl_rings; 2261 __le16 num_tx_rings; 2262 __le16 num_rx_rings; 2263 __le16 num_l2_ctxs; 2264 __le16 num_vnics; 2265 __le16 num_stat_ctxs; 2266 __le16 num_hw_ring_grps; 2267 u8 dflt_mac_addr[6]; 2268 __le16 dflt_vlan; 2269 __be32 dflt_ip_addr[4]; 2270 __le32 min_bw; 2271 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2272 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 2273 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 2274 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 2275 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 2276 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 2277 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2278 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 2279 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2280 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2281 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2282 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2283 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2284 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2285 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 2286 __le32 max_bw; 2287 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2288 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 2289 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 2290 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 2291 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 2292 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 2293 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2294 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 2295 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2296 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2297 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2298 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2299 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2300 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2301 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 2302 __le16 async_event_cr; 2303 u8 vlan_antispoof_mode; 2304 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 2305 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 2306 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 2307 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 2308 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 2309 u8 allowed_vlan_pris; 2310 u8 evb_mode; 2311 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 2312 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 2313 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 2314 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 2315 u8 options; 2316 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 2317 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 2318 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 2319 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 2320 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 2321 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK 0xcUL 2322 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT 2 2323 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN (0x0UL << 2) 2324 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP (0x1UL << 2) 2325 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO (0x2UL << 2) 2326 #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO 2327 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xf0UL 2328 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 4 2329 __le16 num_mcast_filters; 2330 __le16 schq_id; 2331 __le16 mpc_chnls; 2332 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE 0x1UL 2333 #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE 0x2UL 2334 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE 0x4UL 2335 #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE 0x8UL 2336 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE 0x10UL 2337 #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE 0x20UL 2338 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE 0x40UL 2339 #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE 0x80UL 2340 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE 0x100UL 2341 #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE 0x200UL 2342 __le32 partition_min_bw; 2343 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2344 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT 0 2345 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE 0x10000000UL 2346 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS (0x0UL << 28) 2347 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES (0x1UL << 28) 2348 #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES 2349 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2350 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT 29 2351 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2352 #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 2353 __le32 partition_max_bw; 2354 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2355 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT 0 2356 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE 0x10000000UL 2357 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS (0x0UL << 28) 2358 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES (0x1UL << 28) 2359 #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES 2360 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2361 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT 29 2362 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2363 #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 2364 __be16 tpid; 2365 __le16 host_mtu; 2366 __le32 flags2; 2367 #define FUNC_CFG_REQ_FLAGS2_KTLS_KEY_CTX_ASSETS_TEST 0x1UL 2368 #define FUNC_CFG_REQ_FLAGS2_QUIC_KEY_CTX_ASSETS_TEST 0x2UL 2369 __le32 enables2; 2370 #define FUNC_CFG_REQ_ENABLES2_KDNET 0x1UL 2371 #define FUNC_CFG_REQ_ENABLES2_DB_PAGE_SIZE 0x2UL 2372 #define FUNC_CFG_REQ_ENABLES2_QUIC_TX_KEY_CTXS 0x4UL 2373 #define FUNC_CFG_REQ_ENABLES2_QUIC_RX_KEY_CTXS 0x8UL 2374 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_AV_PER_VF 0x10UL 2375 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_CQ_PER_VF 0x20UL 2376 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_MRW_PER_VF 0x40UL 2377 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_QP_PER_VF 0x80UL 2378 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_SRQ_PER_VF 0x100UL 2379 #define FUNC_CFG_REQ_ENABLES2_ROCE_MAX_GID_PER_VF 0x200UL 2380 #define FUNC_CFG_REQ_ENABLES2_XID_PARTITION_CFG 0x400UL 2381 #define FUNC_CFG_REQ_ENABLES2_PHYSICAL_SLOT_NUMBER 0x800UL 2382 #define FUNC_CFG_REQ_ENABLES2_PCIE_COMPLIANCE 0x1000UL 2383 u8 port_kdnet_mode; 2384 #define FUNC_CFG_REQ_PORT_KDNET_MODE_DISABLED 0x0UL 2385 #define FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 0x1UL 2386 #define FUNC_CFG_REQ_PORT_KDNET_MODE_LAST FUNC_CFG_REQ_PORT_KDNET_MODE_ENABLED 2387 u8 db_page_size; 2388 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4KB 0x0UL 2389 #define FUNC_CFG_REQ_DB_PAGE_SIZE_8KB 0x1UL 2390 #define FUNC_CFG_REQ_DB_PAGE_SIZE_16KB 0x2UL 2391 #define FUNC_CFG_REQ_DB_PAGE_SIZE_32KB 0x3UL 2392 #define FUNC_CFG_REQ_DB_PAGE_SIZE_64KB 0x4UL 2393 #define FUNC_CFG_REQ_DB_PAGE_SIZE_128KB 0x5UL 2394 #define FUNC_CFG_REQ_DB_PAGE_SIZE_256KB 0x6UL 2395 #define FUNC_CFG_REQ_DB_PAGE_SIZE_512KB 0x7UL 2396 #define FUNC_CFG_REQ_DB_PAGE_SIZE_1MB 0x8UL 2397 #define FUNC_CFG_REQ_DB_PAGE_SIZE_2MB 0x9UL 2398 #define FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 0xaUL 2399 #define FUNC_CFG_REQ_DB_PAGE_SIZE_LAST FUNC_CFG_REQ_DB_PAGE_SIZE_4MB 2400 __le16 physical_slot_number; 2401 __le32 num_ktls_tx_key_ctxs; 2402 __le32 num_ktls_rx_key_ctxs; 2403 __le32 num_quic_tx_key_ctxs; 2404 __le32 num_quic_rx_key_ctxs; 2405 __le32 roce_max_av_per_vf; 2406 __le32 roce_max_cq_per_vf; 2407 __le32 roce_max_mrw_per_vf; 2408 __le32 roce_max_qp_per_vf; 2409 __le32 roce_max_srq_per_vf; 2410 __le32 roce_max_gid_per_vf; 2411 __le16 xid_partition_cfg; 2412 #define FUNC_CFG_REQ_XID_PARTITION_CFG_TX_CK 0x1UL 2413 #define FUNC_CFG_REQ_XID_PARTITION_CFG_RX_CK 0x2UL 2414 u8 pcie_compliance; 2415 u8 unused_2; 2416}; 2417 2418/* hwrm_func_cfg_output (size:128b/16B) */ 2419struct hwrm_func_cfg_output { 2420 __le16 error_code; 2421 __le16 req_type; 2422 __le16 seq_id; 2423 __le16 resp_len; 2424 u8 unused_0[7]; 2425 u8 valid; 2426}; 2427 2428/* hwrm_func_cfg_cmd_err (size:64b/8B) */ 2429struct hwrm_func_cfg_cmd_err { 2430 u8 code; 2431 #define FUNC_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 2432 #define FUNC_CFG_CMD_ERR_CODE_PARTITION_BW_OUT_OF_RANGE 0x1UL 2433 #define FUNC_CFG_CMD_ERR_CODE_NPAR_PARTITION_DOWN_FAILED 0x2UL 2434 #define FUNC_CFG_CMD_ERR_CODE_TPID_SET_DFLT_VLAN_NOT_SET 0x3UL 2435 #define FUNC_CFG_CMD_ERR_CODE_RES_ARRAY_ALLOC_FAILED 0x4UL 2436 #define FUNC_CFG_CMD_ERR_CODE_TX_RING_ASSET_TEST_FAILED 0x5UL 2437 #define FUNC_CFG_CMD_ERR_CODE_TX_RING_RES_UPDATE_FAILED 0x6UL 2438 #define FUNC_CFG_CMD_ERR_CODE_APPLY_MAX_BW_FAILED 0x7UL 2439 #define FUNC_CFG_CMD_ERR_CODE_ENABLE_EVB_FAILED 0x8UL 2440 #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_ASSET_TEST_FAILED 0x9UL 2441 #define FUNC_CFG_CMD_ERR_CODE_RSS_CTXT_RES_UPDATE_FAILED 0xaUL 2442 #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_ASSET_TEST_FAILED 0xbUL 2443 #define FUNC_CFG_CMD_ERR_CODE_CMPL_RING_RES_UPDATE_FAILED 0xcUL 2444 #define FUNC_CFG_CMD_ERR_CODE_NQ_ASSET_TEST_FAILED 0xdUL 2445 #define FUNC_CFG_CMD_ERR_CODE_NQ_RES_UPDATE_FAILED 0xeUL 2446 #define FUNC_CFG_CMD_ERR_CODE_RX_RING_ASSET_TEST_FAILED 0xfUL 2447 #define FUNC_CFG_CMD_ERR_CODE_RX_RING_RES_UPDATE_FAILED 0x10UL 2448 #define FUNC_CFG_CMD_ERR_CODE_VNIC_ASSET_TEST_FAILED 0x11UL 2449 #define FUNC_CFG_CMD_ERR_CODE_VNIC_RES_UPDATE_FAILED 0x12UL 2450 #define FUNC_CFG_CMD_ERR_CODE_FAILED_TO_START_STATS_THREAD 0x13UL 2451 #define FUNC_CFG_CMD_ERR_CODE_RDMA_SRIOV_DISABLED 0x14UL 2452 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_DISABLED 0x15UL 2453 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_ASSET_TEST_FAILED 0x16UL 2454 #define FUNC_CFG_CMD_ERR_CODE_TX_KTLS_RES_UPDATE_FAILED 0x17UL 2455 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_DISABLED 0x18UL 2456 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_ASSET_TEST_FAILED 0x19UL 2457 #define FUNC_CFG_CMD_ERR_CODE_RX_KTLS_RES_UPDATE_FAILED 0x1aUL 2458 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_DISABLED 0x1bUL 2459 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_ASSET_TEST_FAILED 0x1cUL 2460 #define FUNC_CFG_CMD_ERR_CODE_TX_QUIC_RES_UPDATE_FAILED 0x1dUL 2461 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_DISABLED 0x1eUL 2462 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_ASSET_TEST_FAILED 0x1fUL 2463 #define FUNC_CFG_CMD_ERR_CODE_RX_QUIC_RES_UPDATE_FAILED 0x20UL 2464 #define FUNC_CFG_CMD_ERR_CODE_INVALID_KDNET_MODE 0x21UL 2465 #define FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 0x22UL 2466 #define FUNC_CFG_CMD_ERR_CODE_LAST FUNC_CFG_CMD_ERR_CODE_SCHQ_CFG_FAIL 2467 u8 unused_0[7]; 2468}; 2469 2470/* hwrm_func_qstats_input (size:192b/24B) */ 2471struct hwrm_func_qstats_input { 2472 __le16 req_type; 2473 __le16 cmpl_ring; 2474 __le16 seq_id; 2475 __le16 target_id; 2476 __le64 resp_addr; 2477 __le16 fid; 2478 u8 flags; 2479 #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY 0x1UL 2480 #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL 2481 #define FUNC_QSTATS_REQ_FLAGS_L2_ONLY 0x4UL 2482 u8 unused_0[5]; 2483}; 2484 2485/* hwrm_func_qstats_output (size:1408b/176B) */ 2486struct hwrm_func_qstats_output { 2487 __le16 error_code; 2488 __le16 req_type; 2489 __le16 seq_id; 2490 __le16 resp_len; 2491 __le64 tx_ucast_pkts; 2492 __le64 tx_mcast_pkts; 2493 __le64 tx_bcast_pkts; 2494 __le64 tx_discard_pkts; 2495 __le64 tx_drop_pkts; 2496 __le64 tx_ucast_bytes; 2497 __le64 tx_mcast_bytes; 2498 __le64 tx_bcast_bytes; 2499 __le64 rx_ucast_pkts; 2500 __le64 rx_mcast_pkts; 2501 __le64 rx_bcast_pkts; 2502 __le64 rx_discard_pkts; 2503 __le64 rx_drop_pkts; 2504 __le64 rx_ucast_bytes; 2505 __le64 rx_mcast_bytes; 2506 __le64 rx_bcast_bytes; 2507 __le64 rx_agg_pkts; 2508 __le64 rx_agg_bytes; 2509 __le64 rx_agg_events; 2510 __le64 rx_agg_aborts; 2511 u8 clear_seq; 2512 u8 unused_0[6]; 2513 u8 valid; 2514}; 2515 2516/* hwrm_func_qstats_ext_input (size:256b/32B) */ 2517struct hwrm_func_qstats_ext_input { 2518 __le16 req_type; 2519 __le16 cmpl_ring; 2520 __le16 seq_id; 2521 __le16 target_id; 2522 __le64 resp_addr; 2523 __le16 fid; 2524 u8 flags; 2525 #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY 0x1UL 2526 #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL 2527 u8 unused_0[1]; 2528 __le32 enables; 2529 #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID 0x1UL 2530 __le16 schq_id; 2531 __le16 traffic_class; 2532 u8 unused_1[4]; 2533}; 2534 2535/* hwrm_func_qstats_ext_output (size:1536b/192B) */ 2536struct hwrm_func_qstats_ext_output { 2537 __le16 error_code; 2538 __le16 req_type; 2539 __le16 seq_id; 2540 __le16 resp_len; 2541 __le64 rx_ucast_pkts; 2542 __le64 rx_mcast_pkts; 2543 __le64 rx_bcast_pkts; 2544 __le64 rx_discard_pkts; 2545 __le64 rx_error_pkts; 2546 __le64 rx_ucast_bytes; 2547 __le64 rx_mcast_bytes; 2548 __le64 rx_bcast_bytes; 2549 __le64 tx_ucast_pkts; 2550 __le64 tx_mcast_pkts; 2551 __le64 tx_bcast_pkts; 2552 __le64 tx_error_pkts; 2553 __le64 tx_discard_pkts; 2554 __le64 tx_ucast_bytes; 2555 __le64 tx_mcast_bytes; 2556 __le64 tx_bcast_bytes; 2557 __le64 rx_tpa_eligible_pkt; 2558 __le64 rx_tpa_eligible_bytes; 2559 __le64 rx_tpa_pkt; 2560 __le64 rx_tpa_bytes; 2561 __le64 rx_tpa_errors; 2562 __le64 rx_tpa_events; 2563 u8 unused_0[7]; 2564 u8 valid; 2565}; 2566 2567/* hwrm_func_clr_stats_input (size:192b/24B) */ 2568struct hwrm_func_clr_stats_input { 2569 __le16 req_type; 2570 __le16 cmpl_ring; 2571 __le16 seq_id; 2572 __le16 target_id; 2573 __le64 resp_addr; 2574 __le16 fid; 2575 u8 unused_0[6]; 2576}; 2577 2578/* hwrm_func_clr_stats_output (size:128b/16B) */ 2579struct hwrm_func_clr_stats_output { 2580 __le16 error_code; 2581 __le16 req_type; 2582 __le16 seq_id; 2583 __le16 resp_len; 2584 u8 unused_0[7]; 2585 u8 valid; 2586}; 2587 2588/* hwrm_func_vf_resc_free_input (size:192b/24B) */ 2589struct hwrm_func_vf_resc_free_input { 2590 __le16 req_type; 2591 __le16 cmpl_ring; 2592 __le16 seq_id; 2593 __le16 target_id; 2594 __le64 resp_addr; 2595 __le16 vf_id; 2596 u8 unused_0[6]; 2597}; 2598 2599/* hwrm_func_vf_resc_free_output (size:128b/16B) */ 2600struct hwrm_func_vf_resc_free_output { 2601 __le16 error_code; 2602 __le16 req_type; 2603 __le16 seq_id; 2604 __le16 resp_len; 2605 u8 unused_0[7]; 2606 u8 valid; 2607}; 2608 2609/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 2610struct hwrm_func_drv_rgtr_input { 2611 __le16 req_type; 2612 __le16 cmpl_ring; 2613 __le16 seq_id; 2614 __le16 target_id; 2615 __le64 resp_addr; 2616 __le32 flags; 2617 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 2618 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 2619 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 2620 #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE 0x8UL 2621 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 2622 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 2623 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 2624 #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 2625 #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT 0x100UL 2626 #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT 0x200UL 2627 #define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT 0x400UL 2628 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE 0x800UL 2629 #define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE 0x1000UL 2630 __le32 enables; 2631 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 2632 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 2633 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 2634 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 2635 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 2636 __le16 os_type; 2637 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 2638 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 2639 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 2640 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 2641 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 2642 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 2643 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 2644 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 2645 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 2646 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 2647 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 2648 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 2649 u8 ver_maj_8b; 2650 u8 ver_min_8b; 2651 u8 ver_upd_8b; 2652 u8 unused_0[3]; 2653 __le32 timestamp; 2654 u8 unused_1[4]; 2655 __le32 vf_req_fwd[8]; 2656 __le32 async_event_fwd[8]; 2657 __le16 ver_maj; 2658 __le16 ver_min; 2659 __le16 ver_upd; 2660 __le16 ver_patch; 2661}; 2662 2663/* hwrm_func_drv_rgtr_output (size:128b/16B) */ 2664struct hwrm_func_drv_rgtr_output { 2665 __le16 error_code; 2666 __le16 req_type; 2667 __le16 seq_id; 2668 __le16 resp_len; 2669 __le32 flags; 2670 #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED 0x1UL 2671 u8 unused_0[3]; 2672 u8 valid; 2673}; 2674 2675/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 2676struct hwrm_func_drv_unrgtr_input { 2677 __le16 req_type; 2678 __le16 cmpl_ring; 2679 __le16 seq_id; 2680 __le16 target_id; 2681 __le64 resp_addr; 2682 __le32 flags; 2683 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 2684 u8 unused_0[4]; 2685}; 2686 2687/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 2688struct hwrm_func_drv_unrgtr_output { 2689 __le16 error_code; 2690 __le16 req_type; 2691 __le16 seq_id; 2692 __le16 resp_len; 2693 u8 unused_0[7]; 2694 u8 valid; 2695}; 2696 2697/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 2698struct hwrm_func_buf_rgtr_input { 2699 __le16 req_type; 2700 __le16 cmpl_ring; 2701 __le16 seq_id; 2702 __le16 target_id; 2703 __le64 resp_addr; 2704 __le32 enables; 2705 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 2706 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 2707 __le16 vf_id; 2708 __le16 req_buf_num_pages; 2709 __le16 req_buf_page_size; 2710 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 2711 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 2712 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 2713 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 2714 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 2715 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 2716 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 2717 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 2718 __le16 req_buf_len; 2719 __le16 resp_buf_len; 2720 u8 unused_0[2]; 2721 __le64 req_buf_page_addr0; 2722 __le64 req_buf_page_addr1; 2723 __le64 req_buf_page_addr2; 2724 __le64 req_buf_page_addr3; 2725 __le64 req_buf_page_addr4; 2726 __le64 req_buf_page_addr5; 2727 __le64 req_buf_page_addr6; 2728 __le64 req_buf_page_addr7; 2729 __le64 req_buf_page_addr8; 2730 __le64 req_buf_page_addr9; 2731 __le64 error_buf_addr; 2732 __le64 resp_buf_addr; 2733}; 2734 2735/* hwrm_func_buf_rgtr_output (size:128b/16B) */ 2736struct hwrm_func_buf_rgtr_output { 2737 __le16 error_code; 2738 __le16 req_type; 2739 __le16 seq_id; 2740 __le16 resp_len; 2741 u8 unused_0[7]; 2742 u8 valid; 2743}; 2744 2745/* hwrm_func_drv_qver_input (size:192b/24B) */ 2746struct hwrm_func_drv_qver_input { 2747 __le16 req_type; 2748 __le16 cmpl_ring; 2749 __le16 seq_id; 2750 __le16 target_id; 2751 __le64 resp_addr; 2752 __le32 reserved; 2753 __le16 fid; 2754 u8 driver_type; 2755 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_L2 0x0UL 2756 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 0x1UL 2757 #define FUNC_DRV_QVER_REQ_DRIVER_TYPE_LAST FUNC_DRV_QVER_REQ_DRIVER_TYPE_ROCE 2758 u8 unused_0; 2759}; 2760 2761/* hwrm_func_drv_qver_output (size:256b/32B) */ 2762struct hwrm_func_drv_qver_output { 2763 __le16 error_code; 2764 __le16 req_type; 2765 __le16 seq_id; 2766 __le16 resp_len; 2767 __le16 os_type; 2768 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 2769 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 2770 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 2771 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 2772 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 2773 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 2774 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 2775 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 2776 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 2777 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 2778 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 2779 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 2780 u8 ver_maj_8b; 2781 u8 ver_min_8b; 2782 u8 ver_upd_8b; 2783 u8 unused_0[3]; 2784 __le16 ver_maj; 2785 __le16 ver_min; 2786 __le16 ver_upd; 2787 __le16 ver_patch; 2788 u8 unused_1[7]; 2789 u8 valid; 2790}; 2791 2792/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 2793struct hwrm_func_resource_qcaps_input { 2794 __le16 req_type; 2795 __le16 cmpl_ring; 2796 __le16 seq_id; 2797 __le16 target_id; 2798 __le64 resp_addr; 2799 __le16 fid; 2800 u8 unused_0[6]; 2801}; 2802 2803/* hwrm_func_resource_qcaps_output (size:704b/88B) */ 2804struct hwrm_func_resource_qcaps_output { 2805 __le16 error_code; 2806 __le16 req_type; 2807 __le16 seq_id; 2808 __le16 resp_len; 2809 __le16 max_vfs; 2810 __le16 max_msix; 2811 __le16 vf_reservation_strategy; 2812 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 2813 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 2814 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 2815 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 2816 __le16 min_rsscos_ctx; 2817 __le16 max_rsscos_ctx; 2818 __le16 min_cmpl_rings; 2819 __le16 max_cmpl_rings; 2820 __le16 min_tx_rings; 2821 __le16 max_tx_rings; 2822 __le16 min_rx_rings; 2823 __le16 max_rx_rings; 2824 __le16 min_l2_ctxs; 2825 __le16 max_l2_ctxs; 2826 __le16 min_vnics; 2827 __le16 max_vnics; 2828 __le16 min_stat_ctx; 2829 __le16 max_stat_ctx; 2830 __le16 min_hw_ring_grps; 2831 __le16 max_hw_ring_grps; 2832 __le16 max_tx_scheduler_inputs; 2833 __le16 flags; 2834 #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED 0x1UL 2835 __le16 min_msix; 2836 __le32 min_ktls_tx_key_ctxs; 2837 __le32 max_ktls_tx_key_ctxs; 2838 __le32 min_ktls_rx_key_ctxs; 2839 __le32 max_ktls_rx_key_ctxs; 2840 __le32 min_quic_tx_key_ctxs; 2841 __le32 max_quic_tx_key_ctxs; 2842 __le32 min_quic_rx_key_ctxs; 2843 __le32 max_quic_rx_key_ctxs; 2844 u8 unused_0[3]; 2845 u8 valid; 2846}; 2847 2848/* hwrm_func_vf_resource_cfg_input (size:704b/88B) */ 2849struct hwrm_func_vf_resource_cfg_input { 2850 __le16 req_type; 2851 __le16 cmpl_ring; 2852 __le16 seq_id; 2853 __le16 target_id; 2854 __le64 resp_addr; 2855 __le16 vf_id; 2856 __le16 max_msix; 2857 __le16 min_rsscos_ctx; 2858 __le16 max_rsscos_ctx; 2859 __le16 min_cmpl_rings; 2860 __le16 max_cmpl_rings; 2861 __le16 min_tx_rings; 2862 __le16 max_tx_rings; 2863 __le16 min_rx_rings; 2864 __le16 max_rx_rings; 2865 __le16 min_l2_ctxs; 2866 __le16 max_l2_ctxs; 2867 __le16 min_vnics; 2868 __le16 max_vnics; 2869 __le16 min_stat_ctx; 2870 __le16 max_stat_ctx; 2871 __le16 min_hw_ring_grps; 2872 __le16 max_hw_ring_grps; 2873 __le16 flags; 2874 #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED 0x1UL 2875 __le16 min_msix; 2876 __le32 min_ktls_tx_key_ctxs; 2877 __le32 max_ktls_tx_key_ctxs; 2878 __le32 min_ktls_rx_key_ctxs; 2879 __le32 max_ktls_rx_key_ctxs; 2880 __le32 min_quic_tx_key_ctxs; 2881 __le32 max_quic_tx_key_ctxs; 2882 __le32 min_quic_rx_key_ctxs; 2883 __le32 max_quic_rx_key_ctxs; 2884}; 2885 2886/* hwrm_func_vf_resource_cfg_output (size:384b/48B) */ 2887struct hwrm_func_vf_resource_cfg_output { 2888 __le16 error_code; 2889 __le16 req_type; 2890 __le16 seq_id; 2891 __le16 resp_len; 2892 __le16 reserved_rsscos_ctx; 2893 __le16 reserved_cmpl_rings; 2894 __le16 reserved_tx_rings; 2895 __le16 reserved_rx_rings; 2896 __le16 reserved_l2_ctxs; 2897 __le16 reserved_vnics; 2898 __le16 reserved_stat_ctx; 2899 __le16 reserved_hw_ring_grps; 2900 __le32 reserved_ktls_tx_key_ctxs; 2901 __le32 reserved_ktls_rx_key_ctxs; 2902 __le32 reserved_quic_tx_key_ctxs; 2903 __le32 reserved_quic_rx_key_ctxs; 2904 u8 unused_0[7]; 2905 u8 valid; 2906}; 2907 2908/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */ 2909struct hwrm_func_backing_store_qcaps_input { 2910 __le16 req_type; 2911 __le16 cmpl_ring; 2912 __le16 seq_id; 2913 __le16 target_id; 2914 __le64 resp_addr; 2915}; 2916 2917/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */ 2918struct hwrm_func_backing_store_qcaps_output { 2919 __le16 error_code; 2920 __le16 req_type; 2921 __le16 seq_id; 2922 __le16 resp_len; 2923 __le32 qp_max_entries; 2924 __le16 qp_min_qp1_entries; 2925 __le16 qp_max_l2_entries; 2926 __le16 qp_entry_size; 2927 __le16 srq_max_l2_entries; 2928 __le32 srq_max_entries; 2929 __le16 srq_entry_size; 2930 __le16 cq_max_l2_entries; 2931 __le32 cq_max_entries; 2932 __le16 cq_entry_size; 2933 __le16 vnic_max_vnic_entries; 2934 __le16 vnic_max_ring_table_entries; 2935 __le16 vnic_entry_size; 2936 __le32 stat_max_entries; 2937 __le16 stat_entry_size; 2938 __le16 tqm_entry_size; 2939 __le32 tqm_min_entries_per_ring; 2940 __le32 tqm_max_entries_per_ring; 2941 __le32 mrav_max_entries; 2942 __le16 mrav_entry_size; 2943 __le16 tim_entry_size; 2944 __le32 tim_max_entries; 2945 __le16 mrav_num_entries_units; 2946 u8 tqm_entries_multiple; 2947 u8 ctx_kind_initializer; 2948 __le16 ctx_init_mask; 2949 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2950 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2951 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2952 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2953 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2954 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2955 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC 0x40UL 2956 #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC 0x80UL 2957 u8 qp_init_offset; 2958 u8 srq_init_offset; 2959 u8 cq_init_offset; 2960 u8 vnic_init_offset; 2961 u8 tqm_fp_rings_count; 2962 u8 stat_init_offset; 2963 u8 mrav_init_offset; 2964 u8 tqm_fp_rings_count_ext; 2965 u8 tkc_init_offset; 2966 u8 rkc_init_offset; 2967 __le16 tkc_entry_size; 2968 __le16 rkc_entry_size; 2969 __le32 tkc_max_entries; 2970 __le32 rkc_max_entries; 2971 __le16 fast_qpmd_qp_num_entries; 2972 u8 rsvd1[5]; 2973 u8 valid; 2974}; 2975 2976/* tqm_fp_ring_cfg (size:128b/16B) */ 2977struct tqm_fp_ring_cfg { 2978 u8 tqm_ring_pg_size_tqm_ring_lvl; 2979 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK 0xfUL 2980 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT 0 2981 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 0x0UL 2982 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 0x1UL 2983 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 0x2UL 2984 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 2985 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK 0xf0UL 2986 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT 4 2987 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2988 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2989 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2990 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2991 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2992 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2993 #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G 2994 u8 unused[3]; 2995 __le32 tqm_ring_num_entries; 2996 __le64 tqm_ring_page_dir; 2997}; 2998 2999/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */ 3000struct hwrm_func_backing_store_cfg_input { 3001 __le16 req_type; 3002 __le16 cmpl_ring; 3003 __le16 seq_id; 3004 __le16 target_id; 3005 __le64 resp_addr; 3006 __le32 flags; 3007 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 3008 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 3009 __le32 enables; 3010 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 3011 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 3012 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 3013 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 3014 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 3015 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 3016 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 3017 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 3018 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 3019 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 3020 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 3021 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 3022 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 3023 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 3024 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 3025 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 3026 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 3027 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 3028 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 3029 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC 0x80000UL 3030 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC 0x100000UL 3031 #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP_FAST_QPMD 0x200000UL 3032 u8 qpc_pg_size_qpc_lvl; 3033 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 3034 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 3035 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0 0x0UL 3036 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1 0x1UL 3037 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 0x2UL 3038 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2 3039 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK 0xf0UL 3040 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT 4 3041 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K (0x0UL << 4) 3042 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K (0x1UL << 4) 3043 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K (0x2UL << 4) 3044 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M (0x3UL << 4) 3045 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M (0x4UL << 4) 3046 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G (0x5UL << 4) 3047 #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G 3048 u8 srq_pg_size_srq_lvl; 3049 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK 0xfUL 3050 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT 0 3051 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0 0x0UL 3052 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1 0x1UL 3053 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 0x2UL 3054 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2 3055 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK 0xf0UL 3056 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT 4 3057 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K (0x0UL << 4) 3058 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K (0x1UL << 4) 3059 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K (0x2UL << 4) 3060 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M (0x3UL << 4) 3061 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M (0x4UL << 4) 3062 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G (0x5UL << 4) 3063 #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G 3064 u8 cq_pg_size_cq_lvl; 3065 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK 0xfUL 3066 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT 0 3067 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0 0x0UL 3068 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1 0x1UL 3069 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 0x2UL 3070 #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2 3071 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK 0xf0UL 3072 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT 4 3073 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K (0x0UL << 4) 3074 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K (0x1UL << 4) 3075 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K (0x2UL << 4) 3076 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M (0x3UL << 4) 3077 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M (0x4UL << 4) 3078 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G (0x5UL << 4) 3079 #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G 3080 u8 vnic_pg_size_vnic_lvl; 3081 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK 0xfUL 3082 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT 0 3083 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0 0x0UL 3084 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1 0x1UL 3085 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 0x2UL 3086 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2 3087 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK 0xf0UL 3088 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT 4 3089 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K (0x0UL << 4) 3090 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K (0x1UL << 4) 3091 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K (0x2UL << 4) 3092 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M (0x3UL << 4) 3093 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M (0x4UL << 4) 3094 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G (0x5UL << 4) 3095 #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G 3096 u8 stat_pg_size_stat_lvl; 3097 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK 0xfUL 3098 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT 0 3099 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0 0x0UL 3100 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1 0x1UL 3101 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 0x2UL 3102 #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2 3103 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK 0xf0UL 3104 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT 4 3105 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K (0x0UL << 4) 3106 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K (0x1UL << 4) 3107 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K (0x2UL << 4) 3108 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M (0x3UL << 4) 3109 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M (0x4UL << 4) 3110 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G (0x5UL << 4) 3111 #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G 3112 u8 tqm_sp_pg_size_tqm_sp_lvl; 3113 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK 0xfUL 3114 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT 0 3115 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0 0x0UL 3116 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1 0x1UL 3117 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 0x2UL 3118 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2 3119 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK 0xf0UL 3120 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT 4 3121 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K (0x0UL << 4) 3122 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K (0x1UL << 4) 3123 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K (0x2UL << 4) 3124 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M (0x3UL << 4) 3125 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M (0x4UL << 4) 3126 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G (0x5UL << 4) 3127 #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G 3128 u8 tqm_ring0_pg_size_tqm_ring0_lvl; 3129 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK 0xfUL 3130 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT 0 3131 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0 0x0UL 3132 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1 0x1UL 3133 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 0x2UL 3134 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2 3135 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK 0xf0UL 3136 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT 4 3137 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K (0x0UL << 4) 3138 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K (0x1UL << 4) 3139 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K (0x2UL << 4) 3140 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M (0x3UL << 4) 3141 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M (0x4UL << 4) 3142 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G (0x5UL << 4) 3143 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G 3144 u8 tqm_ring1_pg_size_tqm_ring1_lvl; 3145 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK 0xfUL 3146 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT 0 3147 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0 0x0UL 3148 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1 0x1UL 3149 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 0x2UL 3150 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2 3151 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK 0xf0UL 3152 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT 4 3153 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K (0x0UL << 4) 3154 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K (0x1UL << 4) 3155 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K (0x2UL << 4) 3156 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M (0x3UL << 4) 3157 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M (0x4UL << 4) 3158 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G (0x5UL << 4) 3159 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G 3160 u8 tqm_ring2_pg_size_tqm_ring2_lvl; 3161 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK 0xfUL 3162 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT 0 3163 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0 0x0UL 3164 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1 0x1UL 3165 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 0x2UL 3166 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2 3167 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK 0xf0UL 3168 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT 4 3169 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K (0x0UL << 4) 3170 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K (0x1UL << 4) 3171 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K (0x2UL << 4) 3172 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M (0x3UL << 4) 3173 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M (0x4UL << 4) 3174 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G (0x5UL << 4) 3175 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G 3176 u8 tqm_ring3_pg_size_tqm_ring3_lvl; 3177 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK 0xfUL 3178 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT 0 3179 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0 0x0UL 3180 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1 0x1UL 3181 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 0x2UL 3182 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2 3183 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK 0xf0UL 3184 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT 4 3185 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K (0x0UL << 4) 3186 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K (0x1UL << 4) 3187 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K (0x2UL << 4) 3188 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M (0x3UL << 4) 3189 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M (0x4UL << 4) 3190 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G (0x5UL << 4) 3191 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G 3192 u8 tqm_ring4_pg_size_tqm_ring4_lvl; 3193 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK 0xfUL 3194 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT 0 3195 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0 0x0UL 3196 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1 0x1UL 3197 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 0x2UL 3198 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2 3199 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK 0xf0UL 3200 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT 4 3201 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K (0x0UL << 4) 3202 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K (0x1UL << 4) 3203 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K (0x2UL << 4) 3204 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M (0x3UL << 4) 3205 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M (0x4UL << 4) 3206 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G (0x5UL << 4) 3207 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G 3208 u8 tqm_ring5_pg_size_tqm_ring5_lvl; 3209 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK 0xfUL 3210 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT 0 3211 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0 0x0UL 3212 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1 0x1UL 3213 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 0x2UL 3214 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2 3215 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK 0xf0UL 3216 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT 4 3217 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K (0x0UL << 4) 3218 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K (0x1UL << 4) 3219 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K (0x2UL << 4) 3220 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M (0x3UL << 4) 3221 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M (0x4UL << 4) 3222 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G (0x5UL << 4) 3223 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G 3224 u8 tqm_ring6_pg_size_tqm_ring6_lvl; 3225 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK 0xfUL 3226 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT 0 3227 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0 0x0UL 3228 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1 0x1UL 3229 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 0x2UL 3230 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2 3231 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK 0xf0UL 3232 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT 4 3233 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K (0x0UL << 4) 3234 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K (0x1UL << 4) 3235 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K (0x2UL << 4) 3236 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M (0x3UL << 4) 3237 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M (0x4UL << 4) 3238 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G (0x5UL << 4) 3239 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G 3240 u8 tqm_ring7_pg_size_tqm_ring7_lvl; 3241 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK 0xfUL 3242 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT 0 3243 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0 0x0UL 3244 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1 0x1UL 3245 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 0x2UL 3246 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2 3247 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK 0xf0UL 3248 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT 4 3249 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K (0x0UL << 4) 3250 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K (0x1UL << 4) 3251 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K (0x2UL << 4) 3252 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M (0x3UL << 4) 3253 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M (0x4UL << 4) 3254 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G (0x5UL << 4) 3255 #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G 3256 u8 mrav_pg_size_mrav_lvl; 3257 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK 0xfUL 3258 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT 0 3259 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0 0x0UL 3260 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1 0x1UL 3261 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 0x2UL 3262 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2 3263 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK 0xf0UL 3264 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT 4 3265 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K (0x0UL << 4) 3266 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K (0x1UL << 4) 3267 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K (0x2UL << 4) 3268 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M (0x3UL << 4) 3269 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M (0x4UL << 4) 3270 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G (0x5UL << 4) 3271 #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G 3272 u8 tim_pg_size_tim_lvl; 3273 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK 0xfUL 3274 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT 0 3275 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0 0x0UL 3276 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1 0x1UL 3277 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 0x2UL 3278 #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2 3279 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK 0xf0UL 3280 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT 4 3281 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K (0x0UL << 4) 3282 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K (0x1UL << 4) 3283 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K (0x2UL << 4) 3284 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M (0x3UL << 4) 3285 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M (0x4UL << 4) 3286 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G (0x5UL << 4) 3287 #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G 3288 __le64 qpc_page_dir; 3289 __le64 srq_page_dir; 3290 __le64 cq_page_dir; 3291 __le64 vnic_page_dir; 3292 __le64 stat_page_dir; 3293 __le64 tqm_sp_page_dir; 3294 __le64 tqm_ring0_page_dir; 3295 __le64 tqm_ring1_page_dir; 3296 __le64 tqm_ring2_page_dir; 3297 __le64 tqm_ring3_page_dir; 3298 __le64 tqm_ring4_page_dir; 3299 __le64 tqm_ring5_page_dir; 3300 __le64 tqm_ring6_page_dir; 3301 __le64 tqm_ring7_page_dir; 3302 __le64 mrav_page_dir; 3303 __le64 tim_page_dir; 3304 __le32 qp_num_entries; 3305 __le32 srq_num_entries; 3306 __le32 cq_num_entries; 3307 __le32 stat_num_entries; 3308 __le32 tqm_sp_num_entries; 3309 __le32 tqm_ring0_num_entries; 3310 __le32 tqm_ring1_num_entries; 3311 __le32 tqm_ring2_num_entries; 3312 __le32 tqm_ring3_num_entries; 3313 __le32 tqm_ring4_num_entries; 3314 __le32 tqm_ring5_num_entries; 3315 __le32 tqm_ring6_num_entries; 3316 __le32 tqm_ring7_num_entries; 3317 __le32 mrav_num_entries; 3318 __le32 tim_num_entries; 3319 __le16 qp_num_qp1_entries; 3320 __le16 qp_num_l2_entries; 3321 __le16 qp_entry_size; 3322 __le16 srq_num_l2_entries; 3323 __le16 srq_entry_size; 3324 __le16 cq_num_l2_entries; 3325 __le16 cq_entry_size; 3326 __le16 vnic_num_vnic_entries; 3327 __le16 vnic_num_ring_table_entries; 3328 __le16 vnic_entry_size; 3329 __le16 stat_entry_size; 3330 __le16 tqm_entry_size; 3331 __le16 mrav_entry_size; 3332 __le16 tim_entry_size; 3333 u8 tqm_ring8_pg_size_tqm_ring_lvl; 3334 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 3335 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 3336 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 3337 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 3338 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 3339 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 3340 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 3341 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 3342 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3343 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3344 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3345 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3346 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3347 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3348 #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 3349 u8 ring8_unused[3]; 3350 __le32 tqm_ring8_num_entries; 3351 __le64 tqm_ring8_page_dir; 3352 u8 tqm_ring9_pg_size_tqm_ring_lvl; 3353 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 3354 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 3355 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 3356 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 3357 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 3358 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 3359 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 3360 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 3361 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3362 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3363 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3364 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3365 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3366 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3367 #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 3368 u8 ring9_unused[3]; 3369 __le32 tqm_ring9_num_entries; 3370 __le64 tqm_ring9_page_dir; 3371 u8 tqm_ring10_pg_size_tqm_ring_lvl; 3372 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 3373 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 3374 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 3375 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 3376 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 3377 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 3378 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 3379 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 3380 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 3381 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 3382 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 3383 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 3384 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 3385 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 3386 #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 3387 u8 ring10_unused[3]; 3388 __le32 tqm_ring10_num_entries; 3389 __le64 tqm_ring10_page_dir; 3390 __le32 tkc_num_entries; 3391 __le32 rkc_num_entries; 3392 __le64 tkc_page_dir; 3393 __le64 rkc_page_dir; 3394 __le16 tkc_entry_size; 3395 __le16 rkc_entry_size; 3396 u8 tkc_pg_size_tkc_lvl; 3397 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK 0xfUL 3398 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT 0 3399 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0 0x0UL 3400 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1 0x1UL 3401 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 0x2UL 3402 #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2 3403 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK 0xf0UL 3404 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT 4 3405 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K (0x0UL << 4) 3406 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K (0x1UL << 4) 3407 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K (0x2UL << 4) 3408 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M (0x3UL << 4) 3409 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M (0x4UL << 4) 3410 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G (0x5UL << 4) 3411 #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G 3412 u8 rkc_pg_size_rkc_lvl; 3413 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK 0xfUL 3414 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT 0 3415 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0 0x0UL 3416 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1 0x1UL 3417 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 0x2UL 3418 #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2 3419 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK 0xf0UL 3420 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT 4 3421 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K (0x0UL << 4) 3422 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K (0x1UL << 4) 3423 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K (0x2UL << 4) 3424 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M (0x3UL << 4) 3425 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M (0x4UL << 4) 3426 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G (0x5UL << 4) 3427 #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G 3428 __le16 qp_num_fast_qpmd_entries; 3429}; 3430 3431/* hwrm_func_backing_store_cfg_output (size:128b/16B) */ 3432struct hwrm_func_backing_store_cfg_output { 3433 __le16 error_code; 3434 __le16 req_type; 3435 __le16 seq_id; 3436 __le16 resp_len; 3437 u8 unused_0[7]; 3438 u8 valid; 3439}; 3440 3441/* hwrm_error_recovery_qcfg_input (size:192b/24B) */ 3442struct hwrm_error_recovery_qcfg_input { 3443 __le16 req_type; 3444 __le16 cmpl_ring; 3445 __le16 seq_id; 3446 __le16 target_id; 3447 __le64 resp_addr; 3448 u8 unused_0[8]; 3449}; 3450 3451/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */ 3452struct hwrm_error_recovery_qcfg_output { 3453 __le16 error_code; 3454 __le16 req_type; 3455 __le16 seq_id; 3456 __le16 resp_len; 3457 __le32 flags; 3458 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST 0x1UL 3459 #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU 0x2UL 3460 __le32 driver_polling_freq; 3461 __le32 master_func_wait_period; 3462 __le32 normal_func_wait_period; 3463 __le32 master_func_wait_period_after_reset; 3464 __le32 max_bailout_time_after_reset; 3465 __le32 fw_health_status_reg; 3466 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK 0x3UL 3467 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT 0 3468 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3469 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC 0x1UL 3470 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 0x2UL 3471 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 0x3UL 3472 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 3473 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK 0xfffffffcUL 3474 #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT 2 3475 __le32 fw_heartbeat_reg; 3476 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK 0x3UL 3477 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT 0 3478 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3479 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC 0x1UL 3480 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 0x2UL 3481 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 0x3UL 3482 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 3483 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK 0xfffffffcUL 3484 #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT 2 3485 __le32 fw_reset_cnt_reg; 3486 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK 0x3UL 3487 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT 0 3488 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3489 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC 0x1UL 3490 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3491 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3492 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 3493 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK 0xfffffffcUL 3494 #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT 2 3495 __le32 reset_inprogress_reg; 3496 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK 0x3UL 3497 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT 0 3498 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3499 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC 0x1UL 3500 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 0x2UL 3501 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 0x3UL 3502 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 3503 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK 0xfffffffcUL 3504 #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT 2 3505 __le32 reset_inprogress_reg_mask; 3506 u8 unused_0[3]; 3507 u8 reg_array_cnt; 3508 __le32 reset_reg[16]; 3509 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK 0x3UL 3510 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT 0 3511 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3512 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC 0x1UL 3513 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0 0x2UL 3514 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 0x3UL 3515 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1 3516 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK 0xfffffffcUL 3517 #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT 2 3518 __le32 reset_reg_val[16]; 3519 u8 delay_after_reset[16]; 3520 __le32 err_recovery_cnt_reg; 3521 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK 0x3UL 3522 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT 0 3523 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG 0x0UL 3524 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC 0x1UL 3525 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0 0x2UL 3526 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 0x3UL 3527 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1 3528 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK 0xfffffffcUL 3529 #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT 2 3530 u8 unused_1[3]; 3531 u8 valid; 3532}; 3533 3534/* hwrm_func_echo_response_input (size:192b/24B) */ 3535struct hwrm_func_echo_response_input { 3536 __le16 req_type; 3537 __le16 cmpl_ring; 3538 __le16 seq_id; 3539 __le16 target_id; 3540 __le64 resp_addr; 3541 __le32 event_data1; 3542 __le32 event_data2; 3543}; 3544 3545/* hwrm_func_echo_response_output (size:128b/16B) */ 3546struct hwrm_func_echo_response_output { 3547 __le16 error_code; 3548 __le16 req_type; 3549 __le16 seq_id; 3550 __le16 resp_len; 3551 u8 unused_0[7]; 3552 u8 valid; 3553}; 3554 3555/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */ 3556struct hwrm_func_ptp_pin_qcfg_input { 3557 __le16 req_type; 3558 __le16 cmpl_ring; 3559 __le16 seq_id; 3560 __le16 target_id; 3561 __le64 resp_addr; 3562 u8 unused_0[8]; 3563}; 3564 3565/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */ 3566struct hwrm_func_ptp_pin_qcfg_output { 3567 __le16 error_code; 3568 __le16 req_type; 3569 __le16 seq_id; 3570 __le16 resp_len; 3571 u8 num_pins; 3572 u8 state; 3573 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED 0x1UL 3574 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED 0x2UL 3575 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED 0x4UL 3576 #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED 0x8UL 3577 u8 pin0_usage; 3578 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE 0x0UL 3579 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN 0x1UL 3580 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT 0x2UL 3581 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN 0x3UL 3582 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL 3583 #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 3584 u8 pin1_usage; 3585 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE 0x0UL 3586 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN 0x1UL 3587 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT 0x2UL 3588 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN 0x3UL 3589 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL 3590 #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 3591 u8 pin2_usage; 3592 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE 0x0UL 3593 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN 0x1UL 3594 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT 0x2UL 3595 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN 0x3UL 3596 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL 3597 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3598 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3599 #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3600 u8 pin3_usage; 3601 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE 0x0UL 3602 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN 0x1UL 3603 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT 0x2UL 3604 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN 0x3UL 3605 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL 3606 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3607 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3608 #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3609 u8 unused_0; 3610 u8 valid; 3611}; 3612 3613/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */ 3614struct hwrm_func_ptp_pin_cfg_input { 3615 __le16 req_type; 3616 __le16 cmpl_ring; 3617 __le16 seq_id; 3618 __le16 target_id; 3619 __le64 resp_addr; 3620 __le32 enables; 3621 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE 0x1UL 3622 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE 0x2UL 3623 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE 0x4UL 3624 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE 0x8UL 3625 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE 0x10UL 3626 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE 0x20UL 3627 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE 0x40UL 3628 #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE 0x80UL 3629 u8 pin0_state; 3630 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL 3631 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 0x1UL 3632 #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED 3633 u8 pin0_usage; 3634 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE 0x0UL 3635 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN 0x1UL 3636 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT 0x2UL 3637 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN 0x3UL 3638 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL 3639 #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 3640 u8 pin1_state; 3641 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL 3642 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 0x1UL 3643 #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED 3644 u8 pin1_usage; 3645 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE 0x0UL 3646 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN 0x1UL 3647 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT 0x2UL 3648 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN 0x3UL 3649 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL 3650 #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 3651 u8 pin2_state; 3652 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL 3653 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 0x1UL 3654 #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED 3655 u8 pin2_usage; 3656 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE 0x0UL 3657 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN 0x1UL 3658 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT 0x2UL 3659 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN 0x3UL 3660 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL 3661 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3662 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3663 #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3664 u8 pin3_state; 3665 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL 3666 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 0x1UL 3667 #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED 3668 u8 pin3_usage; 3669 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE 0x0UL 3670 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN 0x1UL 3671 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT 0x2UL 3672 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN 0x3UL 3673 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL 3674 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_PRIMARY_CLOCK_OUT 0x5UL 3675 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 0x6UL 3676 #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNCE_SECONDARY_CLOCK_OUT 3677 u8 unused_0[4]; 3678}; 3679 3680/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */ 3681struct hwrm_func_ptp_pin_cfg_output { 3682 __le16 error_code; 3683 __le16 req_type; 3684 __le16 seq_id; 3685 __le16 resp_len; 3686 u8 unused_0[7]; 3687 u8 valid; 3688}; 3689 3690/* hwrm_func_ptp_cfg_input (size:384b/48B) */ 3691struct hwrm_func_ptp_cfg_input { 3692 __le16 req_type; 3693 __le16 cmpl_ring; 3694 __le16 seq_id; 3695 __le16 target_id; 3696 __le64 resp_addr; 3697 __le16 enables; 3698 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT 0x1UL 3699 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE 0x2UL 3700 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE 0x4UL 3701 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD 0x8UL 3702 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP 0x10UL 3703 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE 0x20UL 3704 #define FUNC_PTP_CFG_REQ_ENABLES_PTP_SET_TIME 0x40UL 3705 u8 ptp_pps_event; 3706 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL 0x1UL 3707 #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL 0x2UL 3708 u8 ptp_freq_adj_dll_source; 3709 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE 0x0UL 3710 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0 0x1UL 3711 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1 0x2UL 3712 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2 0x3UL 3713 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3 0x4UL 3714 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0 0x5UL 3715 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1 0x6UL 3716 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2 0x7UL 3717 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3 0x8UL 3718 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL 3719 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 3720 u8 ptp_freq_adj_dll_phase; 3721 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL 3722 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K 0x1UL 3723 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K 0x2UL 3724 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M 0x3UL 3725 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 0x4UL 3726 #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_25M 3727 u8 unused_0[3]; 3728 __le32 ptp_freq_adj_ext_period; 3729 __le32 ptp_freq_adj_ext_up; 3730 __le32 ptp_freq_adj_ext_phase_lower; 3731 __le32 ptp_freq_adj_ext_phase_upper; 3732 __le64 ptp_set_time; 3733}; 3734 3735/* hwrm_func_ptp_cfg_output (size:128b/16B) */ 3736struct hwrm_func_ptp_cfg_output { 3737 __le16 error_code; 3738 __le16 req_type; 3739 __le16 seq_id; 3740 __le16 resp_len; 3741 u8 unused_0[7]; 3742 u8 valid; 3743}; 3744 3745/* hwrm_func_ptp_ts_query_input (size:192b/24B) */ 3746struct hwrm_func_ptp_ts_query_input { 3747 __le16 req_type; 3748 __le16 cmpl_ring; 3749 __le16 seq_id; 3750 __le16 target_id; 3751 __le64 resp_addr; 3752 __le32 flags; 3753 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME 0x1UL 3754 #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME 0x2UL 3755 u8 unused_0[4]; 3756}; 3757 3758/* hwrm_func_ptp_ts_query_output (size:320b/40B) */ 3759struct hwrm_func_ptp_ts_query_output { 3760 __le16 error_code; 3761 __le16 req_type; 3762 __le16 seq_id; 3763 __le16 resp_len; 3764 __le64 pps_event_ts; 3765 __le64 ptm_local_ts; 3766 __le64 ptm_system_ts; 3767 __le32 ptm_link_delay; 3768 u8 unused_0[3]; 3769 u8 valid; 3770}; 3771 3772/* hwrm_func_ptp_ext_cfg_input (size:256b/32B) */ 3773struct hwrm_func_ptp_ext_cfg_input { 3774 __le16 req_type; 3775 __le16 cmpl_ring; 3776 __le16 seq_id; 3777 __le16 target_id; 3778 __le64 resp_addr; 3779 __le16 enables; 3780 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_MASTER_FID 0x1UL 3781 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_FID 0x2UL 3782 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_PHC_SEC_MODE 0x4UL 3783 #define FUNC_PTP_EXT_CFG_REQ_ENABLES_FAILOVER_TIMER 0x8UL 3784 __le16 phc_master_fid; 3785 __le16 phc_sec_fid; 3786 u8 phc_sec_mode; 3787 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_SWITCH 0x0UL 3788 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_ALL 0x1UL 3789 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 0x2UL 3790 #define FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_LAST FUNC_PTP_EXT_CFG_REQ_PHC_SEC_MODE_PF_ONLY 3791 u8 unused_0; 3792 __le32 failover_timer; 3793 u8 unused_1[4]; 3794}; 3795 3796/* hwrm_func_ptp_ext_cfg_output (size:128b/16B) */ 3797struct hwrm_func_ptp_ext_cfg_output { 3798 __le16 error_code; 3799 __le16 req_type; 3800 __le16 seq_id; 3801 __le16 resp_len; 3802 u8 unused_0[7]; 3803 u8 valid; 3804}; 3805 3806/* hwrm_func_ptp_ext_qcfg_input (size:192b/24B) */ 3807struct hwrm_func_ptp_ext_qcfg_input { 3808 __le16 req_type; 3809 __le16 cmpl_ring; 3810 __le16 seq_id; 3811 __le16 target_id; 3812 __le64 resp_addr; 3813 u8 unused_0[8]; 3814}; 3815 3816/* hwrm_func_ptp_ext_qcfg_output (size:256b/32B) */ 3817struct hwrm_func_ptp_ext_qcfg_output { 3818 __le16 error_code; 3819 __le16 req_type; 3820 __le16 seq_id; 3821 __le16 resp_len; 3822 __le16 phc_master_fid; 3823 __le16 phc_sec_fid; 3824 __le16 phc_active_fid0; 3825 __le16 phc_active_fid1; 3826 __le32 last_failover_event; 3827 __le16 from_fid; 3828 __le16 to_fid; 3829 u8 unused_0[7]; 3830 u8 valid; 3831}; 3832 3833/* hwrm_func_backing_store_cfg_v2_input (size:512b/64B) */ 3834struct hwrm_func_backing_store_cfg_v2_input { 3835 __le16 req_type; 3836 __le16 cmpl_ring; 3837 __le16 seq_id; 3838 __le16 target_id; 3839 __le64 resp_addr; 3840 __le16 type; 3841 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_QP 0x0UL 3842 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ 0x1UL 3843 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ 0x2UL 3844 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_VNIC 0x3UL 3845 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_STAT 0x4UL 3846 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3847 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3848 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV 0xeUL 3849 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM 0xfUL 3850 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK 0x13UL 3851 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK 0x14UL 3852 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3853 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3854 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3855 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3856 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3857 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3858 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_XID_PARTITION 0x1dUL 3859 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3860 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3861 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3862 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3863 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3864 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3865 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3866 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3867 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3868 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3869 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3870 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3871 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3872 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3873 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 0xffffUL 3874 #define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_INVALID 3875 __le16 instance; 3876 __le32 flags; 3877 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_PREBOOT_MODE 0x1UL 3878 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_CFG_ALL_DONE 0x2UL 3879 #define FUNC_BACKING_STORE_CFG_V2_REQ_FLAGS_BS_EXTEND 0x4UL 3880 __le64 page_dir; 3881 __le32 num_entries; 3882 __le16 entry_size; 3883 u8 page_size_pbl_level; 3884 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_MASK 0xfUL 3885 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_SFT 0 3886 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_0 0x0UL 3887 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_1 0x1UL 3888 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 0x2UL 3889 #define FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PBL_LEVEL_LVL_2 3890 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_MASK 0xf0UL 3891 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_SFT 4 3892 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_4K (0x0UL << 4) 3893 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8K (0x1UL << 4) 3894 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_64K (0x2UL << 4) 3895 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_2M (0x3UL << 4) 3896 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_8M (0x4UL << 4) 3897 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G (0x5UL << 4) 3898 #define FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_LAST FUNC_BACKING_STORE_CFG_V2_REQ_PAGE_SIZE_PG_1G 3899 u8 subtype_valid_cnt; 3900 __le32 split_entry_0; 3901 __le32 split_entry_1; 3902 __le32 split_entry_2; 3903 __le32 split_entry_3; 3904 __le32 enables; 3905 #define FUNC_BACKING_STORE_CFG_V2_REQ_ENABLES_NEXT_BS_OFFSET 0x1UL 3906 __le32 next_bs_offset; 3907}; 3908 3909/* hwrm_func_backing_store_cfg_v2_output (size:128b/16B) */ 3910struct hwrm_func_backing_store_cfg_v2_output { 3911 __le16 error_code; 3912 __le16 req_type; 3913 __le16 seq_id; 3914 __le16 resp_len; 3915 u8 rsvd0[7]; 3916 u8 valid; 3917}; 3918 3919/* hwrm_func_backing_store_qcfg_v2_input (size:192b/24B) */ 3920struct hwrm_func_backing_store_qcfg_v2_input { 3921 __le16 req_type; 3922 __le16 cmpl_ring; 3923 __le16 seq_id; 3924 __le16 target_id; 3925 __le64 resp_addr; 3926 __le16 type; 3927 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_QP 0x0UL 3928 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ 0x1UL 3929 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ 0x2UL 3930 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_VNIC 0x3UL 3931 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_STAT 0x4UL 3932 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SP_TQM_RING 0x5UL 3933 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_FP_TQM_RING 0x6UL 3934 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MRAV 0xeUL 3935 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TIM 0xfUL 3936 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TX_CK 0x13UL 3937 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RX_CK 0x14UL 3938 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_MP_TQM_RING 0x15UL 3939 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 3940 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 3941 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 3942 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 3943 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 3944 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_XID_PARTITION_TABLE 0x1dUL 3945 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT_TRACE 0x1eUL 3946 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 3947 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT_TRACE 0x20UL 3948 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CRT2_TRACE 0x21UL 3949 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 3950 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 3951 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 3952 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 3953 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA0_TRACE 0x26UL 3954 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA1_TRACE 0x27UL 3955 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_CA2_TRACE 0x28UL 3956 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 3957 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 3958 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 3959 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 0xffffUL 3960 #define FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_REQ_TYPE_INVALID 3961 __le16 instance; 3962 u8 rsvd[4]; 3963}; 3964 3965/* hwrm_func_backing_store_qcfg_v2_output (size:448b/56B) */ 3966struct hwrm_func_backing_store_qcfg_v2_output { 3967 __le16 error_code; 3968 __le16 req_type; 3969 __le16 seq_id; 3970 __le16 resp_len; 3971 __le16 type; 3972 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_QP 0x0UL 3973 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRQ 0x1UL 3974 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CQ 0x2UL 3975 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_VNIC 0x3UL 3976 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_STAT 0x4UL 3977 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SP_TQM_RING 0x5UL 3978 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING 0x6UL 3979 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV 0xeUL 3980 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM 0xfUL 3981 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK 0x13UL 3982 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK 0x14UL 3983 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING 0x15UL 3984 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 3985 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION 0x1dUL 3986 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT_TRACE 0x1eUL 3987 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 3988 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT_TRACE 0x20UL 3989 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CRT2_TRACE 0x21UL 3990 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 3991 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 3992 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 3993 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 3994 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA0_TRACE 0x26UL 3995 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA1_TRACE 0x27UL 3996 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_CA2_TRACE 0x28UL 3997 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 3998 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_ERR_QPC_TRACE 0x2aUL 3999 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 0xffffUL 4000 #define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_INVALID 4001 __le16 instance; 4002 __le32 flags; 4003 __le64 page_dir; 4004 __le32 num_entries; 4005 u8 page_size_pbl_level; 4006 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_MASK 0xfUL 4007 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_SFT 0 4008 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_0 0x0UL 4009 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_1 0x1UL 4010 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 0x2UL 4011 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PBL_LEVEL_LVL_2 4012 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_MASK 0xf0UL 4013 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_SFT 4 4014 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_4K (0x0UL << 4) 4015 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8K (0x1UL << 4) 4016 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_64K (0x2UL << 4) 4017 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_2M (0x3UL << 4) 4018 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_8M (0x4UL << 4) 4019 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G (0x5UL << 4) 4020 #define FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_LAST FUNC_BACKING_STORE_QCFG_V2_RESP_PAGE_SIZE_PG_1G 4021 u8 subtype_valid_cnt; 4022 u8 rsvd[2]; 4023 __le32 split_entry_0; 4024 __le32 split_entry_1; 4025 __le32 split_entry_2; 4026 __le32 split_entry_3; 4027 u8 rsvd2[7]; 4028 u8 valid; 4029}; 4030 4031/* qpc_split_entries (size:128b/16B) */ 4032struct qpc_split_entries { 4033 __le32 qp_num_l2_entries; 4034 __le32 qp_num_qp1_entries; 4035 __le32 qp_num_fast_qpmd_entries; 4036 __le32 rsvd; 4037}; 4038 4039/* srq_split_entries (size:128b/16B) */ 4040struct srq_split_entries { 4041 __le32 srq_num_l2_entries; 4042 __le32 rsvd; 4043 __le32 rsvd2[2]; 4044}; 4045 4046/* cq_split_entries (size:128b/16B) */ 4047struct cq_split_entries { 4048 __le32 cq_num_l2_entries; 4049 __le32 rsvd; 4050 __le32 rsvd2[2]; 4051}; 4052 4053/* vnic_split_entries (size:128b/16B) */ 4054struct vnic_split_entries { 4055 __le32 vnic_num_vnic_entries; 4056 __le32 rsvd; 4057 __le32 rsvd2[2]; 4058}; 4059 4060/* mrav_split_entries (size:128b/16B) */ 4061struct mrav_split_entries { 4062 __le32 mrav_num_av_entries; 4063 __le32 rsvd; 4064 __le32 rsvd2[2]; 4065}; 4066 4067/* ts_split_entries (size:128b/16B) */ 4068struct ts_split_entries { 4069 __le32 region_num_entries; 4070 u8 tsid; 4071 u8 lkup_static_bkt_cnt_exp[2]; 4072 u8 locked; 4073 __le32 rsvd2[2]; 4074}; 4075 4076/* ck_split_entries (size:128b/16B) */ 4077struct ck_split_entries { 4078 __le32 num_quic_entries; 4079 __le32 rsvd; 4080 __le32 rsvd2[2]; 4081}; 4082 4083/* hwrm_func_backing_store_qcaps_v2_input (size:192b/24B) */ 4084struct hwrm_func_backing_store_qcaps_v2_input { 4085 __le16 req_type; 4086 __le16 cmpl_ring; 4087 __le16 seq_id; 4088 __le16 target_id; 4089 __le64 resp_addr; 4090 __le16 type; 4091 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_QP 0x0UL 4092 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ 0x1UL 4093 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ 0x2UL 4094 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_VNIC 0x3UL 4095 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_STAT 0x4UL 4096 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SP_TQM_RING 0x5UL 4097 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING 0x6UL 4098 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV 0xeUL 4099 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM 0xfUL 4100 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK 0x13UL 4101 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK 0x14UL 4102 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING 0x15UL 4103 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW 0x16UL 4104 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW 0x17UL 4105 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRQ_DB_SHADOW 0x18UL 4106 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CQ_DB_SHADOW 0x19UL 4107 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TBL_SCOPE 0x1cUL 4108 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_XID_PARTITION 0x1dUL 4109 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT_TRACE 0x1eUL 4110 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SRT2_TRACE 0x1fUL 4111 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT_TRACE 0x20UL 4112 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CRT2_TRACE 0x21UL 4113 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP0_TRACE 0x22UL 4114 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_L2_HWRM_TRACE 0x23UL 4115 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ROCE_HWRM_TRACE 0x24UL 4116 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TTX_PACING_TQM_RING 0x25UL 4117 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA0_TRACE 0x26UL 4118 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA1_TRACE 0x27UL 4119 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_CA2_TRACE 0x28UL 4120 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RIGP1_TRACE 0x29UL 4121 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4122 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_ERR_QPC_TRACE 0x2bUL 4123 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 0xffffUL 4124 #define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_INVALID 4125 u8 rsvd[6]; 4126}; 4127 4128/* hwrm_func_backing_store_qcaps_v2_output (size:448b/56B) */ 4129struct hwrm_func_backing_store_qcaps_v2_output { 4130 __le16 error_code; 4131 __le16 req_type; 4132 __le16 seq_id; 4133 __le16 resp_len; 4134 __le16 type; 4135 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_QP 0x0UL 4136 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ 0x1UL 4137 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ 0x2UL 4138 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_VNIC 0x3UL 4139 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_STAT 0x4UL 4140 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SP_TQM_RING 0x5UL 4141 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING 0x6UL 4142 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV 0xeUL 4143 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM 0xfUL 4144 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK 0x13UL 4145 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK 0x14UL 4146 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING 0x15UL 4147 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW 0x16UL 4148 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW 0x17UL 4149 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRQ_DB_SHADOW 0x18UL 4150 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CQ_DB_SHADOW 0x19UL 4151 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TBL_SCOPE 0x1cUL 4152 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_XID_PARTITION 0x1dUL 4153 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT_TRACE 0x1eUL 4154 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SRT2_TRACE 0x1fUL 4155 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT_TRACE 0x20UL 4156 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CRT2_TRACE 0x21UL 4157 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP0_TRACE 0x22UL 4158 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_L2_HWRM_TRACE 0x23UL 4159 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ROCE_HWRM_TRACE 0x24UL 4160 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TTX_PACING_TQM_RING 0x25UL 4161 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA0_TRACE 0x26UL 4162 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA1_TRACE 0x27UL 4163 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_CA2_TRACE 0x28UL 4164 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RIGP1_TRACE 0x29UL 4165 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_AFM_KONG_HWRM_TRACE 0x2aUL 4166 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_ERR_QPC_TRACE 0x2bUL 4167 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 0xffffUL 4168 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_LAST FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_INVALID 4169 __le16 entry_size; 4170 __le32 flags; 4171 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ENABLE_CTX_KIND_INIT 0x1UL 4172 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_TYPE_VALID 0x2UL 4173 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_DRIVER_MANAGED_MEMORY 0x4UL 4174 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_ROCE_QP_PSEUDO_STATIC_ALLOC 0x8UL 4175 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_DBG_TRACE 0x10UL 4176 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_FW_BIN_DBG_TRACE 0x20UL 4177 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_FLAGS_NEXT_BS_OFFSET 0x40UL 4178 __le32 instance_bit_map; 4179 u8 ctx_init_value; 4180 u8 ctx_init_offset; 4181 u8 entry_multiple; 4182 u8 rsvd; 4183 __le32 max_num_entries; 4184 __le32 min_num_entries; 4185 __le16 next_valid_type; 4186 u8 subtype_valid_cnt; 4187 u8 exact_cnt_bit_map; 4188 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_0_EXACT 0x1UL 4189 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_1_EXACT 0x2UL 4190 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_2_EXACT 0x4UL 4191 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_SPLIT_ENTRY_3_EXACT 0x8UL 4192 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_MASK 0xf0UL 4193 #define FUNC_BACKING_STORE_QCAPS_V2_RESP_EXACT_CNT_BIT_MAP_UNUSED_SFT 4 4194 __le32 split_entry_0; 4195 __le32 split_entry_1; 4196 __le32 split_entry_2; 4197 __le32 split_entry_3; 4198 __le16 max_instance_count; 4199 u8 rsvd3; 4200 u8 valid; 4201}; 4202 4203/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */ 4204struct hwrm_func_dbr_pacing_qcfg_input { 4205 __le16 req_type; 4206 __le16 cmpl_ring; 4207 __le16 seq_id; 4208 __le16 target_id; 4209 __le64 resp_addr; 4210}; 4211 4212/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */ 4213struct hwrm_func_dbr_pacing_qcfg_output { 4214 __le16 error_code; 4215 __le16 req_type; 4216 __le16 seq_id; 4217 __le16 resp_len; 4218 u8 flags; 4219 #define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED 0x1UL 4220 u8 unused_0[7]; 4221 __le32 dbr_stat_db_fifo_reg; 4222 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK 0x3UL 4223 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT 0 4224 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4225 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC 0x1UL 4226 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0 0x2UL 4227 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 0x3UL 4228 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1 4229 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK 0xfffffffcUL 4230 #define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT 2 4231 __le32 dbr_stat_db_fifo_reg_watermark_mask; 4232 u8 dbr_stat_db_fifo_reg_watermark_shift; 4233 u8 unused_1[3]; 4234 __le32 dbr_stat_db_fifo_reg_fifo_room_mask; 4235 u8 dbr_stat_db_fifo_reg_fifo_room_shift; 4236 u8 unused_2[3]; 4237 __le32 dbr_throttling_aeq_arm_reg; 4238 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK 0x3UL 4239 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT 0 4240 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG 0x0UL 4241 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC 0x1UL 4242 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0 0x2UL 4243 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 0x3UL 4244 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1 4245 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK 0xfffffffcUL 4246 #define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT 2 4247 u8 dbr_throttling_aeq_arm_reg_val; 4248 u8 unused_3[3]; 4249 __le32 dbr_stat_db_max_fifo_depth; 4250 __le32 primary_nq_id; 4251 __le32 pacing_threshold; 4252 u8 unused_4[7]; 4253 u8 valid; 4254}; 4255 4256/* hwrm_func_drv_if_change_input (size:192b/24B) */ 4257struct hwrm_func_drv_if_change_input { 4258 __le16 req_type; 4259 __le16 cmpl_ring; 4260 __le16 seq_id; 4261 __le16 target_id; 4262 __le64 resp_addr; 4263 __le32 flags; 4264 #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP 0x1UL 4265 __le32 unused; 4266}; 4267 4268/* hwrm_func_drv_if_change_output (size:128b/16B) */ 4269struct hwrm_func_drv_if_change_output { 4270 __le16 error_code; 4271 __le16 req_type; 4272 __le16 seq_id; 4273 __le16 resp_len; 4274 __le32 flags; 4275 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE 0x1UL 4276 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE 0x2UL 4277 #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_CAPS_CHANGE 0x4UL 4278 u8 unused_0[3]; 4279 u8 valid; 4280}; 4281 4282/* hwrm_port_phy_cfg_input (size:512b/64B) */ 4283struct hwrm_port_phy_cfg_input { 4284 __le16 req_type; 4285 __le16 cmpl_ring; 4286 __le16 seq_id; 4287 __le16 target_id; 4288 __le64 resp_addr; 4289 __le32 flags; 4290 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 4291 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 4292 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 4293 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 4294 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 4295 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 4296 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 4297 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 4298 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 4299 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 4300 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 4301 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 4302 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 4303 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 4304 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 4305 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE 0x8000UL 4306 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE 0x10000UL 4307 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE 0x20000UL 4308 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE 0x40000UL 4309 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE 0x80000UL 4310 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE 0x100000UL 4311 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE 0x200000UL 4312 #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE 0x400000UL 4313 #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_ENABLE 0x800000UL 4314 #define PORT_PHY_CFG_REQ_FLAGS_LINK_TRAINING_DISABLE 0x1000000UL 4315 #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_ENABLE 0x2000000UL 4316 #define PORT_PHY_CFG_REQ_FLAGS_PRECODING_DISABLE 0x4000000UL 4317 __le32 enables; 4318 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 4319 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 4320 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 4321 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 4322 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 4323 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 4324 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 4325 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 4326 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 4327 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 4328 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 4329 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED 0x800UL 4330 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK 0x1000UL 4331 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 0x2000UL 4332 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 0x4000UL 4333 __le16 port_id; 4334 __le16 force_link_speed; 4335 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 4336 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 4337 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 4338 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 4339 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 4340 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 4341 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 4342 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 4343 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 4344 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 4345 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 4346 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 4347 u8 auto_mode; 4348 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 4349 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 4350 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 4351 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 4352 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 4353 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 4354 u8 auto_duplex; 4355 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 4356 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 4357 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 4358 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 4359 u8 auto_pause; 4360 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 4361 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 4362 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4363 u8 mgmt_flag; 4364 #define PORT_PHY_CFG_REQ_MGMT_FLAG_LINK_RELEASE 0x1UL 4365 #define PORT_PHY_CFG_REQ_MGMT_FLAG_MGMT_VALID 0x80UL 4366 __le16 auto_link_speed; 4367 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 4368 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 4369 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 4370 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 4371 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 4372 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 4373 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 4374 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 4375 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 4376 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 4377 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 4378 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 4379 __le16 auto_link_speed_mask; 4380 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4381 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4382 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4383 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4384 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4385 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4386 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4387 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4388 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4389 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4390 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4391 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4392 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4393 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4394 u8 wirespeed; 4395 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 4396 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 4397 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 4398 u8 lpbk; 4399 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 4400 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 4401 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 4402 #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL 4403 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_EXTERNAL 4404 u8 force_pause; 4405 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 4406 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 4407 u8 unused_1; 4408 __le32 preemphasis; 4409 __le16 eee_link_speed_mask; 4410 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4411 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 4412 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4413 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 4414 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4415 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4416 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 4417 __le16 force_pam4_link_speed; 4418 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4419 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4420 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4421 #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 4422 __le32 tx_lpi_timer; 4423 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 4424 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 4425 __le16 auto_link_pam4_speed_mask; 4426 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G 0x1UL 4427 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G 0x2UL 4428 #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G 0x4UL 4429 __le16 force_link_speeds2; 4430 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_1GB 0xaUL 4431 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_10GB 0x64UL 4432 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4433 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_40GB 0x190UL 4434 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4435 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4436 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4437 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4438 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4439 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4440 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4441 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4442 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4443 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4444 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4445 __le16 auto_link_speeds2_mask; 4446 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB 0x1UL 4447 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB 0x2UL 4448 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_25GB 0x4UL 4449 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_40GB 0x8UL 4450 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB 0x10UL 4451 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB 0x20UL 4452 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_50GB_PAM4_56 0x40UL 4453 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_56 0x80UL 4454 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_56 0x100UL 4455 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_56 0x200UL 4456 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112 0x400UL 4457 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112 0x800UL 4458 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112 0x1000UL 4459 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112 0x2000UL 4460 u8 unused_2[6]; 4461}; 4462 4463/* hwrm_port_phy_cfg_output (size:128b/16B) */ 4464struct hwrm_port_phy_cfg_output { 4465 __le16 error_code; 4466 __le16 req_type; 4467 __le16 seq_id; 4468 __le16 resp_len; 4469 u8 unused_0[7]; 4470 u8 valid; 4471}; 4472 4473/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 4474struct hwrm_port_phy_cfg_cmd_err { 4475 u8 code; 4476 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 4477 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 4478 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 4479 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 4480 u8 unused_0[7]; 4481}; 4482 4483/* hwrm_port_phy_qcfg_input (size:192b/24B) */ 4484struct hwrm_port_phy_qcfg_input { 4485 __le16 req_type; 4486 __le16 cmpl_ring; 4487 __le16 seq_id; 4488 __le16 target_id; 4489 __le64 resp_addr; 4490 __le16 port_id; 4491 u8 unused_0[6]; 4492}; 4493 4494/* hwrm_port_phy_qcfg_output (size:832b/104B) */ 4495struct hwrm_port_phy_qcfg_output { 4496 __le16 error_code; 4497 __le16 req_type; 4498 __le16 seq_id; 4499 __le16 resp_len; 4500 u8 link; 4501 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 4502 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 4503 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 4504 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 4505 u8 active_fec_signal_mode; 4506 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK 0xfUL 4507 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT 0 4508 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 0x0UL 4509 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 0x1UL 4510 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 0x2UL 4511 #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 4512 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK 0xf0UL 4513 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT 4 4514 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE (0x0UL << 4) 4515 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE (0x1UL << 4) 4516 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE (0x2UL << 4) 4517 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE (0x3UL << 4) 4518 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE (0x4UL << 4) 4519 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE (0x5UL << 4) 4520 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE (0x6UL << 4) 4521 #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE 4522 __le16 link_speed; 4523 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 4524 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 4525 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 4526 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 4527 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 4528 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 4529 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 4530 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 4531 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 4532 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 4533 #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL 4534 #define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL 4535 #define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL 4536 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 4537 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 4538 u8 duplex_cfg; 4539 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 4540 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 4541 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 4542 u8 pause; 4543 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 4544 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 4545 __le16 support_speeds; 4546 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 4547 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 4548 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 4549 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 4550 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 4551 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 4552 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 4553 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 4554 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 4555 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 4556 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 4557 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 4558 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 4559 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 4560 __le16 force_link_speed; 4561 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 4562 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 4563 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 4564 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 4565 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 4566 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 4567 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 4568 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 4569 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 4570 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 4571 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 4572 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 4573 u8 auto_mode; 4574 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 4575 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 4576 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 4577 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 4578 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 4579 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 4580 u8 auto_pause; 4581 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 4582 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 4583 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 4584 __le16 auto_link_speed; 4585 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 4586 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 4587 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 4588 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 4589 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 4590 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 4591 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 4592 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 4593 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 4594 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 4595 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 4596 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 4597 __le16 auto_link_speed_mask; 4598 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 4599 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 4600 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 4601 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 4602 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 4603 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 4604 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 4605 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 4606 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 4607 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 4608 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 4609 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 4610 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 4611 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 4612 u8 wirespeed; 4613 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 4614 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 4615 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 4616 u8 lpbk; 4617 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 4618 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 4619 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 4620 #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL 4621 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 4622 u8 force_pause; 4623 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 4624 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 4625 u8 module_status; 4626 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 4627 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 4628 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 4629 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 4630 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 4631 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT 0x5UL 4632 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_OVERHEATED 0x6UL 4633 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 4634 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 4635 __le32 preemphasis; 4636 u8 phy_maj; 4637 u8 phy_min; 4638 u8 phy_bld; 4639 u8 phy_type; 4640 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 4641 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 4642 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 4643 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 4644 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 4645 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 4646 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 4647 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 4648 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 4649 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 4650 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 4651 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 4652 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 4653 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 4654 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 4655 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 4656 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 4657 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 4658 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 4659 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 4660 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 4661 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 4662 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 4663 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 4664 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 4665 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 4666 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 4667 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 4668 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR4 0x1cUL 4669 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR4 0x1dUL 4670 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR4 0x1eUL 4671 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER4 0x1fUL 4672 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASECR 0x20UL 4673 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASESR 0x21UL 4674 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASELR 0x22UL 4675 #define PORT_PHY_QCFG_RESP_PHY_TYPE_50G_BASEER 0x23UL 4676 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR2 0x24UL 4677 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR2 0x25UL 4678 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR2 0x26UL 4679 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER2 0x27UL 4680 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR 0x28UL 4681 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR 0x29UL 4682 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR 0x2aUL 4683 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER 0x2bUL 4684 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASECR2 0x2cUL 4685 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASESR2 0x2dUL 4686 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASELR2 0x2eUL 4687 #define PORT_PHY_QCFG_RESP_PHY_TYPE_200G_BASEER2 0x2fUL 4688 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR8 0x30UL 4689 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR8 0x31UL 4690 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR8 0x32UL 4691 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER8 0x33UL 4692 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASECR4 0x34UL 4693 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4 0x35UL 4694 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4 0x36UL 4695 #define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4 0x37UL 4696 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8 0x38UL 4697 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8 0x39UL 4698 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8 0x3aUL 4699 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8 0x3bUL 4700 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8 0x3cUL 4701 #define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 0x3dUL 4702 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8 4703 u8 media_type; 4704 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 4705 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 4706 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 4707 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 4708 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 0x4UL 4709 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_BACKPLANE 4710 u8 xcvr_pkg_type; 4711 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 4712 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 4713 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 4714 u8 eee_config_phy_addr; 4715 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 4716 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 4717 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 4718 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 4719 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 4720 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 4721 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 4722 u8 parallel_detect; 4723 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 4724 __le16 link_partner_adv_speeds; 4725 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 4726 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 4727 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 4728 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 4729 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 4730 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 4731 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 4732 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 4733 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 4734 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 4735 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 4736 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 4737 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 4738 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 4739 u8 link_partner_adv_auto_mode; 4740 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 4741 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 4742 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 4743 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 4744 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 4745 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 4746 u8 link_partner_adv_pause; 4747 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 4748 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 4749 __le16 adv_eee_link_speed_mask; 4750 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4751 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4752 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4753 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4754 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4755 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4756 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4757 __le16 link_partner_adv_eee_link_speed_mask; 4758 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 4759 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 4760 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 4761 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 4762 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 4763 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 4764 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 4765 __le32 xcvr_identifier_type_tx_lpi_timer; 4766 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 4767 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 4768 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 4769 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 4770 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 4771 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 4772 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 4773 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 4774 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 4775 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPDD (0x18UL << 24) 4776 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP112 (0x1eUL << 24) 4777 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFPDD (0x1fUL << 24) 4778 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP (0x20UL << 24) 4779 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_CSFP 4780 __le16 fec_cfg; 4781 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 4782 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 4783 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 4784 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 4785 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 4786 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 4787 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 4788 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_SUPPORTED 0x80UL 4789 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED 0x100UL 4790 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_SUPPORTED 0x200UL 4791 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED 0x400UL 4792 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED 0x800UL 4793 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED 0x1000UL 4794 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED 0x2000UL 4795 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED 0x4000UL 4796 u8 duplex_state; 4797 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 4798 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 4799 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 4800 u8 option_flags; 4801 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 4802 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 4803 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SPEEDS2_SUPPORTED 0x4UL 4804 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_LINK_TRAINING 0x8UL 4805 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_PRECODING 0x10UL 4806 char phy_vendor_name[16]; 4807 char phy_vendor_partnumber[16]; 4808 __le16 support_pam4_speeds; 4809 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G 0x1UL 4810 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G 0x2UL 4811 #define PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G 0x4UL 4812 __le16 force_pam4_link_speed; 4813 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_50GB 0x1f4UL 4814 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL 4815 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL 4816 #define PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_PAM4_LINK_SPEED_200GB 4817 __le16 auto_pam4_link_speed_mask; 4818 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_50G 0x1UL 4819 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_100G 0x2UL 4820 #define PORT_PHY_QCFG_RESP_AUTO_PAM4_LINK_SPEED_MASK_200G 0x4UL 4821 u8 link_partner_pam4_adv_speeds; 4822 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_50GB 0x1UL 4823 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_100GB 0x2UL 4824 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_PAM4_ADV_SPEEDS_200GB 0x4UL 4825 u8 link_down_reason; 4826 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_RF 0x1UL 4827 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_OTP_SPEED_VIOLATION 0x2UL 4828 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_CABLE_REMOVED 0x4UL 4829 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_MODULE_FAULT 0x8UL 4830 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_BMC_REQUEST 0x10UL 4831 #define PORT_PHY_QCFG_RESP_LINK_DOWN_REASON_TX_LASER_DISABLED 0x20UL 4832 __le16 support_speeds2; 4833 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_1GB 0x1UL 4834 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_10GB 0x2UL 4835 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_25GB 0x4UL 4836 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_40GB 0x8UL 4837 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 0x10UL 4838 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 0x20UL 4839 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 0x40UL 4840 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 0x80UL 4841 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 0x100UL 4842 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 0x200UL 4843 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 0x400UL 4844 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 0x800UL 4845 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 0x1000UL 4846 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 0x2000UL 4847 __le16 force_link_speeds2; 4848 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_1GB 0xaUL 4849 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_10GB 0x64UL 4850 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_25GB 0xfaUL 4851 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_40GB 0x190UL 4852 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB 0x1f4UL 4853 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB 0x3e8UL 4854 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_50GB_PAM4_56 0x1f5UL 4855 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_56 0x3e9UL 4856 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_56 0x7d1UL 4857 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_56 0xfa1UL 4858 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL 4859 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL 4860 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL 4861 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL 4862 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEEDS2_800GB_PAM4_112 4863 __le16 auto_link_speeds2; 4864 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_1GB 0x1UL 4865 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_10GB 0x2UL 4866 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_25GB 0x4UL 4867 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_40GB 0x8UL 4868 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB 0x10UL 4869 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB 0x20UL 4870 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_50GB_PAM4_56 0x40UL 4871 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_56 0x80UL 4872 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_56 0x100UL 4873 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_56 0x200UL 4874 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_100GB_PAM4_112 0x400UL 4875 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_200GB_PAM4_112 0x800UL 4876 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_400GB_PAM4_112 0x1000UL 4877 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEEDS2_800GB_PAM4_112 0x2000UL 4878 u8 active_lanes; 4879 u8 valid; 4880}; 4881 4882/* hwrm_port_mac_cfg_input (size:448b/56B) */ 4883struct hwrm_port_mac_cfg_input { 4884 __le16 req_type; 4885 __le16 cmpl_ring; 4886 __le16 seq_id; 4887 __le16 target_id; 4888 __le64 resp_addr; 4889 __le32 flags; 4890 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 4891 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 4892 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 4893 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 4894 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 4895 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 4896 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 4897 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 4898 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 4899 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 4900 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 4901 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 4902 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 4903 #define PORT_MAC_CFG_REQ_FLAGS_PTP_ONE_STEP_TX_TS 0x2000UL 4904 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_ENABLE 0x4000UL 4905 #define PORT_MAC_CFG_REQ_FLAGS_ALL_RX_TS_CAPTURE_DISABLE 0x8000UL 4906 __le32 enables; 4907 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 4908 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 4909 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 4910 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 4911 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 4912 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 4913 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 4914 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 4915 #define PORT_MAC_CFG_REQ_ENABLES_PTP_FREQ_ADJ_PPB 0x200UL 4916 #define PORT_MAC_CFG_REQ_ENABLES_PTP_ADJ_PHASE 0x400UL 4917 #define PORT_MAC_CFG_REQ_ENABLES_PTP_LOAD_CONTROL 0x800UL 4918 __le16 port_id; 4919 u8 ipg; 4920 u8 lpbk; 4921 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 4922 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 4923 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 4924 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 4925 u8 vlan_pri2cos_map_pri; 4926 u8 reserved1; 4927 u8 tunnel_pri2cos_map_pri; 4928 u8 dscp2pri_map_pri; 4929 __le16 rx_ts_capture_ptp_msg_type; 4930 __le16 tx_ts_capture_ptp_msg_type; 4931 u8 cos_field_cfg; 4932 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 4933 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 4934 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 4935 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 4936 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 4937 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 4938 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 4939 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 4940 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 4941 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 4942 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 4943 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 4944 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 4945 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 4946 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 4947 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 4948 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 4949 u8 unused_0[3]; 4950 __le32 ptp_freq_adj_ppb; 4951 u8 unused_1[3]; 4952 u8 ptp_load_control; 4953 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_NONE 0x0UL 4954 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_IMMEDIATE 0x1UL 4955 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 0x2UL 4956 #define PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_LAST PORT_MAC_CFG_REQ_PTP_LOAD_CONTROL_PPS_EVENT 4957 __le64 ptp_adj_phase; 4958}; 4959 4960/* hwrm_port_mac_cfg_output (size:128b/16B) */ 4961struct hwrm_port_mac_cfg_output { 4962 __le16 error_code; 4963 __le16 req_type; 4964 __le16 seq_id; 4965 __le16 resp_len; 4966 __le16 mru; 4967 __le16 mtu; 4968 u8 ipg; 4969 u8 lpbk; 4970 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 4971 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 4972 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 4973 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 4974 u8 unused_0; 4975 u8 valid; 4976}; 4977 4978/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 4979struct hwrm_port_mac_ptp_qcfg_input { 4980 __le16 req_type; 4981 __le16 cmpl_ring; 4982 __le16 seq_id; 4983 __le16 target_id; 4984 __le64 resp_addr; 4985 __le16 port_id; 4986 u8 unused_0[6]; 4987}; 4988 4989/* hwrm_port_mac_ptp_qcfg_output (size:704b/88B) */ 4990struct hwrm_port_mac_ptp_qcfg_output { 4991 __le16 error_code; 4992 __le16 req_type; 4993 __le16 seq_id; 4994 __le16 resp_len; 4995 u8 flags; 4996 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 4997 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_ONE_STEP_TX_TS 0x4UL 4998 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x8UL 4999 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK 0x10UL 5000 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_RTC_CONFIGURED 0x20UL 5001 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME 0x40UL 5002 u8 unused_0[3]; 5003 __le32 rx_ts_reg_off_lower; 5004 __le32 rx_ts_reg_off_upper; 5005 __le32 rx_ts_reg_off_seq_id; 5006 __le32 rx_ts_reg_off_src_id_0; 5007 __le32 rx_ts_reg_off_src_id_1; 5008 __le32 rx_ts_reg_off_src_id_2; 5009 __le32 rx_ts_reg_off_domain_id; 5010 __le32 rx_ts_reg_off_fifo; 5011 __le32 rx_ts_reg_off_fifo_adv; 5012 __le32 rx_ts_reg_off_granularity; 5013 __le32 tx_ts_reg_off_lower; 5014 __le32 tx_ts_reg_off_upper; 5015 __le32 tx_ts_reg_off_seq_id; 5016 __le32 tx_ts_reg_off_fifo; 5017 __le32 tx_ts_reg_off_granularity; 5018 __le32 ts_ref_clock_reg_lower; 5019 __le32 ts_ref_clock_reg_upper; 5020 u8 unused_1[7]; 5021 u8 valid; 5022}; 5023 5024/* tx_port_stats (size:3264b/408B) */ 5025struct tx_port_stats { 5026 __le64 tx_64b_frames; 5027 __le64 tx_65b_127b_frames; 5028 __le64 tx_128b_255b_frames; 5029 __le64 tx_256b_511b_frames; 5030 __le64 tx_512b_1023b_frames; 5031 __le64 tx_1024b_1518b_frames; 5032 __le64 tx_good_vlan_frames; 5033 __le64 tx_1519b_2047b_frames; 5034 __le64 tx_2048b_4095b_frames; 5035 __le64 tx_4096b_9216b_frames; 5036 __le64 tx_9217b_16383b_frames; 5037 __le64 tx_good_frames; 5038 __le64 tx_total_frames; 5039 __le64 tx_ucast_frames; 5040 __le64 tx_mcast_frames; 5041 __le64 tx_bcast_frames; 5042 __le64 tx_pause_frames; 5043 __le64 tx_pfc_frames; 5044 __le64 tx_jabber_frames; 5045 __le64 tx_fcs_err_frames; 5046 __le64 tx_control_frames; 5047 __le64 tx_oversz_frames; 5048 __le64 tx_single_dfrl_frames; 5049 __le64 tx_multi_dfrl_frames; 5050 __le64 tx_single_coll_frames; 5051 __le64 tx_multi_coll_frames; 5052 __le64 tx_late_coll_frames; 5053 __le64 tx_excessive_coll_frames; 5054 __le64 tx_frag_frames; 5055 __le64 tx_err; 5056 __le64 tx_tagged_frames; 5057 __le64 tx_dbl_tagged_frames; 5058 __le64 tx_runt_frames; 5059 __le64 tx_fifo_underruns; 5060 __le64 tx_pfc_ena_frames_pri0; 5061 __le64 tx_pfc_ena_frames_pri1; 5062 __le64 tx_pfc_ena_frames_pri2; 5063 __le64 tx_pfc_ena_frames_pri3; 5064 __le64 tx_pfc_ena_frames_pri4; 5065 __le64 tx_pfc_ena_frames_pri5; 5066 __le64 tx_pfc_ena_frames_pri6; 5067 __le64 tx_pfc_ena_frames_pri7; 5068 __le64 tx_eee_lpi_events; 5069 __le64 tx_eee_lpi_duration; 5070 __le64 tx_llfc_logical_msgs; 5071 __le64 tx_hcfc_msgs; 5072 __le64 tx_total_collisions; 5073 __le64 tx_bytes; 5074 __le64 tx_xthol_frames; 5075 __le64 tx_stat_discard; 5076 __le64 tx_stat_error; 5077}; 5078 5079/* rx_port_stats (size:4224b/528B) */ 5080struct rx_port_stats { 5081 __le64 rx_64b_frames; 5082 __le64 rx_65b_127b_frames; 5083 __le64 rx_128b_255b_frames; 5084 __le64 rx_256b_511b_frames; 5085 __le64 rx_512b_1023b_frames; 5086 __le64 rx_1024b_1518b_frames; 5087 __le64 rx_good_vlan_frames; 5088 __le64 rx_1519b_2047b_frames; 5089 __le64 rx_2048b_4095b_frames; 5090 __le64 rx_4096b_9216b_frames; 5091 __le64 rx_9217b_16383b_frames; 5092 __le64 rx_total_frames; 5093 __le64 rx_ucast_frames; 5094 __le64 rx_mcast_frames; 5095 __le64 rx_bcast_frames; 5096 __le64 rx_fcs_err_frames; 5097 __le64 rx_ctrl_frames; 5098 __le64 rx_pause_frames; 5099 __le64 rx_pfc_frames; 5100 __le64 rx_unsupported_opcode_frames; 5101 __le64 rx_unsupported_da_pausepfc_frames; 5102 __le64 rx_wrong_sa_frames; 5103 __le64 rx_align_err_frames; 5104 __le64 rx_oor_len_frames; 5105 __le64 rx_code_err_frames; 5106 __le64 rx_false_carrier_frames; 5107 __le64 rx_ovrsz_frames; 5108 __le64 rx_jbr_frames; 5109 __le64 rx_mtu_err_frames; 5110 __le64 rx_match_crc_frames; 5111 __le64 rx_promiscuous_frames; 5112 __le64 rx_tagged_frames; 5113 __le64 rx_double_tagged_frames; 5114 __le64 rx_trunc_frames; 5115 __le64 rx_good_frames; 5116 __le64 rx_pfc_xon2xoff_frames_pri0; 5117 __le64 rx_pfc_xon2xoff_frames_pri1; 5118 __le64 rx_pfc_xon2xoff_frames_pri2; 5119 __le64 rx_pfc_xon2xoff_frames_pri3; 5120 __le64 rx_pfc_xon2xoff_frames_pri4; 5121 __le64 rx_pfc_xon2xoff_frames_pri5; 5122 __le64 rx_pfc_xon2xoff_frames_pri6; 5123 __le64 rx_pfc_xon2xoff_frames_pri7; 5124 __le64 rx_pfc_ena_frames_pri0; 5125 __le64 rx_pfc_ena_frames_pri1; 5126 __le64 rx_pfc_ena_frames_pri2; 5127 __le64 rx_pfc_ena_frames_pri3; 5128 __le64 rx_pfc_ena_frames_pri4; 5129 __le64 rx_pfc_ena_frames_pri5; 5130 __le64 rx_pfc_ena_frames_pri6; 5131 __le64 rx_pfc_ena_frames_pri7; 5132 __le64 rx_sch_crc_err_frames; 5133 __le64 rx_undrsz_frames; 5134 __le64 rx_frag_frames; 5135 __le64 rx_eee_lpi_events; 5136 __le64 rx_eee_lpi_duration; 5137 __le64 rx_llfc_physical_msgs; 5138 __le64 rx_llfc_logical_msgs; 5139 __le64 rx_llfc_msgs_with_crc_err; 5140 __le64 rx_hcfc_msgs; 5141 __le64 rx_hcfc_msgs_with_crc_err; 5142 __le64 rx_bytes; 5143 __le64 rx_runt_bytes; 5144 __le64 rx_runt_frames; 5145 __le64 rx_stat_discard; 5146 __le64 rx_stat_err; 5147}; 5148 5149/* hwrm_port_qstats_input (size:320b/40B) */ 5150struct hwrm_port_qstats_input { 5151 __le16 req_type; 5152 __le16 cmpl_ring; 5153 __le16 seq_id; 5154 __le16 target_id; 5155 __le64 resp_addr; 5156 __le16 port_id; 5157 u8 flags; 5158 #define PORT_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5159 u8 unused_0[5]; 5160 __le64 tx_stat_host_addr; 5161 __le64 rx_stat_host_addr; 5162}; 5163 5164/* hwrm_port_qstats_output (size:128b/16B) */ 5165struct hwrm_port_qstats_output { 5166 __le16 error_code; 5167 __le16 req_type; 5168 __le16 seq_id; 5169 __le16 resp_len; 5170 __le16 tx_stat_size; 5171 __le16 rx_stat_size; 5172 u8 flags; 5173 #define PORT_QSTATS_RESP_FLAGS_CLEARED 0x1UL 5174 u8 unused_0[2]; 5175 u8 valid; 5176}; 5177 5178/* tx_port_stats_ext (size:2048b/256B) */ 5179struct tx_port_stats_ext { 5180 __le64 tx_bytes_cos0; 5181 __le64 tx_bytes_cos1; 5182 __le64 tx_bytes_cos2; 5183 __le64 tx_bytes_cos3; 5184 __le64 tx_bytes_cos4; 5185 __le64 tx_bytes_cos5; 5186 __le64 tx_bytes_cos6; 5187 __le64 tx_bytes_cos7; 5188 __le64 tx_packets_cos0; 5189 __le64 tx_packets_cos1; 5190 __le64 tx_packets_cos2; 5191 __le64 tx_packets_cos3; 5192 __le64 tx_packets_cos4; 5193 __le64 tx_packets_cos5; 5194 __le64 tx_packets_cos6; 5195 __le64 tx_packets_cos7; 5196 __le64 pfc_pri0_tx_duration_us; 5197 __le64 pfc_pri0_tx_transitions; 5198 __le64 pfc_pri1_tx_duration_us; 5199 __le64 pfc_pri1_tx_transitions; 5200 __le64 pfc_pri2_tx_duration_us; 5201 __le64 pfc_pri2_tx_transitions; 5202 __le64 pfc_pri3_tx_duration_us; 5203 __le64 pfc_pri3_tx_transitions; 5204 __le64 pfc_pri4_tx_duration_us; 5205 __le64 pfc_pri4_tx_transitions; 5206 __le64 pfc_pri5_tx_duration_us; 5207 __le64 pfc_pri5_tx_transitions; 5208 __le64 pfc_pri6_tx_duration_us; 5209 __le64 pfc_pri6_tx_transitions; 5210 __le64 pfc_pri7_tx_duration_us; 5211 __le64 pfc_pri7_tx_transitions; 5212}; 5213 5214/* rx_port_stats_ext (size:3904b/488B) */ 5215struct rx_port_stats_ext { 5216 __le64 link_down_events; 5217 __le64 continuous_pause_events; 5218 __le64 resume_pause_events; 5219 __le64 continuous_roce_pause_events; 5220 __le64 resume_roce_pause_events; 5221 __le64 rx_bytes_cos0; 5222 __le64 rx_bytes_cos1; 5223 __le64 rx_bytes_cos2; 5224 __le64 rx_bytes_cos3; 5225 __le64 rx_bytes_cos4; 5226 __le64 rx_bytes_cos5; 5227 __le64 rx_bytes_cos6; 5228 __le64 rx_bytes_cos7; 5229 __le64 rx_packets_cos0; 5230 __le64 rx_packets_cos1; 5231 __le64 rx_packets_cos2; 5232 __le64 rx_packets_cos3; 5233 __le64 rx_packets_cos4; 5234 __le64 rx_packets_cos5; 5235 __le64 rx_packets_cos6; 5236 __le64 rx_packets_cos7; 5237 __le64 pfc_pri0_rx_duration_us; 5238 __le64 pfc_pri0_rx_transitions; 5239 __le64 pfc_pri1_rx_duration_us; 5240 __le64 pfc_pri1_rx_transitions; 5241 __le64 pfc_pri2_rx_duration_us; 5242 __le64 pfc_pri2_rx_transitions; 5243 __le64 pfc_pri3_rx_duration_us; 5244 __le64 pfc_pri3_rx_transitions; 5245 __le64 pfc_pri4_rx_duration_us; 5246 __le64 pfc_pri4_rx_transitions; 5247 __le64 pfc_pri5_rx_duration_us; 5248 __le64 pfc_pri5_rx_transitions; 5249 __le64 pfc_pri6_rx_duration_us; 5250 __le64 pfc_pri6_rx_transitions; 5251 __le64 pfc_pri7_rx_duration_us; 5252 __le64 pfc_pri7_rx_transitions; 5253 __le64 rx_bits; 5254 __le64 rx_buffer_passed_threshold; 5255 __le64 rx_pcs_symbol_err; 5256 __le64 rx_corrected_bits; 5257 __le64 rx_discard_bytes_cos0; 5258 __le64 rx_discard_bytes_cos1; 5259 __le64 rx_discard_bytes_cos2; 5260 __le64 rx_discard_bytes_cos3; 5261 __le64 rx_discard_bytes_cos4; 5262 __le64 rx_discard_bytes_cos5; 5263 __le64 rx_discard_bytes_cos6; 5264 __le64 rx_discard_bytes_cos7; 5265 __le64 rx_discard_packets_cos0; 5266 __le64 rx_discard_packets_cos1; 5267 __le64 rx_discard_packets_cos2; 5268 __le64 rx_discard_packets_cos3; 5269 __le64 rx_discard_packets_cos4; 5270 __le64 rx_discard_packets_cos5; 5271 __le64 rx_discard_packets_cos6; 5272 __le64 rx_discard_packets_cos7; 5273 __le64 rx_fec_corrected_blocks; 5274 __le64 rx_fec_uncorrectable_blocks; 5275 __le64 rx_filter_miss; 5276 __le64 rx_fec_symbol_err; 5277}; 5278 5279/* hwrm_port_qstats_ext_input (size:320b/40B) */ 5280struct hwrm_port_qstats_ext_input { 5281 __le16 req_type; 5282 __le16 cmpl_ring; 5283 __le16 seq_id; 5284 __le16 target_id; 5285 __le64 resp_addr; 5286 __le16 port_id; 5287 __le16 tx_stat_size; 5288 __le16 rx_stat_size; 5289 u8 flags; 5290 #define PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x1UL 5291 u8 unused_0; 5292 __le64 tx_stat_host_addr; 5293 __le64 rx_stat_host_addr; 5294}; 5295 5296/* hwrm_port_qstats_ext_output (size:128b/16B) */ 5297struct hwrm_port_qstats_ext_output { 5298 __le16 error_code; 5299 __le16 req_type; 5300 __le16 seq_id; 5301 __le16 resp_len; 5302 __le16 tx_stat_size; 5303 __le16 rx_stat_size; 5304 __le16 total_active_cos_queues; 5305 u8 flags; 5306 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEAR_ROCE_COUNTERS_SUPPORTED 0x1UL 5307 #define PORT_QSTATS_EXT_RESP_FLAGS_CLEARED 0x2UL 5308 u8 valid; 5309}; 5310 5311/* hwrm_port_lpbk_qstats_input (size:256b/32B) */ 5312struct hwrm_port_lpbk_qstats_input { 5313 __le16 req_type; 5314 __le16 cmpl_ring; 5315 __le16 seq_id; 5316 __le16 target_id; 5317 __le64 resp_addr; 5318 __le16 lpbk_stat_size; 5319 u8 flags; 5320 #define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5321 u8 unused_0[5]; 5322 __le64 lpbk_stat_host_addr; 5323}; 5324 5325/* hwrm_port_lpbk_qstats_output (size:128b/16B) */ 5326struct hwrm_port_lpbk_qstats_output { 5327 __le16 error_code; 5328 __le16 req_type; 5329 __le16 seq_id; 5330 __le16 resp_len; 5331 __le16 lpbk_stat_size; 5332 u8 unused_0[5]; 5333 u8 valid; 5334}; 5335 5336/* port_lpbk_stats (size:640b/80B) */ 5337struct port_lpbk_stats { 5338 __le64 lpbk_ucast_frames; 5339 __le64 lpbk_mcast_frames; 5340 __le64 lpbk_bcast_frames; 5341 __le64 lpbk_ucast_bytes; 5342 __le64 lpbk_mcast_bytes; 5343 __le64 lpbk_bcast_bytes; 5344 __le64 lpbk_tx_discards; 5345 __le64 lpbk_tx_errors; 5346 __le64 lpbk_rx_discards; 5347 __le64 lpbk_rx_errors; 5348}; 5349 5350/* hwrm_port_ecn_qstats_input (size:256b/32B) */ 5351struct hwrm_port_ecn_qstats_input { 5352 __le16 req_type; 5353 __le16 cmpl_ring; 5354 __le16 seq_id; 5355 __le16 target_id; 5356 __le64 resp_addr; 5357 __le16 port_id; 5358 __le16 ecn_stat_buf_size; 5359 u8 flags; 5360 #define PORT_ECN_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 5361 u8 unused_0[3]; 5362 __le64 ecn_stat_host_addr; 5363}; 5364 5365/* hwrm_port_ecn_qstats_output (size:128b/16B) */ 5366struct hwrm_port_ecn_qstats_output { 5367 __le16 error_code; 5368 __le16 req_type; 5369 __le16 seq_id; 5370 __le16 resp_len; 5371 __le16 ecn_stat_buf_size; 5372 u8 mark_en; 5373 u8 unused_0[4]; 5374 u8 valid; 5375}; 5376 5377/* port_stats_ecn (size:512b/64B) */ 5378struct port_stats_ecn { 5379 __le64 mark_cnt_cos0; 5380 __le64 mark_cnt_cos1; 5381 __le64 mark_cnt_cos2; 5382 __le64 mark_cnt_cos3; 5383 __le64 mark_cnt_cos4; 5384 __le64 mark_cnt_cos5; 5385 __le64 mark_cnt_cos6; 5386 __le64 mark_cnt_cos7; 5387}; 5388 5389/* hwrm_port_clr_stats_input (size:192b/24B) */ 5390struct hwrm_port_clr_stats_input { 5391 __le16 req_type; 5392 __le16 cmpl_ring; 5393 __le16 seq_id; 5394 __le16 target_id; 5395 __le64 resp_addr; 5396 __le16 port_id; 5397 u8 flags; 5398 #define PORT_CLR_STATS_REQ_FLAGS_ROCE_COUNTERS 0x1UL 5399 u8 unused_0[5]; 5400}; 5401 5402/* hwrm_port_clr_stats_output (size:128b/16B) */ 5403struct hwrm_port_clr_stats_output { 5404 __le16 error_code; 5405 __le16 req_type; 5406 __le16 seq_id; 5407 __le16 resp_len; 5408 u8 unused_0[7]; 5409 u8 valid; 5410}; 5411 5412/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */ 5413struct hwrm_port_lpbk_clr_stats_input { 5414 __le16 req_type; 5415 __le16 cmpl_ring; 5416 __le16 seq_id; 5417 __le16 target_id; 5418 __le64 resp_addr; 5419 __le16 port_id; 5420 u8 unused_0[6]; 5421}; 5422 5423/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 5424struct hwrm_port_lpbk_clr_stats_output { 5425 __le16 error_code; 5426 __le16 req_type; 5427 __le16 seq_id; 5428 __le16 resp_len; 5429 u8 unused_0[7]; 5430 u8 valid; 5431}; 5432 5433/* hwrm_port_ts_query_input (size:320b/40B) */ 5434struct hwrm_port_ts_query_input { 5435 __le16 req_type; 5436 __le16 cmpl_ring; 5437 __le16 seq_id; 5438 __le16 target_id; 5439 __le64 resp_addr; 5440 __le32 flags; 5441 #define PORT_TS_QUERY_REQ_FLAGS_PATH 0x1UL 5442 #define PORT_TS_QUERY_REQ_FLAGS_PATH_TX 0x0UL 5443 #define PORT_TS_QUERY_REQ_FLAGS_PATH_RX 0x1UL 5444 #define PORT_TS_QUERY_REQ_FLAGS_PATH_LAST PORT_TS_QUERY_REQ_FLAGS_PATH_RX 5445 #define PORT_TS_QUERY_REQ_FLAGS_CURRENT_TIME 0x2UL 5446 __le16 port_id; 5447 u8 unused_0[2]; 5448 __le16 enables; 5449 #define PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT 0x1UL 5450 #define PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID 0x2UL 5451 #define PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET 0x4UL 5452 __le16 ts_req_timeout; 5453 __le32 ptp_seq_id; 5454 __le16 ptp_hdr_offset; 5455 u8 unused_1[6]; 5456}; 5457 5458/* hwrm_port_ts_query_output (size:192b/24B) */ 5459struct hwrm_port_ts_query_output { 5460 __le16 error_code; 5461 __le16 req_type; 5462 __le16 seq_id; 5463 __le16 resp_len; 5464 __le64 ptp_msg_ts; 5465 __le16 ptp_msg_seqid; 5466 u8 unused_0[5]; 5467 u8 valid; 5468}; 5469 5470/* hwrm_port_phy_qcaps_input (size:192b/24B) */ 5471struct hwrm_port_phy_qcaps_input { 5472 __le16 req_type; 5473 __le16 cmpl_ring; 5474 __le16 seq_id; 5475 __le16 target_id; 5476 __le64 resp_addr; 5477 __le16 port_id; 5478 u8 unused_0[6]; 5479}; 5480 5481/* hwrm_port_phy_qcaps_output (size:320b/40B) */ 5482struct hwrm_port_phy_qcaps_output { 5483 __le16 error_code; 5484 __le16 req_type; 5485 __le16 seq_id; 5486 __le16 resp_len; 5487 u8 flags; 5488 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 5489 #define PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED 0x2UL 5490 #define PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED 0x4UL 5491 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 5492 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 5493 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 5494 #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 5495 #define PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS 0x80UL 5496 u8 port_cnt; 5497 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 5498 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 5499 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 5500 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 5501 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 5502 #define PORT_PHY_QCAPS_RESP_PORT_CNT_12 0xcUL 5503 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_12 5504 __le16 supported_speeds_force_mode; 5505 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 5506 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 5507 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 5508 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 5509 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 5510 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 5511 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 5512 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 5513 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 5514 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 5515 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 5516 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 5517 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 5518 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 5519 __le16 supported_speeds_auto_mode; 5520 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 5521 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 5522 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 5523 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 5524 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 5525 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 5526 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 5527 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 5528 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 5529 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 5530 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 5531 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 5532 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 5533 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 5534 __le16 supported_speeds_eee_mode; 5535 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 5536 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 5537 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 5538 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 5539 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 5540 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 5541 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 5542 __le32 tx_lpi_timer_low; 5543 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 5544 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 5545 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 5546 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 5547 __le32 valid_tx_lpi_timer_high; 5548 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 5549 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 5550 #define PORT_PHY_QCAPS_RESP_RSVD_MASK 0xff000000UL 5551 #define PORT_PHY_QCAPS_RESP_RSVD_SFT 24 5552 __le16 supported_pam4_speeds_auto_mode; 5553 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_50G 0x1UL 5554 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_100G 0x2UL 5555 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_AUTO_MODE_200G 0x4UL 5556 __le16 supported_pam4_speeds_force_mode; 5557 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_50G 0x1UL 5558 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_100G 0x2UL 5559 #define PORT_PHY_QCAPS_RESP_SUPPORTED_PAM4_SPEEDS_FORCE_MODE_200G 0x4UL 5560 __le16 flags2; 5561 #define PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED 0x1UL 5562 #define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED 0x2UL 5563 #define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED 0x4UL 5564 #define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED 0x8UL 5565 #define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED 0x10UL 5566 u8 internal_port_cnt; 5567 u8 unused_0; 5568 __le16 supported_speeds2_force_mode; 5569 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_1GB 0x1UL 5570 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_10GB 0x2UL 5571 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_25GB 0x4UL 5572 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_40GB 0x8UL 5573 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB 0x10UL 5574 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB 0x20UL 5575 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_50GB_PAM4_56 0x40UL 5576 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_56 0x80UL 5577 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_56 0x100UL 5578 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_56 0x200UL 5579 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_100GB_PAM4_112 0x400UL 5580 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_200GB_PAM4_112 0x800UL 5581 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_400GB_PAM4_112 0x1000UL 5582 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_FORCE_MODE_800GB_PAM4_112 0x2000UL 5583 __le16 supported_speeds2_auto_mode; 5584 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_1GB 0x1UL 5585 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_10GB 0x2UL 5586 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_25GB 0x4UL 5587 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_40GB 0x8UL 5588 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB 0x10UL 5589 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB 0x20UL 5590 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_50GB_PAM4_56 0x40UL 5591 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_56 0x80UL 5592 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_56 0x100UL 5593 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_56 0x200UL 5594 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_100GB_PAM4_112 0x400UL 5595 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_200GB_PAM4_112 0x800UL 5596 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_400GB_PAM4_112 0x1000UL 5597 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS2_AUTO_MODE_800GB_PAM4_112 0x2000UL 5598 u8 unused_1[3]; 5599 u8 valid; 5600}; 5601 5602/* hwrm_port_phy_i2c_write_input (size:832b/104B) */ 5603struct hwrm_port_phy_i2c_write_input { 5604 __le16 req_type; 5605 __le16 cmpl_ring; 5606 __le16 seq_id; 5607 __le16 target_id; 5608 __le64 resp_addr; 5609 __le32 flags; 5610 __le32 enables; 5611 #define PORT_PHY_I2C_WRITE_REQ_ENABLES_PAGE_OFFSET 0x1UL 5612 #define PORT_PHY_I2C_WRITE_REQ_ENABLES_BANK_NUMBER 0x2UL 5613 __le16 port_id; 5614 u8 i2c_slave_addr; 5615 u8 bank_number; 5616 __le16 page_number; 5617 __le16 page_offset; 5618 u8 data_length; 5619 u8 unused_1[7]; 5620 __le32 data[16]; 5621}; 5622 5623/* hwrm_port_phy_i2c_write_output (size:128b/16B) */ 5624struct hwrm_port_phy_i2c_write_output { 5625 __le16 error_code; 5626 __le16 req_type; 5627 __le16 seq_id; 5628 __le16 resp_len; 5629 u8 unused_0[7]; 5630 u8 valid; 5631}; 5632 5633/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 5634struct hwrm_port_phy_i2c_read_input { 5635 __le16 req_type; 5636 __le16 cmpl_ring; 5637 __le16 seq_id; 5638 __le16 target_id; 5639 __le64 resp_addr; 5640 __le32 flags; 5641 __le32 enables; 5642 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 5643 #define PORT_PHY_I2C_READ_REQ_ENABLES_BANK_NUMBER 0x2UL 5644 __le16 port_id; 5645 u8 i2c_slave_addr; 5646 u8 bank_number; 5647 __le16 page_number; 5648 __le16 page_offset; 5649 u8 data_length; 5650 u8 unused_1[7]; 5651}; 5652 5653/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 5654struct hwrm_port_phy_i2c_read_output { 5655 __le16 error_code; 5656 __le16 req_type; 5657 __le16 seq_id; 5658 __le16 resp_len; 5659 __le32 data[16]; 5660 u8 unused_0[7]; 5661 u8 valid; 5662}; 5663 5664/* hwrm_port_phy_mdio_write_input (size:320b/40B) */ 5665struct hwrm_port_phy_mdio_write_input { 5666 __le16 req_type; 5667 __le16 cmpl_ring; 5668 __le16 seq_id; 5669 __le16 target_id; 5670 __le64 resp_addr; 5671 __le32 unused_0[2]; 5672 __le16 port_id; 5673 u8 phy_addr; 5674 u8 dev_addr; 5675 __le16 reg_addr; 5676 __le16 reg_data; 5677 u8 cl45_mdio; 5678 u8 unused_1[7]; 5679}; 5680 5681/* hwrm_port_phy_mdio_write_output (size:128b/16B) */ 5682struct hwrm_port_phy_mdio_write_output { 5683 __le16 error_code; 5684 __le16 req_type; 5685 __le16 seq_id; 5686 __le16 resp_len; 5687 u8 unused_0[7]; 5688 u8 valid; 5689}; 5690 5691/* hwrm_port_phy_mdio_read_input (size:256b/32B) */ 5692struct hwrm_port_phy_mdio_read_input { 5693 __le16 req_type; 5694 __le16 cmpl_ring; 5695 __le16 seq_id; 5696 __le16 target_id; 5697 __le64 resp_addr; 5698 __le32 unused_0[2]; 5699 __le16 port_id; 5700 u8 phy_addr; 5701 u8 dev_addr; 5702 __le16 reg_addr; 5703 u8 cl45_mdio; 5704 u8 unused_1; 5705}; 5706 5707/* hwrm_port_phy_mdio_read_output (size:128b/16B) */ 5708struct hwrm_port_phy_mdio_read_output { 5709 __le16 error_code; 5710 __le16 req_type; 5711 __le16 seq_id; 5712 __le16 resp_len; 5713 __le16 reg_data; 5714 u8 unused_0[5]; 5715 u8 valid; 5716}; 5717 5718/* hwrm_port_led_cfg_input (size:512b/64B) */ 5719struct hwrm_port_led_cfg_input { 5720 __le16 req_type; 5721 __le16 cmpl_ring; 5722 __le16 seq_id; 5723 __le16 target_id; 5724 __le64 resp_addr; 5725 __le32 enables; 5726 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 5727 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 5728 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 5729 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 5730 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 5731 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 5732 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 5733 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 5734 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 5735 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 5736 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 5737 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 5738 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 5739 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 5740 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 5741 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 5742 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 5743 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 5744 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 5745 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 5746 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 5747 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 5748 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 5749 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 5750 __le16 port_id; 5751 u8 num_leds; 5752 u8 rsvd; 5753 u8 led0_id; 5754 u8 led0_state; 5755 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 5756 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 5757 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 5758 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 5759 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 5760 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 5761 u8 led0_color; 5762 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 5763 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 5764 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 5765 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 5766 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 5767 u8 unused_0; 5768 __le16 led0_blink_on; 5769 __le16 led0_blink_off; 5770 u8 led0_group_id; 5771 u8 rsvd0; 5772 u8 led1_id; 5773 u8 led1_state; 5774 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 5775 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 5776 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 5777 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 5778 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 5779 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 5780 u8 led1_color; 5781 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 5782 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 5783 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 5784 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 5785 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 5786 u8 unused_1; 5787 __le16 led1_blink_on; 5788 __le16 led1_blink_off; 5789 u8 led1_group_id; 5790 u8 rsvd1; 5791 u8 led2_id; 5792 u8 led2_state; 5793 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 5794 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 5795 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 5796 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 5797 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 5798 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 5799 u8 led2_color; 5800 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 5801 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 5802 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 5803 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 5804 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 5805 u8 unused_2; 5806 __le16 led2_blink_on; 5807 __le16 led2_blink_off; 5808 u8 led2_group_id; 5809 u8 rsvd2; 5810 u8 led3_id; 5811 u8 led3_state; 5812 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 5813 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 5814 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 5815 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 5816 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 5817 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 5818 u8 led3_color; 5819 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 5820 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 5821 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 5822 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 5823 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 5824 u8 unused_3; 5825 __le16 led3_blink_on; 5826 __le16 led3_blink_off; 5827 u8 led3_group_id; 5828 u8 rsvd3; 5829}; 5830 5831/* hwrm_port_led_cfg_output (size:128b/16B) */ 5832struct hwrm_port_led_cfg_output { 5833 __le16 error_code; 5834 __le16 req_type; 5835 __le16 seq_id; 5836 __le16 resp_len; 5837 u8 unused_0[7]; 5838 u8 valid; 5839}; 5840 5841/* hwrm_port_led_qcfg_input (size:192b/24B) */ 5842struct hwrm_port_led_qcfg_input { 5843 __le16 req_type; 5844 __le16 cmpl_ring; 5845 __le16 seq_id; 5846 __le16 target_id; 5847 __le64 resp_addr; 5848 __le16 port_id; 5849 u8 unused_0[6]; 5850}; 5851 5852/* hwrm_port_led_qcfg_output (size:448b/56B) */ 5853struct hwrm_port_led_qcfg_output { 5854 __le16 error_code; 5855 __le16 req_type; 5856 __le16 seq_id; 5857 __le16 resp_len; 5858 u8 num_leds; 5859 u8 led0_id; 5860 u8 led0_type; 5861 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 5862 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 5863 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 5864 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 5865 u8 led0_state; 5866 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 5867 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 5868 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 5869 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 5870 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 5871 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 5872 u8 led0_color; 5873 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 5874 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 5875 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 5876 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 5877 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 5878 u8 unused_0; 5879 __le16 led0_blink_on; 5880 __le16 led0_blink_off; 5881 u8 led0_group_id; 5882 u8 led1_id; 5883 u8 led1_type; 5884 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 5885 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 5886 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 5887 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 5888 u8 led1_state; 5889 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 5890 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 5891 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 5892 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 5893 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 5894 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 5895 u8 led1_color; 5896 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 5897 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 5898 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 5899 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 5900 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 5901 u8 unused_1; 5902 __le16 led1_blink_on; 5903 __le16 led1_blink_off; 5904 u8 led1_group_id; 5905 u8 led2_id; 5906 u8 led2_type; 5907 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 5908 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 5909 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 5910 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 5911 u8 led2_state; 5912 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 5913 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 5914 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 5915 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 5916 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 5917 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 5918 u8 led2_color; 5919 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 5920 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 5921 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 5922 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 5923 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 5924 u8 unused_2; 5925 __le16 led2_blink_on; 5926 __le16 led2_blink_off; 5927 u8 led2_group_id; 5928 u8 led3_id; 5929 u8 led3_type; 5930 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 5931 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 5932 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 5933 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 5934 u8 led3_state; 5935 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 5936 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 5937 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 5938 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 5939 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 5940 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 5941 u8 led3_color; 5942 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 5943 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 5944 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 5945 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 5946 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 5947 u8 unused_3; 5948 __le16 led3_blink_on; 5949 __le16 led3_blink_off; 5950 u8 led3_group_id; 5951 u8 unused_4[6]; 5952 u8 valid; 5953}; 5954 5955/* hwrm_port_led_qcaps_input (size:192b/24B) */ 5956struct hwrm_port_led_qcaps_input { 5957 __le16 req_type; 5958 __le16 cmpl_ring; 5959 __le16 seq_id; 5960 __le16 target_id; 5961 __le64 resp_addr; 5962 __le16 port_id; 5963 u8 unused_0[6]; 5964}; 5965 5966/* hwrm_port_led_qcaps_output (size:384b/48B) */ 5967struct hwrm_port_led_qcaps_output { 5968 __le16 error_code; 5969 __le16 req_type; 5970 __le16 seq_id; 5971 __le16 resp_len; 5972 u8 num_leds; 5973 u8 unused[3]; 5974 u8 led0_id; 5975 u8 led0_type; 5976 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 5977 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 5978 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 5979 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 5980 u8 led0_group_id; 5981 u8 unused_0; 5982 __le16 led0_state_caps; 5983 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 5984 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 5985 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 5986 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 5987 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 5988 __le16 led0_color_caps; 5989 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 5990 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 5991 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 5992 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 5993 u8 led1_id; 5994 u8 led1_type; 5995 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 5996 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 5997 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 5998 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 5999 u8 led1_group_id; 6000 u8 unused_1; 6001 __le16 led1_state_caps; 6002 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 6003 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 6004 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 6005 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6006 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6007 __le16 led1_color_caps; 6008 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 6009 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6010 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6011 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6012 u8 led2_id; 6013 u8 led2_type; 6014 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 6015 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 6016 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 6017 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 6018 u8 led2_group_id; 6019 u8 unused_2; 6020 __le16 led2_state_caps; 6021 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 6022 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 6023 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 6024 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6025 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6026 __le16 led2_color_caps; 6027 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 6028 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6029 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6030 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6031 u8 led3_id; 6032 u8 led3_type; 6033 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 6034 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 6035 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 6036 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 6037 u8 led3_group_id; 6038 u8 unused_3; 6039 __le16 led3_state_caps; 6040 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 6041 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 6042 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 6043 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 6044 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 6045 __le16 led3_color_caps; 6046 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 6047 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 6048 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 6049 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GRNAMB_SUPPORTED 0x8UL 6050 u8 unused_4[3]; 6051 u8 valid; 6052}; 6053 6054/* hwrm_port_mac_qcaps_input (size:192b/24B) */ 6055struct hwrm_port_mac_qcaps_input { 6056 __le16 req_type; 6057 __le16 cmpl_ring; 6058 __le16 seq_id; 6059 __le16 target_id; 6060 __le64 resp_addr; 6061 __le16 port_id; 6062 u8 unused_0[6]; 6063}; 6064 6065/* hwrm_port_mac_qcaps_output (size:128b/16B) */ 6066struct hwrm_port_mac_qcaps_output { 6067 __le16 error_code; 6068 __le16 req_type; 6069 __le16 seq_id; 6070 __le16 resp_len; 6071 u8 flags; 6072 #define PORT_MAC_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x1UL 6073 #define PORT_MAC_QCAPS_RESP_FLAGS_REMOTE_LPBK_SUPPORTED 0x2UL 6074 u8 unused_0[6]; 6075 u8 valid; 6076}; 6077 6078/* hwrm_queue_qportcfg_input (size:192b/24B) */ 6079struct hwrm_queue_qportcfg_input { 6080 __le16 req_type; 6081 __le16 cmpl_ring; 6082 __le16 seq_id; 6083 __le16 target_id; 6084 __le64 resp_addr; 6085 __le32 flags; 6086 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 6087 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 6088 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 6089 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 6090 __le16 port_id; 6091 u8 drv_qmap_cap; 6092 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 6093 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 6094 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 6095 u8 unused_0; 6096}; 6097 6098/* hwrm_queue_qportcfg_output (size:1344b/168B) */ 6099struct hwrm_queue_qportcfg_output { 6100 __le16 error_code; 6101 __le16 req_type; 6102 __le16 seq_id; 6103 __le16 resp_len; 6104 u8 max_configurable_queues; 6105 u8 max_configurable_lossless_queues; 6106 u8 queue_cfg_allowed; 6107 u8 queue_cfg_info; 6108 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6109 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_USE_PROFILE_TYPE 0x2UL 6110 u8 queue_pfcenable_cfg_allowed; 6111 u8 queue_pri2cos_cfg_allowed; 6112 u8 queue_cos2bw_cfg_allowed; 6113 u8 queue_id0; 6114 u8 queue_id0_service_profile; 6115 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 6116 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS 0x1UL 6117 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6118 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6119 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6120 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 6121 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 6122 u8 queue_id1; 6123 u8 queue_id1_service_profile; 6124 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 6125 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS 0x1UL 6126 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6127 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6128 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6129 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 6130 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 6131 u8 queue_id2; 6132 u8 queue_id2_service_profile; 6133 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 6134 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS 0x1UL 6135 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6136 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6137 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6138 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 6139 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 6140 u8 queue_id3; 6141 u8 queue_id3_service_profile; 6142 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 6143 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS 0x1UL 6144 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6145 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6146 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6147 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 6148 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 6149 u8 queue_id4; 6150 u8 queue_id4_service_profile; 6151 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 6152 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS 0x1UL 6153 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6154 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6155 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6156 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 6157 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 6158 u8 queue_id5; 6159 u8 queue_id5_service_profile; 6160 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 6161 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS 0x1UL 6162 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6163 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6164 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6165 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 6166 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 6167 u8 queue_id6; 6168 u8 queue_id6_service_profile; 6169 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 6170 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS 0x1UL 6171 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6172 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6173 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6174 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 6175 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 6176 u8 queue_id7; 6177 u8 queue_id7_service_profile; 6178 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 6179 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS 0x1UL 6180 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 6181 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 6182 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 6183 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 6184 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 6185 u8 queue_id0_service_profile_type; 6186 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6187 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 6188 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 6189 char qid0_name[16]; 6190 char qid1_name[16]; 6191 char qid2_name[16]; 6192 char qid3_name[16]; 6193 char qid4_name[16]; 6194 char qid5_name[16]; 6195 char qid6_name[16]; 6196 char qid7_name[16]; 6197 u8 queue_id1_service_profile_type; 6198 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6199 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 6200 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 6201 u8 queue_id2_service_profile_type; 6202 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6203 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 6204 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 6205 u8 queue_id3_service_profile_type; 6206 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6207 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 6208 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 6209 u8 queue_id4_service_profile_type; 6210 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6211 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 6212 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 6213 u8 queue_id5_service_profile_type; 6214 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6215 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 6216 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 6217 u8 queue_id6_service_profile_type; 6218 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6219 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 6220 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 6221 u8 queue_id7_service_profile_type; 6222 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 6223 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 6224 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 6225 u8 valid; 6226}; 6227 6228/* hwrm_queue_qcfg_input (size:192b/24B) */ 6229struct hwrm_queue_qcfg_input { 6230 __le16 req_type; 6231 __le16 cmpl_ring; 6232 __le16 seq_id; 6233 __le16 target_id; 6234 __le64 resp_addr; 6235 __le32 flags; 6236 #define QUEUE_QCFG_REQ_FLAGS_PATH 0x1UL 6237 #define QUEUE_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6238 #define QUEUE_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6239 #define QUEUE_QCFG_REQ_FLAGS_PATH_LAST QUEUE_QCFG_REQ_FLAGS_PATH_RX 6240 __le32 queue_id; 6241}; 6242 6243/* hwrm_queue_qcfg_output (size:128b/16B) */ 6244struct hwrm_queue_qcfg_output { 6245 __le16 error_code; 6246 __le16 req_type; 6247 __le16 seq_id; 6248 __le16 resp_len; 6249 __le32 queue_len; 6250 u8 service_profile; 6251 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSY 0x0UL 6252 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LOSSLESS 0x1UL 6253 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 0xffUL 6254 #define QUEUE_QCFG_RESP_SERVICE_PROFILE_LAST QUEUE_QCFG_RESP_SERVICE_PROFILE_UNKNOWN 6255 u8 queue_cfg_info; 6256 #define QUEUE_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6257 u8 unused_0; 6258 u8 valid; 6259}; 6260 6261/* hwrm_queue_cfg_input (size:320b/40B) */ 6262struct hwrm_queue_cfg_input { 6263 __le16 req_type; 6264 __le16 cmpl_ring; 6265 __le16 seq_id; 6266 __le16 target_id; 6267 __le64 resp_addr; 6268 __le32 flags; 6269 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6270 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 6271 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 6272 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 6273 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6274 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 6275 __le32 enables; 6276 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 6277 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 6278 __le32 queue_id; 6279 __le32 dflt_len; 6280 u8 service_profile; 6281 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 6282 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 6283 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 6284 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 6285 u8 unused_0[7]; 6286}; 6287 6288/* hwrm_queue_cfg_output (size:128b/16B) */ 6289struct hwrm_queue_cfg_output { 6290 __le16 error_code; 6291 __le16 req_type; 6292 __le16 seq_id; 6293 __le16 resp_len; 6294 u8 unused_0[7]; 6295 u8 valid; 6296}; 6297 6298/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 6299struct hwrm_queue_pfcenable_qcfg_input { 6300 __le16 req_type; 6301 __le16 cmpl_ring; 6302 __le16 seq_id; 6303 __le16 target_id; 6304 __le64 resp_addr; 6305 __le16 port_id; 6306 u8 unused_0[6]; 6307}; 6308 6309/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 6310struct hwrm_queue_pfcenable_qcfg_output { 6311 __le16 error_code; 6312 __le16 req_type; 6313 __le16 seq_id; 6314 __le16 resp_len; 6315 __le32 flags; 6316 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 6317 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 6318 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 6319 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 6320 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 6321 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 6322 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 6323 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 6324 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6325 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6326 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6327 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6328 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6329 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6330 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6331 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6332 u8 unused_0[3]; 6333 u8 valid; 6334}; 6335 6336/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 6337struct hwrm_queue_pfcenable_cfg_input { 6338 __le16 req_type; 6339 __le16 cmpl_ring; 6340 __le16 seq_id; 6341 __le16 target_id; 6342 __le64 resp_addr; 6343 __le32 flags; 6344 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 6345 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 6346 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 6347 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 6348 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 6349 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 6350 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 6351 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 6352 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_WATCHDOG_ENABLED 0x100UL 6353 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_WATCHDOG_ENABLED 0x200UL 6354 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_WATCHDOG_ENABLED 0x400UL 6355 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_WATCHDOG_ENABLED 0x800UL 6356 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_WATCHDOG_ENABLED 0x1000UL 6357 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_WATCHDOG_ENABLED 0x2000UL 6358 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_WATCHDOG_ENABLED 0x4000UL 6359 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_WATCHDOG_ENABLED 0x8000UL 6360 __le16 port_id; 6361 u8 unused_0[2]; 6362}; 6363 6364/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 6365struct hwrm_queue_pfcenable_cfg_output { 6366 __le16 error_code; 6367 __le16 req_type; 6368 __le16 seq_id; 6369 __le16 resp_len; 6370 u8 unused_0[7]; 6371 u8 valid; 6372}; 6373 6374/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 6375struct hwrm_queue_pri2cos_qcfg_input { 6376 __le16 req_type; 6377 __le16 cmpl_ring; 6378 __le16 seq_id; 6379 __le16 target_id; 6380 __le64 resp_addr; 6381 __le32 flags; 6382 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 6383 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 6384 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 6385 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 6386 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 6387 u8 port_id; 6388 u8 unused_0[3]; 6389}; 6390 6391/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 6392struct hwrm_queue_pri2cos_qcfg_output { 6393 __le16 error_code; 6394 __le16 req_type; 6395 __le16 seq_id; 6396 __le16 resp_len; 6397 u8 pri0_cos_queue_id; 6398 u8 pri1_cos_queue_id; 6399 u8 pri2_cos_queue_id; 6400 u8 pri3_cos_queue_id; 6401 u8 pri4_cos_queue_id; 6402 u8 pri5_cos_queue_id; 6403 u8 pri6_cos_queue_id; 6404 u8 pri7_cos_queue_id; 6405 u8 queue_cfg_info; 6406 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 6407 u8 unused_0[6]; 6408 u8 valid; 6409}; 6410 6411/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 6412struct hwrm_queue_pri2cos_cfg_input { 6413 __le16 req_type; 6414 __le16 cmpl_ring; 6415 __le16 seq_id; 6416 __le16 target_id; 6417 __le64 resp_addr; 6418 __le32 flags; 6419 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 6420 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 6421 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 6422 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 6423 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 6424 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 6425 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 6426 __le32 enables; 6427 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 6428 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 6429 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 6430 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 6431 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 6432 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 6433 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 6434 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 6435 u8 port_id; 6436 u8 pri0_cos_queue_id; 6437 u8 pri1_cos_queue_id; 6438 u8 pri2_cos_queue_id; 6439 u8 pri3_cos_queue_id; 6440 u8 pri4_cos_queue_id; 6441 u8 pri5_cos_queue_id; 6442 u8 pri6_cos_queue_id; 6443 u8 pri7_cos_queue_id; 6444 u8 unused_0[7]; 6445}; 6446 6447/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 6448struct hwrm_queue_pri2cos_cfg_output { 6449 __le16 error_code; 6450 __le16 req_type; 6451 __le16 seq_id; 6452 __le16 resp_len; 6453 u8 unused_0[7]; 6454 u8 valid; 6455}; 6456 6457/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 6458struct hwrm_queue_cos2bw_qcfg_input { 6459 __le16 req_type; 6460 __le16 cmpl_ring; 6461 __le16 seq_id; 6462 __le16 target_id; 6463 __le64 resp_addr; 6464 __le16 port_id; 6465 u8 unused_0[6]; 6466}; 6467 6468/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 6469struct hwrm_queue_cos2bw_qcfg_output { 6470 __le16 error_code; 6471 __le16 req_type; 6472 __le16 seq_id; 6473 __le16 resp_len; 6474 u8 queue_id0; 6475 u8 unused_0; 6476 __le16 unused_1; 6477 __le32 queue_id0_min_bw; 6478 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6479 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6480 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6481 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6482 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6483 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 6484 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6485 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6486 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6487 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6488 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6489 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6490 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6491 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6492 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6493 __le32 queue_id0_max_bw; 6494 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6495 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6496 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6497 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6498 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6499 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 6500 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6501 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6502 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6503 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6504 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6505 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6506 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6507 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6508 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6509 u8 queue_id0_tsa_assign; 6510 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6511 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6512 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6513 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6514 u8 queue_id0_pri_lvl; 6515 u8 queue_id0_bw_weight; 6516 struct { 6517 u8 queue_id; 6518 __le32 queue_id_min_bw; 6519 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6520 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6521 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6522 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6523 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6524 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_SCALE_BYTES 6525 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6526 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6527 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6528 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6529 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6530 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6531 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6532 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6533 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6534 __le32 queue_id_max_bw; 6535 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6536 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6537 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6538 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6539 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6540 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_SCALE_BYTES 6541 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6542 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6543 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6544 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6545 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6546 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6547 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6548 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6549 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6550 u8 queue_id_tsa_assign; 6551 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6552 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6553 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6554 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6555 u8 queue_id_pri_lvl; 6556 u8 queue_id_bw_weight; 6557 } __packed cfg[7]; 6558 u8 unused_2[4]; 6559 u8 valid; 6560}; 6561 6562/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 6563struct hwrm_queue_cos2bw_cfg_input { 6564 __le16 req_type; 6565 __le16 cmpl_ring; 6566 __le16 seq_id; 6567 __le16 target_id; 6568 __le64 resp_addr; 6569 __le32 flags; 6570 __le32 enables; 6571 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 6572 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 6573 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 6574 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 6575 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 6576 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 6577 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 6578 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 6579 __le16 port_id; 6580 u8 queue_id0; 6581 u8 unused_0; 6582 __le32 queue_id0_min_bw; 6583 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6584 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 6585 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 6586 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 6587 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 6588 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 6589 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6590 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 6591 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6592 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6593 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6594 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6595 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6596 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6597 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 6598 __le32 queue_id0_max_bw; 6599 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6600 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 6601 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 6602 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 6603 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 6604 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 6605 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6606 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 6607 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6608 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6609 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6610 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6611 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6612 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6613 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 6614 u8 queue_id0_tsa_assign; 6615 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 6616 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 6617 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6618 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 6619 u8 queue_id0_pri_lvl; 6620 u8 queue_id0_bw_weight; 6621 struct { 6622 u8 queue_id; 6623 __le32 queue_id_min_bw; 6624 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_MASK 0xfffffffUL 6625 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_SFT 0 6626 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE 0x10000000UL 6627 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BITS (0x0UL << 28) 6628 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES (0x1UL << 28) 6629 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_SCALE_BYTES 6630 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6631 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_SFT 29 6632 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6633 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6634 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6635 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6636 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6637 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6638 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MIN_BW_BW_VALUE_UNIT_INVALID 6639 __le32 queue_id_max_bw; 6640 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_MASK 0xfffffffUL 6641 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_SFT 0 6642 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE 0x10000000UL 6643 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BITS (0x0UL << 28) 6644 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES (0x1UL << 28) 6645 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_SCALE_BYTES 6646 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 6647 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_SFT 29 6648 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 6649 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 6650 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 6651 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 6652 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 6653 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 6654 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID_MAX_BW_BW_VALUE_UNIT_INVALID 6655 u8 queue_id_tsa_assign; 6656 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_SP 0x0UL 6657 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_ETS 0x1UL 6658 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_FIRST 0x2UL 6659 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID_TSA_ASSIGN_RESERVED_LAST 0xffUL 6660 u8 queue_id_pri_lvl; 6661 u8 queue_id_bw_weight; 6662 } __packed cfg[7]; 6663 u8 unused_1[5]; 6664}; 6665 6666/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 6667struct hwrm_queue_cos2bw_cfg_output { 6668 __le16 error_code; 6669 __le16 req_type; 6670 __le16 seq_id; 6671 __le16 resp_len; 6672 u8 unused_0[7]; 6673 u8 valid; 6674}; 6675 6676/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 6677struct hwrm_queue_dscp_qcaps_input { 6678 __le16 req_type; 6679 __le16 cmpl_ring; 6680 __le16 seq_id; 6681 __le16 target_id; 6682 __le64 resp_addr; 6683 u8 port_id; 6684 u8 unused_0[7]; 6685}; 6686 6687/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 6688struct hwrm_queue_dscp_qcaps_output { 6689 __le16 error_code; 6690 __le16 req_type; 6691 __le16 seq_id; 6692 __le16 resp_len; 6693 u8 num_dscp_bits; 6694 u8 unused_0; 6695 __le16 max_entries; 6696 u8 unused_1[3]; 6697 u8 valid; 6698}; 6699 6700/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 6701struct hwrm_queue_dscp2pri_qcfg_input { 6702 __le16 req_type; 6703 __le16 cmpl_ring; 6704 __le16 seq_id; 6705 __le16 target_id; 6706 __le64 resp_addr; 6707 __le64 dest_data_addr; 6708 u8 port_id; 6709 u8 unused_0; 6710 __le16 dest_data_buffer_size; 6711 u8 unused_1[4]; 6712}; 6713 6714/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 6715struct hwrm_queue_dscp2pri_qcfg_output { 6716 __le16 error_code; 6717 __le16 req_type; 6718 __le16 seq_id; 6719 __le16 resp_len; 6720 __le16 entry_cnt; 6721 u8 default_pri; 6722 u8 unused_0[4]; 6723 u8 valid; 6724}; 6725 6726/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 6727struct hwrm_queue_dscp2pri_cfg_input { 6728 __le16 req_type; 6729 __le16 cmpl_ring; 6730 __le16 seq_id; 6731 __le16 target_id; 6732 __le64 resp_addr; 6733 __le64 src_data_addr; 6734 __le32 flags; 6735 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 6736 __le32 enables; 6737 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 6738 u8 port_id; 6739 u8 default_pri; 6740 __le16 entry_cnt; 6741 u8 unused_0[4]; 6742}; 6743 6744/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 6745struct hwrm_queue_dscp2pri_cfg_output { 6746 __le16 error_code; 6747 __le16 req_type; 6748 __le16 seq_id; 6749 __le16 resp_len; 6750 u8 unused_0[7]; 6751 u8 valid; 6752}; 6753 6754/* hwrm_queue_pfcwd_timeout_qcaps_input (size:128b/16B) */ 6755struct hwrm_queue_pfcwd_timeout_qcaps_input { 6756 __le16 req_type; 6757 __le16 cmpl_ring; 6758 __le16 seq_id; 6759 __le16 target_id; 6760 __le64 resp_addr; 6761}; 6762 6763/* hwrm_queue_pfcwd_timeout_qcaps_output (size:128b/16B) */ 6764struct hwrm_queue_pfcwd_timeout_qcaps_output { 6765 __le16 error_code; 6766 __le16 req_type; 6767 __le16 seq_id; 6768 __le16 resp_len; 6769 __le16 max_pfcwd_timeout; 6770 u8 unused_0[5]; 6771 u8 valid; 6772}; 6773 6774/* hwrm_queue_pfcwd_timeout_cfg_input (size:192b/24B) */ 6775struct hwrm_queue_pfcwd_timeout_cfg_input { 6776 __le16 req_type; 6777 __le16 cmpl_ring; 6778 __le16 seq_id; 6779 __le16 target_id; 6780 __le64 resp_addr; 6781 __le16 pfcwd_timeout_value; 6782 u8 unused_0[6]; 6783}; 6784 6785/* hwrm_queue_pfcwd_timeout_cfg_output (size:128b/16B) */ 6786struct hwrm_queue_pfcwd_timeout_cfg_output { 6787 __le16 error_code; 6788 __le16 req_type; 6789 __le16 seq_id; 6790 __le16 resp_len; 6791 u8 unused_0[7]; 6792 u8 valid; 6793}; 6794 6795/* hwrm_queue_pfcwd_timeout_qcfg_input (size:128b/16B) */ 6796struct hwrm_queue_pfcwd_timeout_qcfg_input { 6797 __le16 req_type; 6798 __le16 cmpl_ring; 6799 __le16 seq_id; 6800 __le16 target_id; 6801 __le64 resp_addr; 6802}; 6803 6804/* hwrm_queue_pfcwd_timeout_qcfg_output (size:128b/16B) */ 6805struct hwrm_queue_pfcwd_timeout_qcfg_output { 6806 __le16 error_code; 6807 __le16 req_type; 6808 __le16 seq_id; 6809 __le16 resp_len; 6810 __le16 pfcwd_timeout_value; 6811 u8 unused_0[5]; 6812 u8 valid; 6813}; 6814 6815/* hwrm_vnic_alloc_input (size:192b/24B) */ 6816struct hwrm_vnic_alloc_input { 6817 __le16 req_type; 6818 __le16 cmpl_ring; 6819 __le16 seq_id; 6820 __le16 target_id; 6821 __le64 resp_addr; 6822 __le32 flags; 6823 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 6824 #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 6825 #define VNIC_ALLOC_REQ_FLAGS_VNIC_ID_VALID 0x4UL 6826 __le16 virtio_net_fid; 6827 __le16 vnic_id; 6828}; 6829 6830/* hwrm_vnic_alloc_output (size:128b/16B) */ 6831struct hwrm_vnic_alloc_output { 6832 __le16 error_code; 6833 __le16 req_type; 6834 __le16 seq_id; 6835 __le16 resp_len; 6836 __le32 vnic_id; 6837 u8 unused_0[3]; 6838 u8 valid; 6839}; 6840 6841/* hwrm_vnic_update_input (size:256b/32B) */ 6842struct hwrm_vnic_update_input { 6843 __le16 req_type; 6844 __le16 cmpl_ring; 6845 __le16 seq_id; 6846 __le16 target_id; 6847 __le64 resp_addr; 6848 __le32 vnic_id; 6849 __le32 enables; 6850 #define VNIC_UPDATE_REQ_ENABLES_VNIC_STATE_VALID 0x1UL 6851 #define VNIC_UPDATE_REQ_ENABLES_MRU_VALID 0x2UL 6852 #define VNIC_UPDATE_REQ_ENABLES_METADATA_FORMAT_TYPE_VALID 0x4UL 6853 u8 vnic_state; 6854 #define VNIC_UPDATE_REQ_VNIC_STATE_NORMAL 0x0UL 6855 #define VNIC_UPDATE_REQ_VNIC_STATE_DROP 0x1UL 6856 #define VNIC_UPDATE_REQ_VNIC_STATE_LAST VNIC_UPDATE_REQ_VNIC_STATE_DROP 6857 u8 metadata_format_type; 6858 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_0 0x0UL 6859 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_1 0x1UL 6860 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_2 0x2UL 6861 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_3 0x3UL 6862 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 0x4UL 6863 #define VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_LAST VNIC_UPDATE_REQ_METADATA_FORMAT_TYPE_4 6864 __le16 mru; 6865 u8 unused_1[4]; 6866}; 6867 6868/* hwrm_vnic_update_output (size:128b/16B) */ 6869struct hwrm_vnic_update_output { 6870 __le16 error_code; 6871 __le16 req_type; 6872 __le16 seq_id; 6873 __le16 resp_len; 6874 u8 unused_0[7]; 6875 u8 valid; 6876}; 6877 6878/* hwrm_vnic_free_input (size:192b/24B) */ 6879struct hwrm_vnic_free_input { 6880 __le16 req_type; 6881 __le16 cmpl_ring; 6882 __le16 seq_id; 6883 __le16 target_id; 6884 __le64 resp_addr; 6885 __le32 vnic_id; 6886 u8 unused_0[4]; 6887}; 6888 6889/* hwrm_vnic_free_output (size:128b/16B) */ 6890struct hwrm_vnic_free_output { 6891 __le16 error_code; 6892 __le16 req_type; 6893 __le16 seq_id; 6894 __le16 resp_len; 6895 u8 unused_0[7]; 6896 u8 valid; 6897}; 6898 6899/* hwrm_vnic_cfg_input (size:384b/48B) */ 6900struct hwrm_vnic_cfg_input { 6901 __le16 req_type; 6902 __le16 cmpl_ring; 6903 __le16 seq_id; 6904 __le16 target_id; 6905 __le64 resp_addr; 6906 __le32 flags; 6907 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 6908 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 6909 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 6910 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 6911 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 6912 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 6913 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 6914 #define VNIC_CFG_REQ_FLAGS_PORTCOS_MAPPING_MODE 0x80UL 6915 __le32 enables; 6916 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 6917 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 6918 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 6919 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 6920 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 6921 #define VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID 0x20UL 6922 #define VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID 0x40UL 6923 #define VNIC_CFG_REQ_ENABLES_QUEUE_ID 0x80UL 6924 #define VNIC_CFG_REQ_ENABLES_RX_CSUM_V2_MODE 0x100UL 6925 #define VNIC_CFG_REQ_ENABLES_L2_CQE_MODE 0x200UL 6926 #define VNIC_CFG_REQ_ENABLES_RAW_QP_ID 0x400UL 6927 __le16 vnic_id; 6928 __le16 dflt_ring_grp; 6929 __le16 rss_rule; 6930 __le16 cos_rule; 6931 __le16 lb_rule; 6932 __le16 mru; 6933 __le16 default_rx_ring_id; 6934 __le16 default_cmpl_ring_id; 6935 __le16 queue_id; 6936 u8 rx_csum_v2_mode; 6937 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_DEFAULT 0x0UL 6938 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_ALL_OK 0x1UL 6939 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 0x2UL 6940 #define VNIC_CFG_REQ_RX_CSUM_V2_MODE_LAST VNIC_CFG_REQ_RX_CSUM_V2_MODE_MAX 6941 u8 l2_cqe_mode; 6942 #define VNIC_CFG_REQ_L2_CQE_MODE_DEFAULT 0x0UL 6943 #define VNIC_CFG_REQ_L2_CQE_MODE_COMPRESSED 0x1UL 6944 #define VNIC_CFG_REQ_L2_CQE_MODE_MIXED 0x2UL 6945 #define VNIC_CFG_REQ_L2_CQE_MODE_LAST VNIC_CFG_REQ_L2_CQE_MODE_MIXED 6946 __le32 raw_qp_id; 6947}; 6948 6949/* hwrm_vnic_cfg_output (size:128b/16B) */ 6950struct hwrm_vnic_cfg_output { 6951 __le16 error_code; 6952 __le16 req_type; 6953 __le16 seq_id; 6954 __le16 resp_len; 6955 u8 unused_0[7]; 6956 u8 valid; 6957}; 6958 6959/* hwrm_vnic_qcaps_input (size:192b/24B) */ 6960struct hwrm_vnic_qcaps_input { 6961 __le16 req_type; 6962 __le16 cmpl_ring; 6963 __le16 seq_id; 6964 __le16 target_id; 6965 __le64 resp_addr; 6966 __le32 enables; 6967 u8 unused_0[4]; 6968}; 6969 6970/* hwrm_vnic_qcaps_output (size:192b/24B) */ 6971struct hwrm_vnic_qcaps_output { 6972 __le16 error_code; 6973 __le16 req_type; 6974 __le16 seq_id; 6975 __le16 resp_len; 6976 __le16 mru; 6977 u8 unused_0[2]; 6978 __le32 flags; 6979 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 6980 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 6981 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 6982 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 6983 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 6984 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 6985 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 6986 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 6987 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 6988 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 6989 #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 6990 #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 6991 #define VNIC_QCAPS_RESP_FLAGS_METADATA_FORMAT_CAP 0x1000UL 6992 #define VNIC_QCAPS_RESP_FLAGS_RSS_STRICT_HASH_TYPE_CAP 0x2000UL 6993 #define VNIC_QCAPS_RESP_FLAGS_RSS_HASH_TYPE_DELTA_CAP 0x4000UL 6994 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CAP 0x8000UL 6995 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_XOR_CAP 0x10000UL 6996 #define VNIC_QCAPS_RESP_FLAGS_RING_SELECT_MODE_TOEPLITZ_CHKSM_CAP 0x20000UL 6997 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPV6_FLOW_LABEL_CAP 0x40000UL 6998 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V3_CAP 0x80000UL 6999 #define VNIC_QCAPS_RESP_FLAGS_L2_CQE_MODE_CAP 0x100000UL 7000 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV4_CAP 0x200000UL 7001 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV4_CAP 0x400000UL 7002 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_AH_SPI_IPV6_CAP 0x800000UL 7003 #define VNIC_QCAPS_RESP_FLAGS_RSS_IPSEC_ESP_SPI_IPV6_CAP 0x1000000UL 7004 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_TRUSTED_VF_CAP 0x2000000UL 7005 #define VNIC_QCAPS_RESP_FLAGS_PORTCOS_MAPPING_MODE 0x4000000UL 7006 #define VNIC_QCAPS_RESP_FLAGS_RSS_PROF_TCAM_MODE_ENABLED 0x8000000UL 7007 #define VNIC_QCAPS_RESP_FLAGS_VNIC_RSS_HASH_MODE_CAP 0x10000000UL 7008 #define VNIC_QCAPS_RESP_FLAGS_HW_TUNNEL_TPA_CAP 0x20000000UL 7009 #define VNIC_QCAPS_RESP_FLAGS_RE_FLUSH_CAP 0x40000000UL 7010 __le16 max_aggs_supported; 7011 u8 unused_1[5]; 7012 u8 valid; 7013}; 7014 7015/* hwrm_vnic_tpa_cfg_input (size:384b/48B) */ 7016struct hwrm_vnic_tpa_cfg_input { 7017 __le16 req_type; 7018 __le16 cmpl_ring; 7019 __le16 seq_id; 7020 __le16 target_id; 7021 __le64 resp_addr; 7022 __le32 flags; 7023 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 7024 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 7025 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 7026 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 7027 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 7028 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 7029 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 7030 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 7031 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_PACK_AS_GRO 0x100UL 7032 __le32 enables; 7033 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 7034 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 7035 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 7036 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 7037 #define VNIC_TPA_CFG_REQ_ENABLES_TNL_TPA_EN 0x10UL 7038 __le16 vnic_id; 7039 __le16 max_agg_segs; 7040 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 7041 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 7042 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 7043 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 7044 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 7045 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 7046 __le16 max_aggs; 7047 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 7048 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 7049 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 7050 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 7051 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 7052 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 7053 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 7054 u8 unused_0[2]; 7055 __le32 max_agg_timer; 7056 __le32 min_agg_len; 7057 __le32 tnl_tpa_en_bitmap; 7058 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 7059 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 7060 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 7061 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE 0x8UL 7062 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV4 0x10UL 7063 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_IPV6 0x20UL 7064 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 7065 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 7066 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 7067 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 7068 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 7069 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 7070 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 7071 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 7072 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 7073 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 7074 #define VNIC_TPA_CFG_REQ_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 7075 u8 unused_1[4]; 7076}; 7077 7078/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 7079struct hwrm_vnic_tpa_cfg_output { 7080 __le16 error_code; 7081 __le16 req_type; 7082 __le16 seq_id; 7083 __le16 resp_len; 7084 u8 unused_0[7]; 7085 u8 valid; 7086}; 7087 7088/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 7089struct hwrm_vnic_tpa_qcfg_input { 7090 __le16 req_type; 7091 __le16 cmpl_ring; 7092 __le16 seq_id; 7093 __le16 target_id; 7094 __le64 resp_addr; 7095 __le16 vnic_id; 7096 u8 unused_0[6]; 7097}; 7098 7099/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 7100struct hwrm_vnic_tpa_qcfg_output { 7101 __le16 error_code; 7102 __le16 req_type; 7103 __le16 seq_id; 7104 __le16 resp_len; 7105 __le32 flags; 7106 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 7107 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 7108 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 7109 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 7110 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 7111 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 7112 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 7113 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 7114 __le16 max_agg_segs; 7115 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 7116 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 7117 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 7118 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 7119 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 7120 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 7121 __le16 max_aggs; 7122 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 7123 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 7124 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 7125 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 7126 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 7127 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 7128 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 7129 __le32 max_agg_timer; 7130 __le32 min_agg_len; 7131 __le32 tnl_tpa_en_bitmap; 7132 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN 0x1UL 7133 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GENEVE 0x2UL 7134 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_NVGRE 0x4UL 7135 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE 0x8UL 7136 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV4 0x10UL 7137 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_IPV6 0x20UL 7138 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_GPE 0x40UL 7139 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_VXLAN_CUST1 0x80UL 7140 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_GRE_CUST1 0x100UL 7141 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR1 0x200UL 7142 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR2 0x400UL 7143 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR3 0x800UL 7144 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR4 0x1000UL 7145 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR5 0x2000UL 7146 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR6 0x4000UL 7147 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR7 0x8000UL 7148 #define VNIC_TPA_QCFG_RESP_TNL_TPA_EN_BITMAP_UPAR8 0x10000UL 7149 u8 unused_0[3]; 7150 u8 valid; 7151}; 7152 7153/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 7154struct hwrm_vnic_rss_cfg_input { 7155 __le16 req_type; 7156 __le16 cmpl_ring; 7157 __le16 seq_id; 7158 __le16 target_id; 7159 __le64 resp_addr; 7160 __le32 hash_type; 7161 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 7162 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 7163 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 7164 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 7165 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 7166 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 7167 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 7168 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV4 0x80UL 7169 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV4 0x100UL 7170 #define VNIC_RSS_CFG_REQ_HASH_TYPE_AH_SPI_IPV6 0x200UL 7171 #define VNIC_RSS_CFG_REQ_HASH_TYPE_ESP_SPI_IPV6 0x400UL 7172 __le16 vnic_id; 7173 u8 ring_table_pair_index; 7174 u8 hash_mode_flags; 7175 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT 0x1UL 7176 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 7177 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 7178 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 7179 #define VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 7180 __le64 ring_grp_tbl_addr; 7181 __le64 hash_key_tbl_addr; 7182 __le16 rss_ctx_idx; 7183 u8 flags; 7184 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_INCLUDE 0x1UL 7185 #define VNIC_RSS_CFG_REQ_FLAGS_HASH_TYPE_EXCLUDE 0x2UL 7186 #define VNIC_RSS_CFG_REQ_FLAGS_IPSEC_HASH_TYPE_CFG_SUPPORT 0x4UL 7187 u8 ring_select_mode; 7188 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ 0x0UL 7189 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_XOR 0x1UL 7190 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 7191 #define VNIC_RSS_CFG_REQ_RING_SELECT_MODE_LAST VNIC_RSS_CFG_REQ_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 7192 u8 unused_1[4]; 7193}; 7194 7195/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 7196struct hwrm_vnic_rss_cfg_output { 7197 __le16 error_code; 7198 __le16 req_type; 7199 __le16 seq_id; 7200 __le16 resp_len; 7201 u8 unused_0[7]; 7202 u8 valid; 7203}; 7204 7205/* hwrm_vnic_rss_cfg_cmd_err (size:64b/8B) */ 7206struct hwrm_vnic_rss_cfg_cmd_err { 7207 u8 code; 7208 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7209 #define VNIC_RSS_CFG_CMD_ERR_CODE_INTERFACE_NOT_READY 0x1UL 7210 #define VNIC_RSS_CFG_CMD_ERR_CODE_UNABLE_TO_GET_RSS_CFG 0x2UL 7211 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_UNSUPPORTED 0x3UL 7212 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_TYPE_ERR 0x4UL 7213 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_MODE_FAIL 0x5UL 7214 #define VNIC_RSS_CFG_CMD_ERR_CODE_RING_GRP_TABLE_ALLOC_ERR 0x6UL 7215 #define VNIC_RSS_CFG_CMD_ERR_CODE_HASH_KEY_ALLOC_ERR 0x7UL 7216 #define VNIC_RSS_CFG_CMD_ERR_CODE_DMA_FAILED 0x8UL 7217 #define VNIC_RSS_CFG_CMD_ERR_CODE_RX_RING_ALLOC_ERR 0x9UL 7218 #define VNIC_RSS_CFG_CMD_ERR_CODE_CMPL_RING_ALLOC_ERR 0xaUL 7219 #define VNIC_RSS_CFG_CMD_ERR_CODE_HW_SET_RSS_FAILED 0xbUL 7220 #define VNIC_RSS_CFG_CMD_ERR_CODE_CTX_INVALID 0xcUL 7221 #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_INVALID 0xdUL 7222 #define VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 0xeUL 7223 #define VNIC_RSS_CFG_CMD_ERR_CODE_LAST VNIC_RSS_CFG_CMD_ERR_CODE_VNIC_RING_TABLE_PAIR_INVALID 7224 u8 unused_0[7]; 7225}; 7226 7227/* hwrm_vnic_rss_qcfg_input (size:192b/24B) */ 7228struct hwrm_vnic_rss_qcfg_input { 7229 __le16 req_type; 7230 __le16 cmpl_ring; 7231 __le16 seq_id; 7232 __le16 target_id; 7233 __le64 resp_addr; 7234 __le16 rss_ctx_idx; 7235 __le16 vnic_id; 7236 u8 unused_0[4]; 7237}; 7238 7239/* hwrm_vnic_rss_qcfg_output (size:512b/64B) */ 7240struct hwrm_vnic_rss_qcfg_output { 7241 __le16 error_code; 7242 __le16 req_type; 7243 __le16 seq_id; 7244 __le16 resp_len; 7245 __le32 hash_type; 7246 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV4 0x1UL 7247 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV4 0x2UL 7248 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV4 0x4UL 7249 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6 0x8UL 7250 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_TCP_IPV6 0x10UL 7251 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_UDP_IPV6 0x20UL 7252 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_IPV6_FLOW_LABEL 0x40UL 7253 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV4 0x80UL 7254 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV4 0x100UL 7255 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_AH_SPI_IPV6 0x200UL 7256 #define VNIC_RSS_QCFG_RESP_HASH_TYPE_ESP_SPI_IPV6 0x400UL 7257 u8 unused_0[4]; 7258 __le32 hash_key[10]; 7259 u8 hash_mode_flags; 7260 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_DEFAULT 0x1UL 7261 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_4 0x2UL 7262 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_INNERMOST_2 0x4UL 7263 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_4 0x8UL 7264 #define VNIC_RSS_QCFG_RESP_HASH_MODE_FLAGS_OUTERMOST_2 0x10UL 7265 u8 ring_select_mode; 7266 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ 0x0UL 7267 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_XOR 0x1UL 7268 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 0x2UL 7269 #define VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_LAST VNIC_RSS_QCFG_RESP_RING_SELECT_MODE_TOEPLITZ_CHECKSUM 7270 u8 unused_1[5]; 7271 u8 valid; 7272}; 7273 7274/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 7275struct hwrm_vnic_plcmodes_cfg_input { 7276 __le16 req_type; 7277 __le16 cmpl_ring; 7278 __le16 seq_id; 7279 __le16 target_id; 7280 __le64 resp_addr; 7281 __le32 flags; 7282 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 7283 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 7284 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 7285 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 7286 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 7287 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 7288 #define VNIC_PLCMODES_CFG_REQ_FLAGS_VIRTIO_PLACEMENT 0x40UL 7289 __le32 enables; 7290 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 7291 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 7292 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 7293 #define VNIC_PLCMODES_CFG_REQ_ENABLES_MAX_BDS_VALID 0x8UL 7294 __le32 vnic_id; 7295 __le16 jumbo_thresh; 7296 __le16 hds_offset; 7297 __le16 hds_threshold; 7298 __le16 max_bds; 7299 u8 unused_0[4]; 7300}; 7301 7302/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 7303struct hwrm_vnic_plcmodes_cfg_output { 7304 __le16 error_code; 7305 __le16 req_type; 7306 __le16 seq_id; 7307 __le16 resp_len; 7308 u8 unused_0[7]; 7309 u8 valid; 7310}; 7311 7312/* hwrm_vnic_plcmodes_cfg_cmd_err (size:64b/8B) */ 7313struct hwrm_vnic_plcmodes_cfg_cmd_err { 7314 u8 code; 7315 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 7316 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 0x1UL 7317 #define VNIC_PLCMODES_CFG_CMD_ERR_CODE_LAST VNIC_PLCMODES_CFG_CMD_ERR_CODE_INVALID_HDS_THRESHOLD 7318 u8 unused_0[7]; 7319}; 7320 7321/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 7322struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 7323 __le16 req_type; 7324 __le16 cmpl_ring; 7325 __le16 seq_id; 7326 __le16 target_id; 7327 __le64 resp_addr; 7328}; 7329 7330/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 7331struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 7332 __le16 error_code; 7333 __le16 req_type; 7334 __le16 seq_id; 7335 __le16 resp_len; 7336 __le16 rss_cos_lb_ctx_id; 7337 u8 unused_0[5]; 7338 u8 valid; 7339}; 7340 7341/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 7342struct hwrm_vnic_rss_cos_lb_ctx_free_input { 7343 __le16 req_type; 7344 __le16 cmpl_ring; 7345 __le16 seq_id; 7346 __le16 target_id; 7347 __le64 resp_addr; 7348 __le16 rss_cos_lb_ctx_id; 7349 u8 unused_0[6]; 7350}; 7351 7352/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 7353struct hwrm_vnic_rss_cos_lb_ctx_free_output { 7354 __le16 error_code; 7355 __le16 req_type; 7356 __le16 seq_id; 7357 __le16 resp_len; 7358 u8 unused_0[7]; 7359 u8 valid; 7360}; 7361 7362/* hwrm_ring_alloc_input (size:768b/96B) */ 7363struct hwrm_ring_alloc_input { 7364 __le16 req_type; 7365 __le16 cmpl_ring; 7366 __le16 seq_id; 7367 __le16 target_id; 7368 __le64 resp_addr; 7369 __le32 enables; 7370 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 7371 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 7372 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 7373 #define RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID 0x40UL 7374 #define RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID 0x80UL 7375 #define RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID 0x100UL 7376 #define RING_ALLOC_REQ_ENABLES_SCHQ_ID 0x200UL 7377 #define RING_ALLOC_REQ_ENABLES_MPC_CHNLS_TYPE 0x400UL 7378 #define RING_ALLOC_REQ_ENABLES_STEERING_TAG_VALID 0x800UL 7379 #define RING_ALLOC_REQ_ENABLES_RX_RATE_PROFILE_VALID 0x1000UL 7380 #define RING_ALLOC_REQ_ENABLES_DPI_VALID 0x2000UL 7381 u8 ring_type; 7382 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 7383 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 7384 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 7385 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7386 #define RING_ALLOC_REQ_RING_TYPE_RX_AGG 0x4UL 7387 #define RING_ALLOC_REQ_RING_TYPE_NQ 0x5UL 7388 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_NQ 7389 u8 cmpl_coal_cnt; 7390 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_OFF 0x0UL 7391 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_4 0x1UL 7392 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_8 0x2UL 7393 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_12 0x3UL 7394 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_16 0x4UL 7395 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_24 0x5UL 7396 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_32 0x6UL 7397 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_48 0x7UL 7398 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_64 0x8UL 7399 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_96 0x9UL 7400 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_128 0xaUL 7401 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_192 0xbUL 7402 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_256 0xcUL 7403 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_320 0xdUL 7404 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_384 0xeUL 7405 #define RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 0xfUL 7406 #define RING_ALLOC_REQ_CMPL_COAL_CNT_LAST RING_ALLOC_REQ_CMPL_COAL_CNT_COAL_MAX 7407 __le16 flags; 7408 #define RING_ALLOC_REQ_FLAGS_RX_SOP_PAD 0x1UL 7409 #define RING_ALLOC_REQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x2UL 7410 #define RING_ALLOC_REQ_FLAGS_NQ_DBR_PACING 0x4UL 7411 #define RING_ALLOC_REQ_FLAGS_TX_PKT_TS_CMPL_ENABLE 0x8UL 7412 __le64 page_tbl_addr; 7413 __le32 fbo; 7414 u8 page_size; 7415 u8 page_tbl_depth; 7416 __le16 schq_id; 7417 __le32 length; 7418 __le16 logical_id; 7419 __le16 cmpl_ring_id; 7420 __le16 queue_id; 7421 __le16 rx_buf_size; 7422 __le16 rx_ring_id; 7423 __le16 nq_ring_id; 7424 __le16 ring_arb_cfg; 7425 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 7426 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 7427 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 7428 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 7429 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 7430 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 7431 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 7432 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 7433 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 7434 __le16 steering_tag; 7435 __le32 reserved3; 7436 __le32 stat_ctx_id; 7437 __le32 reserved4; 7438 __le32 max_bw; 7439 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 7440 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 7441 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 7442 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 7443 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 7444 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 7445 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 7446 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 7447 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 7448 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 7449 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 7450 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 7451 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 7452 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 7453 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 7454 u8 int_mode; 7455 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 7456 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 7457 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 7458 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 7459 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 7460 u8 mpc_chnls_type; 7461 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TCE 0x0UL 7462 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RCE 0x1UL 7463 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_TE_CFA 0x2UL 7464 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_RE_CFA 0x3UL 7465 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 0x4UL 7466 #define RING_ALLOC_REQ_MPC_CHNLS_TYPE_LAST RING_ALLOC_REQ_MPC_CHNLS_TYPE_PRIMATE 7467 u8 rx_rate_profile_sel; 7468 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_DEFAULT 0x0UL 7469 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 0x1UL 7470 #define RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_LAST RING_ALLOC_REQ_RX_RATE_PROFILE_SEL_POLL_MODE 7471 u8 unused_4; 7472 __le64 cq_handle; 7473 __le16 dpi; 7474 __le16 unused_5[3]; 7475}; 7476 7477/* hwrm_ring_alloc_output (size:128b/16B) */ 7478struct hwrm_ring_alloc_output { 7479 __le16 error_code; 7480 __le16 req_type; 7481 __le16 seq_id; 7482 __le16 resp_len; 7483 __le16 ring_id; 7484 __le16 logical_ring_id; 7485 u8 push_buffer_index; 7486 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7487 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7488 #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7489 u8 unused_0[2]; 7490 u8 valid; 7491}; 7492 7493/* hwrm_ring_free_input (size:256b/32B) */ 7494struct hwrm_ring_free_input { 7495 __le16 req_type; 7496 __le16 cmpl_ring; 7497 __le16 seq_id; 7498 __le16 target_id; 7499 __le64 resp_addr; 7500 u8 ring_type; 7501 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 7502 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 7503 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 7504 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7505 #define RING_FREE_REQ_RING_TYPE_RX_AGG 0x4UL 7506 #define RING_FREE_REQ_RING_TYPE_NQ 0x5UL 7507 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_NQ 7508 u8 flags; 7509 #define RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 0x1UL 7510 #define RING_FREE_REQ_FLAGS_LAST RING_FREE_REQ_FLAGS_VIRTIO_RING_VALID 7511 __le16 ring_id; 7512 __le32 prod_idx; 7513 __le32 opaque; 7514 __le32 unused_1; 7515}; 7516 7517/* hwrm_ring_free_output (size:128b/16B) */ 7518struct hwrm_ring_free_output { 7519 __le16 error_code; 7520 __le16 req_type; 7521 __le16 seq_id; 7522 __le16 resp_len; 7523 u8 unused_0[7]; 7524 u8 valid; 7525}; 7526 7527/* hwrm_ring_reset_input (size:192b/24B) */ 7528struct hwrm_ring_reset_input { 7529 __le16 req_type; 7530 __le16 cmpl_ring; 7531 __le16 seq_id; 7532 __le16 target_id; 7533 __le64 resp_addr; 7534 u8 ring_type; 7535 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 7536 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 7537 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 7538 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 7539 #define RING_RESET_REQ_RING_TYPE_RX_RING_GRP 0x6UL 7540 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_RX_RING_GRP 7541 u8 unused_0; 7542 __le16 ring_id; 7543 u8 unused_1[4]; 7544}; 7545 7546/* hwrm_ring_reset_output (size:128b/16B) */ 7547struct hwrm_ring_reset_output { 7548 __le16 error_code; 7549 __le16 req_type; 7550 __le16 seq_id; 7551 __le16 resp_len; 7552 u8 push_buffer_index; 7553 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 7554 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 7555 #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 7556 u8 unused_0[3]; 7557 u8 consumer_idx[3]; 7558 u8 valid; 7559}; 7560 7561/* hwrm_ring_aggint_qcaps_input (size:128b/16B) */ 7562struct hwrm_ring_aggint_qcaps_input { 7563 __le16 req_type; 7564 __le16 cmpl_ring; 7565 __le16 seq_id; 7566 __le16 target_id; 7567 __le64 resp_addr; 7568}; 7569 7570/* hwrm_ring_aggint_qcaps_output (size:384b/48B) */ 7571struct hwrm_ring_aggint_qcaps_output { 7572 __le16 error_code; 7573 __le16 req_type; 7574 __le16 seq_id; 7575 __le16 resp_len; 7576 __le32 cmpl_params; 7577 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN 0x1UL 7578 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX 0x2UL 7579 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET 0x4UL 7580 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE 0x8UL 7581 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR 0x10UL 7582 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT 0x20UL 7583 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR 0x40UL 7584 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT 0x80UL 7585 #define RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT 0x100UL 7586 __le32 nq_params; 7587 #define RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN 0x1UL 7588 __le16 num_cmpl_dma_aggr_min; 7589 __le16 num_cmpl_dma_aggr_max; 7590 __le16 num_cmpl_dma_aggr_during_int_min; 7591 __le16 num_cmpl_dma_aggr_during_int_max; 7592 __le16 cmpl_aggr_dma_tmr_min; 7593 __le16 cmpl_aggr_dma_tmr_max; 7594 __le16 cmpl_aggr_dma_tmr_during_int_min; 7595 __le16 cmpl_aggr_dma_tmr_during_int_max; 7596 __le16 int_lat_tmr_min_min; 7597 __le16 int_lat_tmr_min_max; 7598 __le16 int_lat_tmr_max_min; 7599 __le16 int_lat_tmr_max_max; 7600 __le16 num_cmpl_aggr_int_min; 7601 __le16 num_cmpl_aggr_int_max; 7602 __le16 timer_units; 7603 u8 unused_0[1]; 7604 u8 valid; 7605}; 7606 7607/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 7608struct hwrm_ring_cmpl_ring_qaggint_params_input { 7609 __le16 req_type; 7610 __le16 cmpl_ring; 7611 __le16 seq_id; 7612 __le16 target_id; 7613 __le64 resp_addr; 7614 __le16 ring_id; 7615 __le16 flags; 7616 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_MASK 0x3UL 7617 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_UNUSED_0_SFT 0 7618 #define RING_CMPL_RING_QAGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7619 u8 unused_0[4]; 7620}; 7621 7622/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 7623struct hwrm_ring_cmpl_ring_qaggint_params_output { 7624 __le16 error_code; 7625 __le16 req_type; 7626 __le16 seq_id; 7627 __le16 resp_len; 7628 __le16 flags; 7629 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 7630 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 7631 __le16 num_cmpl_dma_aggr; 7632 __le16 num_cmpl_dma_aggr_during_int; 7633 __le16 cmpl_aggr_dma_tmr; 7634 __le16 cmpl_aggr_dma_tmr_during_int; 7635 __le16 int_lat_tmr_min; 7636 __le16 int_lat_tmr_max; 7637 __le16 num_cmpl_aggr_int; 7638 u8 unused_0[7]; 7639 u8 valid; 7640}; 7641 7642/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 7643struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 7644 __le16 req_type; 7645 __le16 cmpl_ring; 7646 __le16 seq_id; 7647 __le16 target_id; 7648 __le64 resp_addr; 7649 __le16 ring_id; 7650 __le16 flags; 7651 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 7652 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 7653 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ 0x4UL 7654 __le16 num_cmpl_dma_aggr; 7655 __le16 num_cmpl_dma_aggr_during_int; 7656 __le16 cmpl_aggr_dma_tmr; 7657 __le16 cmpl_aggr_dma_tmr_during_int; 7658 __le16 int_lat_tmr_min; 7659 __le16 int_lat_tmr_max; 7660 __le16 num_cmpl_aggr_int; 7661 __le16 enables; 7662 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR 0x1UL 7663 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT 0x2UL 7664 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR 0x4UL 7665 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN 0x8UL 7666 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX 0x10UL 7667 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT 0x20UL 7668 u8 unused_0[4]; 7669}; 7670 7671/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 7672struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 7673 __le16 error_code; 7674 __le16 req_type; 7675 __le16 seq_id; 7676 __le16 resp_len; 7677 u8 unused_0[7]; 7678 u8 valid; 7679}; 7680 7681/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 7682struct hwrm_ring_grp_alloc_input { 7683 __le16 req_type; 7684 __le16 cmpl_ring; 7685 __le16 seq_id; 7686 __le16 target_id; 7687 __le64 resp_addr; 7688 __le16 cr; 7689 __le16 rr; 7690 __le16 ar; 7691 __le16 sc; 7692}; 7693 7694/* hwrm_ring_grp_alloc_output (size:128b/16B) */ 7695struct hwrm_ring_grp_alloc_output { 7696 __le16 error_code; 7697 __le16 req_type; 7698 __le16 seq_id; 7699 __le16 resp_len; 7700 __le32 ring_group_id; 7701 u8 unused_0[3]; 7702 u8 valid; 7703}; 7704 7705/* hwrm_ring_grp_free_input (size:192b/24B) */ 7706struct hwrm_ring_grp_free_input { 7707 __le16 req_type; 7708 __le16 cmpl_ring; 7709 __le16 seq_id; 7710 __le16 target_id; 7711 __le64 resp_addr; 7712 __le32 ring_group_id; 7713 u8 unused_0[4]; 7714}; 7715 7716/* hwrm_ring_grp_free_output (size:128b/16B) */ 7717struct hwrm_ring_grp_free_output { 7718 __le16 error_code; 7719 __le16 req_type; 7720 __le16 seq_id; 7721 __le16 resp_len; 7722 u8 unused_0[7]; 7723 u8 valid; 7724}; 7725 7726#define DEFAULT_FLOW_ID 0xFFFFFFFFUL 7727#define ROCEV1_FLOW_ID 0xFFFFFFFEUL 7728#define ROCEV2_FLOW_ID 0xFFFFFFFDUL 7729#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL 7730 7731/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 7732struct hwrm_cfa_l2_filter_alloc_input { 7733 __le16 req_type; 7734 __le16 cmpl_ring; 7735 __le16 seq_id; 7736 __le16 target_id; 7737 __le64 resp_addr; 7738 __le32 flags; 7739 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 7740 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 7741 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 7742 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 7743 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 7744 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 7745 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 7746 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_MASK 0x30UL 7747 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_SFT 4 7748 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 4) 7749 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 4) 7750 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 4) 7751 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_TRAFFIC_ROCE 7752 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_XDP_DISABLE 0x40UL 7753 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_SOURCE_VALID 0x80UL 7754 __le32 enables; 7755 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 7756 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 7757 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 7758 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 7759 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 7760 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 7761 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 7762 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 7763 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 7764 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 7765 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 7766 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 7767 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 7768 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 7769 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 7770 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 7771 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 7772 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_NUM_VLANS 0x20000UL 7773 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_NUM_VLANS 0x40000UL 7774 u8 l2_addr[6]; 7775 u8 num_vlans; 7776 u8 t_num_vlans; 7777 u8 l2_addr_mask[6]; 7778 __le16 l2_ovlan; 7779 __le16 l2_ovlan_mask; 7780 __le16 l2_ivlan; 7781 __le16 l2_ivlan_mask; 7782 u8 unused_1[2]; 7783 u8 t_l2_addr[6]; 7784 u8 unused_2[2]; 7785 u8 t_l2_addr_mask[6]; 7786 __le16 t_l2_ovlan; 7787 __le16 t_l2_ovlan_mask; 7788 __le16 t_l2_ivlan; 7789 __le16 t_l2_ivlan_mask; 7790 u8 src_type; 7791 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 7792 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 7793 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 7794 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 7795 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 7796 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 7797 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 7798 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 7799 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 7800 u8 unused_3; 7801 __le32 src_id; 7802 u8 tunnel_type; 7803 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 7804 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 7805 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 7806 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 7807 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 7808 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 7809 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 7810 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 7811 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 7812 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 7813 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 7814 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 7815 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 7816 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 7817 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 7818 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 7819 u8 unused_4; 7820 __le16 dst_id; 7821 __le16 mirror_vnic_id; 7822 u8 pri_hint; 7823 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 7824 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 7825 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 7826 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 7827 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 7828 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 7829 u8 unused_5; 7830 __le32 unused_6; 7831 __le64 l2_filter_id_hint; 7832}; 7833 7834/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 7835struct hwrm_cfa_l2_filter_alloc_output { 7836 __le16 error_code; 7837 __le16 req_type; 7838 __le16 seq_id; 7839 __le16 resp_len; 7840 __le64 l2_filter_id; 7841 __le32 flow_id; 7842 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 7843 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 7844 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 7845 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 7846 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 7847 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 7848 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 7849 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 7850 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 7851 #define CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_L2_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 7852 u8 unused_0[3]; 7853 u8 valid; 7854}; 7855 7856/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 7857struct hwrm_cfa_l2_filter_free_input { 7858 __le16 req_type; 7859 __le16 cmpl_ring; 7860 __le16 seq_id; 7861 __le16 target_id; 7862 __le64 resp_addr; 7863 __le64 l2_filter_id; 7864}; 7865 7866/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 7867struct hwrm_cfa_l2_filter_free_output { 7868 __le16 error_code; 7869 __le16 req_type; 7870 __le16 seq_id; 7871 __le16 resp_len; 7872 u8 unused_0[7]; 7873 u8 valid; 7874}; 7875 7876/* hwrm_cfa_l2_filter_cfg_input (size:384b/48B) */ 7877struct hwrm_cfa_l2_filter_cfg_input { 7878 __le16 req_type; 7879 __le16 cmpl_ring; 7880 __le16 seq_id; 7881 __le16 target_id; 7882 __le64 resp_addr; 7883 __le32 flags; 7884 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 7885 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 7886 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 7887 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 7888 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 7889 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_MASK 0xcUL 7890 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_SFT 2 7891 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_NO_ROCE_L2 (0x0UL << 2) 7892 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_L2 (0x1UL << 2) 7893 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE (0x2UL << 2) 7894 #define CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_TRAFFIC_ROCE 7895 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_MASK 0x30UL 7896 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_SFT 4 7897 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_NO_UPDATE (0x0UL << 4) 7898 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_BYPASS_LKUP (0x1UL << 4) 7899 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_ENABLE_LKUP (0x2UL << 4) 7900 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP (0x3UL << 4) 7901 #define CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_REMAP_OP_RESTORE_FW_OP 7902 __le32 enables; 7903 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 7904 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 7905 #define CFA_L2_FILTER_CFG_REQ_ENABLES_PROF_FUNC 0x4UL 7906 #define CFA_L2_FILTER_CFG_REQ_ENABLES_L2_CONTEXT_ID 0x8UL 7907 __le64 l2_filter_id; 7908 __le32 dst_id; 7909 __le32 new_mirror_vnic_id; 7910 __le32 prof_func; 7911 __le32 l2_context_id; 7912}; 7913 7914/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 7915struct hwrm_cfa_l2_filter_cfg_output { 7916 __le16 error_code; 7917 __le16 req_type; 7918 __le16 seq_id; 7919 __le16 resp_len; 7920 u8 unused_0[7]; 7921 u8 valid; 7922}; 7923 7924/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 7925struct hwrm_cfa_l2_set_rx_mask_input { 7926 __le16 req_type; 7927 __le16 cmpl_ring; 7928 __le16 seq_id; 7929 __le16 target_id; 7930 __le64 resp_addr; 7931 __le32 vnic_id; 7932 __le32 mask; 7933 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 7934 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 7935 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 7936 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 7937 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 7938 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 7939 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 7940 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 7941 __le64 mc_tbl_addr; 7942 __le32 num_mc_entries; 7943 u8 unused_0[4]; 7944 __le64 vlan_tag_tbl_addr; 7945 __le32 num_vlan_tags; 7946 u8 unused_1[4]; 7947}; 7948 7949/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 7950struct hwrm_cfa_l2_set_rx_mask_output { 7951 __le16 error_code; 7952 __le16 req_type; 7953 __le16 seq_id; 7954 __le16 resp_len; 7955 u8 unused_0[7]; 7956 u8 valid; 7957}; 7958 7959/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 7960struct hwrm_cfa_l2_set_rx_mask_cmd_err { 7961 u8 code; 7962 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 7963 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 7964 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_MAX_VLAN_TAGS 0x2UL 7965 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_VNIC_ID 0x3UL 7966 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 0x4UL 7967 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_INVALID_ACTION 7968 u8 unused_0[7]; 7969}; 7970 7971/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 7972struct hwrm_cfa_tunnel_filter_alloc_input { 7973 __le16 req_type; 7974 __le16 cmpl_ring; 7975 __le16 seq_id; 7976 __le16 target_id; 7977 __le64 resp_addr; 7978 __le32 flags; 7979 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 7980 __le32 enables; 7981 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 7982 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 7983 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 7984 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 7985 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 7986 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 7987 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 7988 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 7989 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 7990 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 7991 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 7992 __le64 l2_filter_id; 7993 u8 l2_addr[6]; 7994 __le16 l2_ivlan; 7995 __le32 l3_addr[4]; 7996 __le32 t_l3_addr[4]; 7997 u8 l3_addr_type; 7998 u8 t_l3_addr_type; 7999 u8 tunnel_type; 8000 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8001 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8002 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8003 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8004 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8005 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8006 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8007 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8008 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8009 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8010 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8011 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8012 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8013 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8014 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8015 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8016 u8 tunnel_flags; 8017 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 8018 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 8019 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 8020 __le32 vni; 8021 __le32 dst_vnic_id; 8022 __le32 mirror_vnic_id; 8023}; 8024 8025/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 8026struct hwrm_cfa_tunnel_filter_alloc_output { 8027 __le16 error_code; 8028 __le16 req_type; 8029 __le16 seq_id; 8030 __le16 resp_len; 8031 __le64 tunnel_filter_id; 8032 __le32 flow_id; 8033 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8034 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8035 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8036 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8037 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8038 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 8039 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8040 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8041 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8042 #define CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_TUNNEL_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 8043 u8 unused_0[3]; 8044 u8 valid; 8045}; 8046 8047/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 8048struct hwrm_cfa_tunnel_filter_free_input { 8049 __le16 req_type; 8050 __le16 cmpl_ring; 8051 __le16 seq_id; 8052 __le16 target_id; 8053 __le64 resp_addr; 8054 __le64 tunnel_filter_id; 8055}; 8056 8057/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 8058struct hwrm_cfa_tunnel_filter_free_output { 8059 __le16 error_code; 8060 __le16 req_type; 8061 __le16 seq_id; 8062 __le16 resp_len; 8063 u8 unused_0[7]; 8064 u8 valid; 8065}; 8066 8067/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 8068struct hwrm_vxlan_ipv4_hdr { 8069 u8 ver_hlen; 8070 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 8071 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 8072 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 8073 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 8074 u8 tos; 8075 __be16 ip_id; 8076 __be16 flags_frag_offset; 8077 u8 ttl; 8078 u8 protocol; 8079 __be32 src_ip_addr; 8080 __be32 dest_ip_addr; 8081}; 8082 8083/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 8084struct hwrm_vxlan_ipv6_hdr { 8085 __be32 ver_tc_flow_label; 8086 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 8087 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 8088 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 8089 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 8090 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 8091 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 8092 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 8093 __be16 payload_len; 8094 u8 next_hdr; 8095 u8 ttl; 8096 __be32 src_ip_addr[4]; 8097 __be32 dest_ip_addr[4]; 8098}; 8099 8100/* hwrm_cfa_encap_data_vxlan (size:640b/80B) */ 8101struct hwrm_cfa_encap_data_vxlan { 8102 u8 src_mac_addr[6]; 8103 __le16 unused_0; 8104 u8 dst_mac_addr[6]; 8105 u8 num_vlan_tags; 8106 u8 unused_1; 8107 __be16 ovlan_tpid; 8108 __be16 ovlan_tci; 8109 __be16 ivlan_tpid; 8110 __be16 ivlan_tci; 8111 __le32 l3[10]; 8112 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 8113 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 8114 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 8115 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 8116 __be16 src_port; 8117 __be16 dst_port; 8118 __be32 vni; 8119 u8 hdr_rsvd0[3]; 8120 u8 hdr_rsvd1; 8121 u8 hdr_flags; 8122 u8 unused[3]; 8123}; 8124 8125/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 8126struct hwrm_cfa_encap_record_alloc_input { 8127 __le16 req_type; 8128 __le16 cmpl_ring; 8129 __le16 seq_id; 8130 __le16 target_id; 8131 __le64 resp_addr; 8132 __le32 flags; 8133 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 8134 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_EXTERNAL 0x2UL 8135 u8 encap_type; 8136 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 8137 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 8138 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 8139 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 8140 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 8141 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 8142 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 8143 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 8144 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_V4 0x9UL 8145 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE_V1 0xaUL 8146 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2_ETYPE 0xbUL 8147 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE_V6 0xcUL 8148 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 0x10UL 8149 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN_GPE 8150 u8 unused_0[3]; 8151 __le32 encap_data[20]; 8152}; 8153 8154/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 8155struct hwrm_cfa_encap_record_alloc_output { 8156 __le16 error_code; 8157 __le16 req_type; 8158 __le16 seq_id; 8159 __le16 resp_len; 8160 __le32 encap_record_id; 8161 u8 unused_0[3]; 8162 u8 valid; 8163}; 8164 8165/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 8166struct hwrm_cfa_encap_record_free_input { 8167 __le16 req_type; 8168 __le16 cmpl_ring; 8169 __le16 seq_id; 8170 __le16 target_id; 8171 __le64 resp_addr; 8172 __le32 encap_record_id; 8173 u8 unused_0[4]; 8174}; 8175 8176/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 8177struct hwrm_cfa_encap_record_free_output { 8178 __le16 error_code; 8179 __le16 req_type; 8180 __le16 seq_id; 8181 __le16 resp_len; 8182 u8 unused_0[7]; 8183 u8 valid; 8184}; 8185 8186/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 8187struct hwrm_cfa_ntuple_filter_alloc_input { 8188 __le16 req_type; 8189 __le16 cmpl_ring; 8190 __le16 seq_id; 8191 __le16 target_id; 8192 __le64 resp_addr; 8193 __le32 flags; 8194 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 8195 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 8196 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 8197 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_FID 0x8UL 8198 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_ARP_REPLY 0x10UL 8199 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX 0x20UL 8200 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_NO_L2_CONTEXT 0x40UL 8201 __le32 enables; 8202 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 8203 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 8204 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 8205 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 8206 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 8207 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 8208 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 8209 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 8210 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 8211 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 8212 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 8213 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 8214 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 8215 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 8216 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 8217 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 8218 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 8219 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 8220 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 8221 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_RFS_RING_TBL_IDX 0x80000UL 8222 __le64 l2_filter_id; 8223 u8 src_macaddr[6]; 8224 __be16 ethertype; 8225 u8 ip_addr_type; 8226 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8227 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8228 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8229 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8230 u8 ip_protocol; 8231 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8232 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8233 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8234 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMP 0x1UL 8235 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_ICMPV6 0x3aUL 8236 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 0xffUL 8237 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_RSVD 8238 __le16 dst_id; 8239 __le16 rfs_ring_tbl_idx; 8240 u8 tunnel_type; 8241 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8242 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8243 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8244 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8245 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8246 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8247 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8248 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8249 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8250 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8251 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8252 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8253 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8254 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8255 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8256 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8257 u8 pri_hint; 8258 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 8259 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 8260 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 8261 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 8262 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 8263 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 8264 __be32 src_ipaddr[4]; 8265 __be32 src_ipaddr_mask[4]; 8266 __be32 dst_ipaddr[4]; 8267 __be32 dst_ipaddr_mask[4]; 8268 __be16 src_port; 8269 __be16 src_port_mask; 8270 __be16 dst_port; 8271 __be16 dst_port_mask; 8272 __le64 ntuple_filter_id_hint; 8273}; 8274 8275/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 8276struct hwrm_cfa_ntuple_filter_alloc_output { 8277 __le16 error_code; 8278 __le16 req_type; 8279 __le16 seq_id; 8280 __le16 resp_len; 8281 __le64 ntuple_filter_id; 8282 __le32 flow_id; 8283 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8284 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8285 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8286 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8287 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8288 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_TYPE_EXT 8289 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8290 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8291 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8292 #define CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_NTUPLE_FILTER_ALLOC_RESP_FLOW_ID_DIR_TX 8293 u8 unused_0[3]; 8294 u8 valid; 8295}; 8296 8297/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 8298struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 8299 u8 code; 8300 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8301 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_MAC 0x65UL 8302 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_BC_MC_MAC 0x66UL 8303 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_VNIC 0x67UL 8304 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_PF_FID 0x68UL 8305 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L2_CTXT_ID 0x69UL 8306 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_CTXT_CFG 0x6aUL 8307 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_NULL_L2_DATA_FLD 0x6bUL 8308 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_CFA_LAYOUT 0x6cUL 8309 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_CTXT_ALLOC_FAIL 0x6dUL 8310 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ROCE_FLOW_ERR 0x6eUL 8311 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_OWNER_FID 0x6fUL 8312 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ZERO_REF_CNT 0x70UL 8313 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_FLOW_TYPE 0x71UL 8314 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_IVLAN 0x72UL 8315 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_MAX_VLAN_ID 0x73UL 8316 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_TNL_REQ 0x74UL 8317 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_ADDR 0x75UL 8318 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L2_IVLAN 0x76UL 8319 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR 0x77UL 8320 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_L3_ADDR_TYPE 0x78UL 8321 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_T_L3_ADDR_TYPE 0x79UL 8322 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DST_VNIC_ID 0x7aUL 8323 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VNI 0x7bUL 8324 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_DST_ID 0x7cUL 8325 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_FAIL_ROCE_L2_FLOW 0x7dUL 8326 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_NPAR_VLAN 0x7eUL 8327 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_ATSP_ADD 0x7fUL 8328 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_DFLT_VLAN_FAIL 0x80UL 8329 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_INVALID_L3_TYPE 0x81UL 8330 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 0x82UL 8331 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_VAL_FAIL_TNL_FLOW 8332 u8 unused_0[7]; 8333}; 8334 8335/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 8336struct hwrm_cfa_ntuple_filter_free_input { 8337 __le16 req_type; 8338 __le16 cmpl_ring; 8339 __le16 seq_id; 8340 __le16 target_id; 8341 __le64 resp_addr; 8342 __le64 ntuple_filter_id; 8343}; 8344 8345/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 8346struct hwrm_cfa_ntuple_filter_free_output { 8347 __le16 error_code; 8348 __le16 req_type; 8349 __le16 seq_id; 8350 __le16 resp_len; 8351 u8 unused_0[7]; 8352 u8 valid; 8353}; 8354 8355/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 8356struct hwrm_cfa_ntuple_filter_cfg_input { 8357 __le16 req_type; 8358 __le16 cmpl_ring; 8359 __le16 seq_id; 8360 __le16 target_id; 8361 __le64 resp_addr; 8362 __le32 enables; 8363 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 8364 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 8365 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 8366 __le32 flags; 8367 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_FID 0x1UL 8368 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_DEST_RFS_RING_IDX 0x2UL 8369 #define CFA_NTUPLE_FILTER_CFG_REQ_FLAGS_NO_L2_CONTEXT 0x4UL 8370 __le64 ntuple_filter_id; 8371 __le32 new_dst_id; 8372 __le32 new_mirror_vnic_id; 8373 __le16 new_meter_instance_id; 8374 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 8375 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 8376 u8 unused_1[6]; 8377}; 8378 8379/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 8380struct hwrm_cfa_ntuple_filter_cfg_output { 8381 __le16 error_code; 8382 __le16 req_type; 8383 __le16 seq_id; 8384 __le16 resp_len; 8385 u8 unused_0[7]; 8386 u8 valid; 8387}; 8388 8389/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 8390struct hwrm_cfa_decap_filter_alloc_input { 8391 __le16 req_type; 8392 __le16 cmpl_ring; 8393 __le16 seq_id; 8394 __le16 target_id; 8395 __le64 resp_addr; 8396 __le32 flags; 8397 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 8398 __le32 enables; 8399 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 8400 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 8401 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 8402 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 8403 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 8404 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 8405 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 8406 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 8407 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 8408 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 8409 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 8410 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 8411 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 8412 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 8413 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 8414 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 8415 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 8416 __be32 tunnel_id; 8417 u8 tunnel_type; 8418 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8419 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8420 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8421 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8422 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8423 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8424 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8425 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8426 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8427 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8428 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8429 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8430 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8431 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8432 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8433 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8434 u8 unused_0; 8435 __le16 unused_1; 8436 u8 src_macaddr[6]; 8437 u8 unused_2[2]; 8438 u8 dst_macaddr[6]; 8439 __be16 ovlan_vid; 8440 __be16 ivlan_vid; 8441 __be16 t_ovlan_vid; 8442 __be16 t_ivlan_vid; 8443 __be16 ethertype; 8444 u8 ip_addr_type; 8445 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 8446 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 8447 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 8448 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 8449 u8 ip_protocol; 8450 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 8451 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 8452 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 8453 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 8454 __le16 unused_3; 8455 __le32 unused_4; 8456 __be32 src_ipaddr[4]; 8457 __be32 dst_ipaddr[4]; 8458 __be16 src_port; 8459 __be16 dst_port; 8460 __le16 dst_id; 8461 __le16 l2_ctxt_ref_id; 8462}; 8463 8464/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 8465struct hwrm_cfa_decap_filter_alloc_output { 8466 __le16 error_code; 8467 __le16 req_type; 8468 __le16 seq_id; 8469 __le16 resp_len; 8470 __le32 decap_filter_id; 8471 u8 unused_0[3]; 8472 u8 valid; 8473}; 8474 8475/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 8476struct hwrm_cfa_decap_filter_free_input { 8477 __le16 req_type; 8478 __le16 cmpl_ring; 8479 __le16 seq_id; 8480 __le16 target_id; 8481 __le64 resp_addr; 8482 __le32 decap_filter_id; 8483 u8 unused_0[4]; 8484}; 8485 8486/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 8487struct hwrm_cfa_decap_filter_free_output { 8488 __le16 error_code; 8489 __le16 req_type; 8490 __le16 seq_id; 8491 __le16 resp_len; 8492 u8 unused_0[7]; 8493 u8 valid; 8494}; 8495 8496/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 8497struct hwrm_cfa_flow_alloc_input { 8498 __le16 req_type; 8499 __le16 cmpl_ring; 8500 __le16 seq_id; 8501 __le16 target_id; 8502 __le64 resp_addr; 8503 __le16 flags; 8504 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 8505 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 8506 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 8507 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 8508 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 8509 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 8510 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 8511 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 8512 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 8513 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 8514 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 8515 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 8516 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 8517 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_TX 0x40UL 8518 #define CFA_FLOW_ALLOC_REQ_FLAGS_PATH_RX 0x80UL 8519 #define CFA_FLOW_ALLOC_REQ_FLAGS_MATCH_VXLAN_IP_VNI 0x100UL 8520 #define CFA_FLOW_ALLOC_REQ_FLAGS_VHOST_ID_USE_VLAN 0x200UL 8521 __le16 src_fid; 8522 __le32 tunnel_handle; 8523 __le16 action_flags; 8524 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 8525 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 8526 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 8527 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 8528 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 8529 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 8530 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 8531 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 8532 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 8533 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 8534 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL_IP 0x400UL 8535 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FLOW_AGING_ENABLED 0x800UL 8536 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_PRI_HINT 0x1000UL 8537 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC 0x2000UL 8538 __le16 dst_fid; 8539 __be16 l2_rewrite_vlan_tpid; 8540 __be16 l2_rewrite_vlan_tci; 8541 __le16 act_meter_id; 8542 __le16 ref_flow_handle; 8543 __be16 ethertype; 8544 __be16 outer_vlan_tci; 8545 __be16 dmac[3]; 8546 __be16 inner_vlan_tci; 8547 __be16 smac[3]; 8548 u8 ip_dst_mask_len; 8549 u8 ip_src_mask_len; 8550 __be32 ip_dst[4]; 8551 __be32 ip_src[4]; 8552 __be16 l4_src_port; 8553 __be16 l4_src_port_mask; 8554 __be16 l4_dst_port; 8555 __be16 l4_dst_port_mask; 8556 __be32 nat_ip_address[4]; 8557 __be16 l2_rewrite_dmac[3]; 8558 __be16 nat_port; 8559 __be16 l2_rewrite_smac[3]; 8560 u8 ip_proto; 8561 u8 tunnel_type; 8562 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 8563 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8564 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 8565 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 8566 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 8567 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8568 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 8569 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 8570 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 8571 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8572 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8573 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8574 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 8575 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 8576 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 8577 #define CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_FLOW_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 8578}; 8579 8580/* hwrm_cfa_flow_alloc_output (size:256b/32B) */ 8581struct hwrm_cfa_flow_alloc_output { 8582 __le16 error_code; 8583 __le16 req_type; 8584 __le16 seq_id; 8585 __le16 resp_len; 8586 __le16 flow_handle; 8587 u8 unused_0[2]; 8588 __le32 flow_id; 8589 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_MASK 0x3fffffffUL 8590 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_VALUE_SFT 0 8591 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE 0x40000000UL 8592 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_INT (0x0UL << 30) 8593 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT (0x1UL << 30) 8594 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_TYPE_EXT 8595 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR 0x80000000UL 8596 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_RX (0x0UL << 31) 8597 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX (0x1UL << 31) 8598 #define CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_LAST CFA_FLOW_ALLOC_RESP_FLOW_ID_DIR_TX 8599 __le64 ext_flow_handle; 8600 __le32 flow_counter_id; 8601 u8 unused_1[3]; 8602 u8 valid; 8603}; 8604 8605/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */ 8606struct hwrm_cfa_flow_alloc_cmd_err { 8607 u8 code; 8608 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 8609 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM 0x1UL 8610 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD 0x2UL 8611 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER 0x3UL 8612 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM 0x4UL 8613 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION 0x5UL 8614 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS 0x6UL 8615 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 0x7UL 8616 #define CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB 8617 u8 unused_0[7]; 8618}; 8619 8620/* hwrm_cfa_flow_free_input (size:256b/32B) */ 8621struct hwrm_cfa_flow_free_input { 8622 __le16 req_type; 8623 __le16 cmpl_ring; 8624 __le16 seq_id; 8625 __le16 target_id; 8626 __le64 resp_addr; 8627 __le16 flow_handle; 8628 __le16 unused_0; 8629 __le32 flow_counter_id; 8630 __le64 ext_flow_handle; 8631}; 8632 8633/* hwrm_cfa_flow_free_output (size:256b/32B) */ 8634struct hwrm_cfa_flow_free_output { 8635 __le16 error_code; 8636 __le16 req_type; 8637 __le16 seq_id; 8638 __le16 resp_len; 8639 __le64 packet; 8640 __le64 byte; 8641 u8 unused_0[7]; 8642 u8 valid; 8643}; 8644 8645/* hwrm_cfa_flow_info_input (size:256b/32B) */ 8646struct hwrm_cfa_flow_info_input { 8647 __le16 req_type; 8648 __le16 cmpl_ring; 8649 __le16 seq_id; 8650 __le16 target_id; 8651 __le64 resp_addr; 8652 __le16 flow_handle; 8653 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_MAX_MASK 0xfffUL 8654 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT 0x1000UL 8655 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT 0x2000UL 8656 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_TX 0x3000UL 8657 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT 0x4000UL 8658 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_DIR_RX 0x8000UL 8659 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_CNP_CNT_RX 0x9000UL 8660 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV1_CNT_RX 0xa000UL 8661 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_NIC_RX 0xb000UL 8662 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 0xc000UL 8663 #define CFA_FLOW_INFO_REQ_FLOW_HANDLE_LAST CFA_FLOW_INFO_REQ_FLOW_HANDLE_ROCEV2_CNT_RX 8664 u8 unused_0[6]; 8665 __le64 ext_flow_handle; 8666}; 8667 8668/* hwrm_cfa_flow_info_output (size:5632b/704B) */ 8669struct hwrm_cfa_flow_info_output { 8670 __le16 error_code; 8671 __le16 req_type; 8672 __le16 seq_id; 8673 __le16 resp_len; 8674 u8 flags; 8675 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_TX 0x1UL 8676 #define CFA_FLOW_INFO_RESP_FLAGS_PATH_RX 0x2UL 8677 u8 profile; 8678 __le16 src_fid; 8679 __le16 dst_fid; 8680 __le16 l2_ctxt_id; 8681 __le64 em_info; 8682 __le64 tcam_info; 8683 __le64 vfp_tcam_info; 8684 __le16 ar_id; 8685 __le16 flow_handle; 8686 __le32 tunnel_handle; 8687 __le16 flow_timer; 8688 u8 unused_0[6]; 8689 __le32 flow_key_data[130]; 8690 __le32 flow_action_info[30]; 8691 u8 unused_1[7]; 8692 u8 valid; 8693}; 8694 8695/* hwrm_cfa_flow_stats_input (size:640b/80B) */ 8696struct hwrm_cfa_flow_stats_input { 8697 __le16 req_type; 8698 __le16 cmpl_ring; 8699 __le16 seq_id; 8700 __le16 target_id; 8701 __le64 resp_addr; 8702 __le16 num_flows; 8703 __le16 flow_handle_0; 8704 __le16 flow_handle_1; 8705 __le16 flow_handle_2; 8706 __le16 flow_handle_3; 8707 __le16 flow_handle_4; 8708 __le16 flow_handle_5; 8709 __le16 flow_handle_6; 8710 __le16 flow_handle_7; 8711 __le16 flow_handle_8; 8712 __le16 flow_handle_9; 8713 u8 unused_0[2]; 8714 __le32 flow_id_0; 8715 __le32 flow_id_1; 8716 __le32 flow_id_2; 8717 __le32 flow_id_3; 8718 __le32 flow_id_4; 8719 __le32 flow_id_5; 8720 __le32 flow_id_6; 8721 __le32 flow_id_7; 8722 __le32 flow_id_8; 8723 __le32 flow_id_9; 8724}; 8725 8726/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 8727struct hwrm_cfa_flow_stats_output { 8728 __le16 error_code; 8729 __le16 req_type; 8730 __le16 seq_id; 8731 __le16 resp_len; 8732 __le64 packet_0; 8733 __le64 packet_1; 8734 __le64 packet_2; 8735 __le64 packet_3; 8736 __le64 packet_4; 8737 __le64 packet_5; 8738 __le64 packet_6; 8739 __le64 packet_7; 8740 __le64 packet_8; 8741 __le64 packet_9; 8742 __le64 byte_0; 8743 __le64 byte_1; 8744 __le64 byte_2; 8745 __le64 byte_3; 8746 __le64 byte_4; 8747 __le64 byte_5; 8748 __le64 byte_6; 8749 __le64 byte_7; 8750 __le64 byte_8; 8751 __le64 byte_9; 8752 __le16 flow_hits; 8753 u8 unused_0[5]; 8754 u8 valid; 8755}; 8756 8757/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 8758struct hwrm_cfa_vfr_alloc_input { 8759 __le16 req_type; 8760 __le16 cmpl_ring; 8761 __le16 seq_id; 8762 __le16 target_id; 8763 __le64 resp_addr; 8764 __le16 vf_id; 8765 __le16 reserved; 8766 u8 unused_0[4]; 8767 char vfr_name[32]; 8768}; 8769 8770/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 8771struct hwrm_cfa_vfr_alloc_output { 8772 __le16 error_code; 8773 __le16 req_type; 8774 __le16 seq_id; 8775 __le16 resp_len; 8776 __le16 rx_cfa_code; 8777 __le16 tx_cfa_action; 8778 u8 unused_0[3]; 8779 u8 valid; 8780}; 8781 8782/* hwrm_cfa_vfr_free_input (size:448b/56B) */ 8783struct hwrm_cfa_vfr_free_input { 8784 __le16 req_type; 8785 __le16 cmpl_ring; 8786 __le16 seq_id; 8787 __le16 target_id; 8788 __le64 resp_addr; 8789 char vfr_name[32]; 8790 __le16 vf_id; 8791 __le16 reserved; 8792 u8 unused_0[4]; 8793}; 8794 8795/* hwrm_cfa_vfr_free_output (size:128b/16B) */ 8796struct hwrm_cfa_vfr_free_output { 8797 __le16 error_code; 8798 __le16 req_type; 8799 __le16 seq_id; 8800 __le16 resp_len; 8801 u8 unused_0[7]; 8802 u8 valid; 8803}; 8804 8805/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */ 8806struct hwrm_cfa_eem_qcaps_input { 8807 __le16 req_type; 8808 __le16 cmpl_ring; 8809 __le16 seq_id; 8810 __le16 target_id; 8811 __le64 resp_addr; 8812 __le32 flags; 8813 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_TX 0x1UL 8814 #define CFA_EEM_QCAPS_REQ_FLAGS_PATH_RX 0x2UL 8815 #define CFA_EEM_QCAPS_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8816 __le32 unused_0; 8817}; 8818 8819/* hwrm_cfa_eem_qcaps_output (size:320b/40B) */ 8820struct hwrm_cfa_eem_qcaps_output { 8821 __le16 error_code; 8822 __le16 req_type; 8823 __le16 seq_id; 8824 __le16 resp_len; 8825 __le32 flags; 8826 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_TX 0x1UL 8827 #define CFA_EEM_QCAPS_RESP_FLAGS_PATH_RX 0x2UL 8828 #define CFA_EEM_QCAPS_RESP_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x4UL 8829 #define CFA_EEM_QCAPS_RESP_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED 0x8UL 8830 __le32 unused_0; 8831 __le32 supported; 8832 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY0_TABLE 0x1UL 8833 #define CFA_EEM_QCAPS_RESP_SUPPORTED_KEY1_TABLE 0x2UL 8834 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_RECORD_TABLE 0x4UL 8835 #define CFA_EEM_QCAPS_RESP_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE 0x8UL 8836 #define CFA_EEM_QCAPS_RESP_SUPPORTED_FID_TABLE 0x10UL 8837 __le32 max_entries_supported; 8838 __le16 key_entry_size; 8839 __le16 record_entry_size; 8840 __le16 efc_entry_size; 8841 __le16 fid_entry_size; 8842 u8 unused_1[7]; 8843 u8 valid; 8844}; 8845 8846/* hwrm_cfa_eem_cfg_input (size:384b/48B) */ 8847struct hwrm_cfa_eem_cfg_input { 8848 __le16 req_type; 8849 __le16 cmpl_ring; 8850 __le16 seq_id; 8851 __le16 target_id; 8852 __le64 resp_addr; 8853 __le32 flags; 8854 #define CFA_EEM_CFG_REQ_FLAGS_PATH_TX 0x1UL 8855 #define CFA_EEM_CFG_REQ_FLAGS_PATH_RX 0x2UL 8856 #define CFA_EEM_CFG_REQ_FLAGS_PREFERRED_OFFLOAD 0x4UL 8857 #define CFA_EEM_CFG_REQ_FLAGS_SECONDARY_PF 0x8UL 8858 __le16 group_id; 8859 __le16 unused_0; 8860 __le32 num_entries; 8861 __le32 unused_1; 8862 __le16 key0_ctx_id; 8863 __le16 key1_ctx_id; 8864 __le16 record_ctx_id; 8865 __le16 efc_ctx_id; 8866 __le16 fid_ctx_id; 8867 __le16 unused_2; 8868 __le32 unused_3; 8869}; 8870 8871/* hwrm_cfa_eem_cfg_output (size:128b/16B) */ 8872struct hwrm_cfa_eem_cfg_output { 8873 __le16 error_code; 8874 __le16 req_type; 8875 __le16 seq_id; 8876 __le16 resp_len; 8877 u8 unused_0[7]; 8878 u8 valid; 8879}; 8880 8881/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */ 8882struct hwrm_cfa_eem_qcfg_input { 8883 __le16 req_type; 8884 __le16 cmpl_ring; 8885 __le16 seq_id; 8886 __le16 target_id; 8887 __le64 resp_addr; 8888 __le32 flags; 8889 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_TX 0x1UL 8890 #define CFA_EEM_QCFG_REQ_FLAGS_PATH_RX 0x2UL 8891 __le32 unused_0; 8892}; 8893 8894/* hwrm_cfa_eem_qcfg_output (size:256b/32B) */ 8895struct hwrm_cfa_eem_qcfg_output { 8896 __le16 error_code; 8897 __le16 req_type; 8898 __le16 seq_id; 8899 __le16 resp_len; 8900 __le32 flags; 8901 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_TX 0x1UL 8902 #define CFA_EEM_QCFG_RESP_FLAGS_PATH_RX 0x2UL 8903 #define CFA_EEM_QCFG_RESP_FLAGS_PREFERRED_OFFLOAD 0x4UL 8904 __le32 num_entries; 8905 __le16 key0_ctx_id; 8906 __le16 key1_ctx_id; 8907 __le16 record_ctx_id; 8908 __le16 efc_ctx_id; 8909 __le16 fid_ctx_id; 8910 u8 unused_2[5]; 8911 u8 valid; 8912}; 8913 8914/* hwrm_cfa_eem_op_input (size:192b/24B) */ 8915struct hwrm_cfa_eem_op_input { 8916 __le16 req_type; 8917 __le16 cmpl_ring; 8918 __le16 seq_id; 8919 __le16 target_id; 8920 __le64 resp_addr; 8921 __le32 flags; 8922 #define CFA_EEM_OP_REQ_FLAGS_PATH_TX 0x1UL 8923 #define CFA_EEM_OP_REQ_FLAGS_PATH_RX 0x2UL 8924 __le16 unused_0; 8925 __le16 op; 8926 #define CFA_EEM_OP_REQ_OP_RESERVED 0x0UL 8927 #define CFA_EEM_OP_REQ_OP_EEM_DISABLE 0x1UL 8928 #define CFA_EEM_OP_REQ_OP_EEM_ENABLE 0x2UL 8929 #define CFA_EEM_OP_REQ_OP_EEM_CLEANUP 0x3UL 8930 #define CFA_EEM_OP_REQ_OP_LAST CFA_EEM_OP_REQ_OP_EEM_CLEANUP 8931}; 8932 8933/* hwrm_cfa_eem_op_output (size:128b/16B) */ 8934struct hwrm_cfa_eem_op_output { 8935 __le16 error_code; 8936 __le16 req_type; 8937 __le16 seq_id; 8938 __le16 resp_len; 8939 u8 unused_0[7]; 8940 u8 valid; 8941}; 8942 8943/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */ 8944struct hwrm_cfa_adv_flow_mgnt_qcaps_input { 8945 __le16 req_type; 8946 __le16 cmpl_ring; 8947 __le16 seq_id; 8948 __le16 target_id; 8949 __le64 resp_addr; 8950 __le32 unused_0[4]; 8951}; 8952 8953/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */ 8954struct hwrm_cfa_adv_flow_mgnt_qcaps_output { 8955 __le16 error_code; 8956 __le16 req_type; 8957 __le16 seq_id; 8958 __le16 resp_len; 8959 __le32 flags; 8960 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 8961 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 8962 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 8963 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 8964 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 8965 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 8966 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 8967 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 8968 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 8969 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 8970 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 8971 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 8972 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 8973 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 8974 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 8975 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 8976 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 8977 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_LAG_SUPPORTED 0x20000UL 8978 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_NO_L2CTX_SUPPORTED 0x40000UL 8979 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NIC_FLOW_STATS_SUPPORTED 0x80000UL 8980 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_EXT_IP_PROTO_SUPPORTED 0x100000UL 8981 #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V3_SUPPORTED 0x200000UL 8982 u8 unused_0[3]; 8983 u8 valid; 8984}; 8985 8986/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 8987struct hwrm_tunnel_dst_port_query_input { 8988 __le16 req_type; 8989 __le16 cmpl_ring; 8990 __le16 seq_id; 8991 __le16 target_id; 8992 __le64 resp_addr; 8993 u8 tunnel_type; 8994 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 8995 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 8996 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 8997 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 8998 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 8999 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9000 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9001 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9002 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_SRV6 0xfUL 9003 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9004 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GRE 0x11UL 9005 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9006 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9007 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9008 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9009 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9010 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9011 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9012 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9013 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9014 u8 tunnel_next_proto; 9015 u8 unused_0[6]; 9016}; 9017 9018/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 9019struct hwrm_tunnel_dst_port_query_output { 9020 __le16 error_code; 9021 __le16 req_type; 9022 __le16 seq_id; 9023 __le16 resp_len; 9024 __le16 tunnel_dst_port_id; 9025 __be16 tunnel_dst_port_val; 9026 u8 upar_in_use; 9027 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR0 0x1UL 9028 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR1 0x2UL 9029 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR2 0x4UL 9030 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR3 0x8UL 9031 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR4 0x10UL 9032 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR5 0x20UL 9033 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR6 0x40UL 9034 #define TUNNEL_DST_PORT_QUERY_RESP_UPAR_IN_USE_UPAR7 0x80UL 9035 u8 status; 9036 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_CHIP_LEVEL 0x1UL 9037 #define TUNNEL_DST_PORT_QUERY_RESP_STATUS_FUNC_LEVEL 0x2UL 9038 u8 unused_0; 9039 u8 valid; 9040}; 9041 9042/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 9043struct hwrm_tunnel_dst_port_alloc_input { 9044 __le16 req_type; 9045 __le16 cmpl_ring; 9046 __le16 seq_id; 9047 __le16 target_id; 9048 __le64 resp_addr; 9049 u8 tunnel_type; 9050 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 9051 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 9052 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 9053 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 9054 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 9055 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9056 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9057 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9058 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_SRV6 0xfUL 9059 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9060 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GRE 0x11UL 9061 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9062 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9063 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9064 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9065 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9066 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9067 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9068 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9069 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9070 u8 tunnel_next_proto; 9071 __be16 tunnel_dst_port_val; 9072 u8 unused_0[4]; 9073}; 9074 9075/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 9076struct hwrm_tunnel_dst_port_alloc_output { 9077 __le16 error_code; 9078 __le16 req_type; 9079 __le16 seq_id; 9080 __le16 resp_len; 9081 __le16 tunnel_dst_port_id; 9082 u8 error_info; 9083 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_SUCCESS 0x0UL 9084 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ALLOCATED 0x1UL 9085 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_NO_RESOURCE 0x2UL 9086 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 0x3UL 9087 #define TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_ALLOC_RESP_ERROR_INFO_ERR_ENABLED 9088 u8 upar_in_use; 9089 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR0 0x1UL 9090 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR1 0x2UL 9091 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR2 0x4UL 9092 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR3 0x8UL 9093 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR4 0x10UL 9094 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR5 0x20UL 9095 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR6 0x40UL 9096 #define TUNNEL_DST_PORT_ALLOC_RESP_UPAR_IN_USE_UPAR7 0x80UL 9097 u8 unused_0[3]; 9098 u8 valid; 9099}; 9100 9101/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 9102struct hwrm_tunnel_dst_port_free_input { 9103 __le16 req_type; 9104 __le16 cmpl_ring; 9105 __le16 seq_id; 9106 __le16 target_id; 9107 __le64 resp_addr; 9108 u8 tunnel_type; 9109 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 9110 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 9111 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 9112 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_IPGRE_V1 0xaUL 9113 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_L2_ETYPE 0xbUL 9114 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE_V6 0xcUL 9115 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_CUSTOM_GRE 0xdUL 9116 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ECPRI 0xeUL 9117 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_SRV6 0xfUL 9118 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_GPE 0x10UL 9119 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GRE 0x11UL 9120 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR 0x12UL 9121 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES01 0x13UL 9122 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES02 0x14UL 9123 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES03 0x15UL 9124 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES04 0x16UL 9125 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES05 0x17UL 9126 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES06 0x18UL 9127 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 0x19UL 9128 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_ULP_DYN_UPAR_RES07 9129 u8 tunnel_next_proto; 9130 __le16 tunnel_dst_port_id; 9131 u8 unused_0[4]; 9132}; 9133 9134/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 9135struct hwrm_tunnel_dst_port_free_output { 9136 __le16 error_code; 9137 __le16 req_type; 9138 __le16 seq_id; 9139 __le16 resp_len; 9140 u8 error_info; 9141 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_SUCCESS 0x0UL 9142 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_OWNER 0x1UL 9143 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 0x2UL 9144 #define TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_LAST TUNNEL_DST_PORT_FREE_RESP_ERROR_INFO_ERR_NOT_ALLOCATED 9145 u8 unused_1[6]; 9146 u8 valid; 9147}; 9148 9149/* ctx_hw_stats (size:1280b/160B) */ 9150struct ctx_hw_stats { 9151 __le64 rx_ucast_pkts; 9152 __le64 rx_mcast_pkts; 9153 __le64 rx_bcast_pkts; 9154 __le64 rx_discard_pkts; 9155 __le64 rx_error_pkts; 9156 __le64 rx_ucast_bytes; 9157 __le64 rx_mcast_bytes; 9158 __le64 rx_bcast_bytes; 9159 __le64 tx_ucast_pkts; 9160 __le64 tx_mcast_pkts; 9161 __le64 tx_bcast_pkts; 9162 __le64 tx_error_pkts; 9163 __le64 tx_discard_pkts; 9164 __le64 tx_ucast_bytes; 9165 __le64 tx_mcast_bytes; 9166 __le64 tx_bcast_bytes; 9167 __le64 tpa_pkts; 9168 __le64 tpa_bytes; 9169 __le64 tpa_events; 9170 __le64 tpa_aborts; 9171}; 9172 9173/* ctx_hw_stats_ext (size:1408b/176B) */ 9174struct ctx_hw_stats_ext { 9175 __le64 rx_ucast_pkts; 9176 __le64 rx_mcast_pkts; 9177 __le64 rx_bcast_pkts; 9178 __le64 rx_discard_pkts; 9179 __le64 rx_error_pkts; 9180 __le64 rx_ucast_bytes; 9181 __le64 rx_mcast_bytes; 9182 __le64 rx_bcast_bytes; 9183 __le64 tx_ucast_pkts; 9184 __le64 tx_mcast_pkts; 9185 __le64 tx_bcast_pkts; 9186 __le64 tx_error_pkts; 9187 __le64 tx_discard_pkts; 9188 __le64 tx_ucast_bytes; 9189 __le64 tx_mcast_bytes; 9190 __le64 tx_bcast_bytes; 9191 __le64 rx_tpa_eligible_pkt; 9192 __le64 rx_tpa_eligible_bytes; 9193 __le64 rx_tpa_pkt; 9194 __le64 rx_tpa_bytes; 9195 __le64 rx_tpa_errors; 9196 __le64 rx_tpa_events; 9197}; 9198 9199/* hwrm_stat_ctx_alloc_input (size:384b/48B) */ 9200struct hwrm_stat_ctx_alloc_input { 9201 __le16 req_type; 9202 __le16 cmpl_ring; 9203 __le16 seq_id; 9204 __le16 target_id; 9205 __le64 resp_addr; 9206 __le64 stats_dma_addr; 9207 __le32 update_period_ms; 9208 u8 stat_ctx_flags; 9209 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 9210 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_DUP_HOST_BUF 0x2UL 9211 u8 unused_0; 9212 __le16 stats_dma_length; 9213 __le16 flags; 9214 #define STAT_CTX_ALLOC_REQ_FLAGS_STEERING_TAG_VALID 0x1UL 9215 __le16 steering_tag; 9216 __le32 stat_ctx_id; 9217 __le16 alloc_seq_id; 9218 u8 unused_1[6]; 9219}; 9220 9221/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 9222struct hwrm_stat_ctx_alloc_output { 9223 __le16 error_code; 9224 __le16 req_type; 9225 __le16 seq_id; 9226 __le16 resp_len; 9227 __le32 stat_ctx_id; 9228 u8 unused_0[3]; 9229 u8 valid; 9230}; 9231 9232/* hwrm_stat_ctx_free_input (size:192b/24B) */ 9233struct hwrm_stat_ctx_free_input { 9234 __le16 req_type; 9235 __le16 cmpl_ring; 9236 __le16 seq_id; 9237 __le16 target_id; 9238 __le64 resp_addr; 9239 __le32 stat_ctx_id; 9240 u8 unused_0[4]; 9241}; 9242 9243/* hwrm_stat_ctx_free_output (size:128b/16B) */ 9244struct hwrm_stat_ctx_free_output { 9245 __le16 error_code; 9246 __le16 req_type; 9247 __le16 seq_id; 9248 __le16 resp_len; 9249 __le32 stat_ctx_id; 9250 u8 unused_0[3]; 9251 u8 valid; 9252}; 9253 9254/* hwrm_stat_ctx_query_input (size:192b/24B) */ 9255struct hwrm_stat_ctx_query_input { 9256 __le16 req_type; 9257 __le16 cmpl_ring; 9258 __le16 seq_id; 9259 __le16 target_id; 9260 __le64 resp_addr; 9261 __le32 stat_ctx_id; 9262 u8 flags; 9263 #define STAT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 9264 u8 unused_0[3]; 9265}; 9266 9267/* hwrm_stat_ctx_query_output (size:1408b/176B) */ 9268struct hwrm_stat_ctx_query_output { 9269 __le16 error_code; 9270 __le16 req_type; 9271 __le16 seq_id; 9272 __le16 resp_len; 9273 __le64 tx_ucast_pkts; 9274 __le64 tx_mcast_pkts; 9275 __le64 tx_bcast_pkts; 9276 __le64 tx_discard_pkts; 9277 __le64 tx_error_pkts; 9278 __le64 tx_ucast_bytes; 9279 __le64 tx_mcast_bytes; 9280 __le64 tx_bcast_bytes; 9281 __le64 rx_ucast_pkts; 9282 __le64 rx_mcast_pkts; 9283 __le64 rx_bcast_pkts; 9284 __le64 rx_discard_pkts; 9285 __le64 rx_error_pkts; 9286 __le64 rx_ucast_bytes; 9287 __le64 rx_mcast_bytes; 9288 __le64 rx_bcast_bytes; 9289 __le64 rx_agg_pkts; 9290 __le64 rx_agg_bytes; 9291 __le64 rx_agg_events; 9292 __le64 rx_agg_aborts; 9293 u8 unused_0[7]; 9294 u8 valid; 9295}; 9296 9297/* hwrm_stat_ext_ctx_query_input (size:192b/24B) */ 9298struct hwrm_stat_ext_ctx_query_input { 9299 __le16 req_type; 9300 __le16 cmpl_ring; 9301 __le16 seq_id; 9302 __le16 target_id; 9303 __le64 resp_addr; 9304 __le32 stat_ctx_id; 9305 u8 flags; 9306 #define STAT_EXT_CTX_QUERY_REQ_FLAGS_COUNTER_MASK 0x1UL 9307 u8 unused_0[3]; 9308}; 9309 9310/* hwrm_stat_ext_ctx_query_output (size:1536b/192B) */ 9311struct hwrm_stat_ext_ctx_query_output { 9312 __le16 error_code; 9313 __le16 req_type; 9314 __le16 seq_id; 9315 __le16 resp_len; 9316 __le64 rx_ucast_pkts; 9317 __le64 rx_mcast_pkts; 9318 __le64 rx_bcast_pkts; 9319 __le64 rx_discard_pkts; 9320 __le64 rx_error_pkts; 9321 __le64 rx_ucast_bytes; 9322 __le64 rx_mcast_bytes; 9323 __le64 rx_bcast_bytes; 9324 __le64 tx_ucast_pkts; 9325 __le64 tx_mcast_pkts; 9326 __le64 tx_bcast_pkts; 9327 __le64 tx_error_pkts; 9328 __le64 tx_discard_pkts; 9329 __le64 tx_ucast_bytes; 9330 __le64 tx_mcast_bytes; 9331 __le64 tx_bcast_bytes; 9332 __le64 rx_tpa_eligible_pkt; 9333 __le64 rx_tpa_eligible_bytes; 9334 __le64 rx_tpa_pkt; 9335 __le64 rx_tpa_bytes; 9336 __le64 rx_tpa_errors; 9337 __le64 rx_tpa_events; 9338 u8 unused_0[7]; 9339 u8 valid; 9340}; 9341 9342/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 9343struct hwrm_stat_ctx_clr_stats_input { 9344 __le16 req_type; 9345 __le16 cmpl_ring; 9346 __le16 seq_id; 9347 __le16 target_id; 9348 __le64 resp_addr; 9349 __le32 stat_ctx_id; 9350 u8 unused_0[4]; 9351}; 9352 9353/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 9354struct hwrm_stat_ctx_clr_stats_output { 9355 __le16 error_code; 9356 __le16 req_type; 9357 __le16 seq_id; 9358 __le16 resp_len; 9359 u8 unused_0[7]; 9360 u8 valid; 9361}; 9362 9363/* hwrm_pcie_qstats_input (size:256b/32B) */ 9364struct hwrm_pcie_qstats_input { 9365 __le16 req_type; 9366 __le16 cmpl_ring; 9367 __le16 seq_id; 9368 __le16 target_id; 9369 __le64 resp_addr; 9370 __le16 pcie_stat_size; 9371 u8 unused_0[6]; 9372 __le64 pcie_stat_host_addr; 9373}; 9374 9375/* hwrm_pcie_qstats_output (size:128b/16B) */ 9376struct hwrm_pcie_qstats_output { 9377 __le16 error_code; 9378 __le16 req_type; 9379 __le16 seq_id; 9380 __le16 resp_len; 9381 __le16 pcie_stat_size; 9382 u8 unused_0[5]; 9383 u8 valid; 9384}; 9385 9386/* pcie_ctx_hw_stats (size:768b/96B) */ 9387struct pcie_ctx_hw_stats { 9388 __le64 pcie_pl_signal_integrity; 9389 __le64 pcie_dl_signal_integrity; 9390 __le64 pcie_tl_signal_integrity; 9391 __le64 pcie_link_integrity; 9392 __le64 pcie_tx_traffic_rate; 9393 __le64 pcie_rx_traffic_rate; 9394 __le64 pcie_tx_dllp_statistics; 9395 __le64 pcie_rx_dllp_statistics; 9396 __le64 pcie_equalization_time; 9397 __le32 pcie_ltssm_histogram[4]; 9398 __le64 pcie_recovery_histogram; 9399}; 9400 9401/* pcie_ctx_hw_stats_v2 (size:4544b/568B) */ 9402struct pcie_ctx_hw_stats_v2 { 9403 __le64 pcie_pl_signal_integrity; 9404 __le64 pcie_dl_signal_integrity; 9405 __le64 pcie_tl_signal_integrity; 9406 __le64 pcie_link_integrity; 9407 __le64 pcie_tx_traffic_rate; 9408 __le64 pcie_rx_traffic_rate; 9409 __le64 pcie_tx_dllp_statistics; 9410 __le64 pcie_rx_dllp_statistics; 9411 __le64 pcie_equalization_time; 9412 __le32 pcie_ltssm_histogram[4]; 9413 __le64 pcie_recovery_histogram; 9414 __le32 pcie_tl_credit_nph_histogram[8]; 9415 __le32 pcie_tl_credit_ph_histogram[8]; 9416 __le32 pcie_tl_credit_pd_histogram[8]; 9417 __le32 pcie_cmpl_latest_times[4]; 9418 __le32 pcie_cmpl_longest_time; 9419 __le32 pcie_cmpl_shortest_time; 9420 __le32 unused_0[2]; 9421 __le32 pcie_cmpl_latest_headers[4][4]; 9422 __le32 pcie_cmpl_longest_headers[4][4]; 9423 __le32 pcie_cmpl_shortest_headers[4][4]; 9424 __le32 pcie_wr_latency_histogram[12]; 9425 __le32 pcie_wr_latency_all_normal_count; 9426 __le32 unused_1; 9427 __le64 pcie_posted_packet_count; 9428 __le64 pcie_non_posted_packet_count; 9429 __le64 pcie_other_packet_count; 9430 __le64 pcie_blocked_packet_count; 9431 __le64 pcie_cmpl_packet_count; 9432 __le32 pcie_rd_latency_histogram[12]; 9433 __le32 pcie_rd_latency_all_normal_count; 9434 __le32 unused_2; 9435}; 9436 9437/* hwrm_stat_generic_qstats_input (size:256b/32B) */ 9438struct hwrm_stat_generic_qstats_input { 9439 __le16 req_type; 9440 __le16 cmpl_ring; 9441 __le16 seq_id; 9442 __le16 target_id; 9443 __le64 resp_addr; 9444 __le16 generic_stat_size; 9445 u8 flags; 9446 #define STAT_GENERIC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x1UL 9447 u8 unused_0[5]; 9448 __le64 generic_stat_host_addr; 9449}; 9450 9451/* hwrm_stat_generic_qstats_output (size:128b/16B) */ 9452struct hwrm_stat_generic_qstats_output { 9453 __le16 error_code; 9454 __le16 req_type; 9455 __le16 seq_id; 9456 __le16 resp_len; 9457 __le16 generic_stat_size; 9458 u8 unused_0[5]; 9459 u8 valid; 9460}; 9461 9462/* generic_sw_hw_stats (size:1472b/184B) */ 9463struct generic_sw_hw_stats { 9464 __le64 pcie_statistics_tx_tlp; 9465 __le64 pcie_statistics_rx_tlp; 9466 __le64 pcie_credit_fc_hdr_posted; 9467 __le64 pcie_credit_fc_hdr_nonposted; 9468 __le64 pcie_credit_fc_hdr_cmpl; 9469 __le64 pcie_credit_fc_data_posted; 9470 __le64 pcie_credit_fc_data_nonposted; 9471 __le64 pcie_credit_fc_data_cmpl; 9472 __le64 pcie_credit_fc_tgt_nonposted; 9473 __le64 pcie_credit_fc_tgt_data_posted; 9474 __le64 pcie_credit_fc_tgt_hdr_posted; 9475 __le64 pcie_credit_fc_cmpl_hdr_posted; 9476 __le64 pcie_credit_fc_cmpl_data_posted; 9477 __le64 pcie_cmpl_longest; 9478 __le64 pcie_cmpl_shortest; 9479 __le64 cache_miss_count_cfcq; 9480 __le64 cache_miss_count_cfcs; 9481 __le64 cache_miss_count_cfcc; 9482 __le64 cache_miss_count_cfcm; 9483 __le64 hw_db_recov_dbs_dropped; 9484 __le64 hw_db_recov_drops_serviced; 9485 __le64 hw_db_recov_dbs_recovered; 9486 __le64 hw_db_recov_oo_drop_count; 9487}; 9488 9489/* hwrm_fw_reset_input (size:192b/24B) */ 9490struct hwrm_fw_reset_input { 9491 __le16 req_type; 9492 __le16 cmpl_ring; 9493 __le16 seq_id; 9494 __le16 target_id; 9495 __le64 resp_addr; 9496 u8 embedded_proc_type; 9497 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9498 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9499 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9500 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9501 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9502 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9503 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9504 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 9505 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 0x8UL 9506 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_IMPACTLESS_ACTIVATION 9507 u8 selfrst_status; 9508 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 9509 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 9510 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9511 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9512 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTIMMEDIATE 9513 u8 host_idx; 9514 u8 flags; 9515 #define FW_RESET_REQ_FLAGS_RESET_GRACEFUL 0x1UL 9516 #define FW_RESET_REQ_FLAGS_FW_ACTIVATION 0x2UL 9517 u8 unused_0[4]; 9518}; 9519 9520/* hwrm_fw_reset_output (size:128b/16B) */ 9521struct hwrm_fw_reset_output { 9522 __le16 error_code; 9523 __le16 req_type; 9524 __le16 seq_id; 9525 __le16 resp_len; 9526 u8 selfrst_status; 9527 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9528 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9529 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9530 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 0x3UL 9531 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTIMMEDIATE 9532 u8 unused_0[6]; 9533 u8 valid; 9534}; 9535 9536/* hwrm_fw_qstatus_input (size:192b/24B) */ 9537struct hwrm_fw_qstatus_input { 9538 __le16 req_type; 9539 __le16 cmpl_ring; 9540 __le16 seq_id; 9541 __le16 target_id; 9542 __le64 resp_addr; 9543 u8 embedded_proc_type; 9544 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 9545 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 9546 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 9547 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 9548 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 9549 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 9550 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 9551 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 9552 u8 unused_0[7]; 9553}; 9554 9555/* hwrm_fw_qstatus_output (size:128b/16B) */ 9556struct hwrm_fw_qstatus_output { 9557 __le16 error_code; 9558 __le16 req_type; 9559 __le16 seq_id; 9560 __le16 resp_len; 9561 u8 selfrst_status; 9562 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 9563 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 9564 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 9565 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 0x3UL 9566 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPOWER 9567 u8 nvm_option_action_status; 9568 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_NONE 0x0UL 9569 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_HOTRESET 0x1UL 9570 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_WARMBOOT 0x2UL 9571 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 0x3UL 9572 #define FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_LAST FW_QSTATUS_RESP_NVM_OPTION_ACTION_STATUS_NVMOPT_ACTION_COLDBOOT 9573 u8 unused_0[5]; 9574 u8 valid; 9575}; 9576 9577/* hwrm_fw_set_time_input (size:256b/32B) */ 9578struct hwrm_fw_set_time_input { 9579 __le16 req_type; 9580 __le16 cmpl_ring; 9581 __le16 seq_id; 9582 __le16 target_id; 9583 __le64 resp_addr; 9584 __le16 year; 9585 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 9586 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 9587 u8 month; 9588 u8 day; 9589 u8 hour; 9590 u8 minute; 9591 u8 second; 9592 u8 unused_0; 9593 __le16 millisecond; 9594 __le16 zone; 9595 #define FW_SET_TIME_REQ_ZONE_UTC 0 9596 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 65535 9597 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 9598 u8 unused_1[4]; 9599}; 9600 9601/* hwrm_fw_set_time_output (size:128b/16B) */ 9602struct hwrm_fw_set_time_output { 9603 __le16 error_code; 9604 __le16 req_type; 9605 __le16 seq_id; 9606 __le16 resp_len; 9607 u8 unused_0[7]; 9608 u8 valid; 9609}; 9610 9611/* hwrm_struct_hdr (size:128b/16B) */ 9612struct hwrm_struct_hdr { 9613 __le16 struct_id; 9614 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 9615 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 9616 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 9617 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 9618 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 9619 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 9620 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 9621 #define STRUCT_HDR_STRUCT_ID_POWER_BKUP 0x427UL 9622 #define STRUCT_HDR_STRUCT_ID_PEER_MMAP 0x429UL 9623 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 9624 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 9625 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 9626 #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 9627 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_COUNT 0x12cUL 9628 #define STRUCT_HDR_STRUCT_ID_UDCC_RTT_BUCKET_BOUND 0x12dUL 9629 #define STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 0x190UL 9630 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_DBG_TOKEN_CLAIMS 9631 __le16 len; 9632 u8 version; 9633 #define STRUCT_HDR_VERSION_0 0x0UL 9634 #define STRUCT_HDR_VERSION_1 0x1UL 9635 #define STRUCT_HDR_VERSION_LAST STRUCT_HDR_VERSION_1 9636 u8 count; 9637 __le16 subtype; 9638 __le16 next_offset; 9639 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 9640 u8 unused_0[6]; 9641}; 9642 9643/* hwrm_struct_data_dcbx_app (size:64b/8B) */ 9644struct hwrm_struct_data_dcbx_app { 9645 __be16 protocol_id; 9646 u8 protocol_selector; 9647 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 9648 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 9649 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 9650 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 9651 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 9652 u8 priority; 9653 u8 valid; 9654 u8 unused_0[3]; 9655}; 9656 9657/* hwrm_fw_set_structured_data_input (size:256b/32B) */ 9658struct hwrm_fw_set_structured_data_input { 9659 __le16 req_type; 9660 __le16 cmpl_ring; 9661 __le16 seq_id; 9662 __le16 target_id; 9663 __le64 resp_addr; 9664 __le64 src_data_addr; 9665 __le16 data_len; 9666 u8 hdr_cnt; 9667 u8 unused_0[5]; 9668}; 9669 9670/* hwrm_fw_set_structured_data_output (size:128b/16B) */ 9671struct hwrm_fw_set_structured_data_output { 9672 __le16 error_code; 9673 __le16 req_type; 9674 __le16 seq_id; 9675 __le16 resp_len; 9676 u8 unused_0[7]; 9677 u8 valid; 9678}; 9679 9680/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 9681struct hwrm_fw_set_structured_data_cmd_err { 9682 u8 code; 9683 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9684 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 9685 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 9686 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9687 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_ALREADY_ADDED 0x4UL 9688 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 0x5UL 9689 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_INST_IN_PROG 9690 u8 unused_0[7]; 9691}; 9692 9693/* hwrm_fw_get_structured_data_input (size:256b/32B) */ 9694struct hwrm_fw_get_structured_data_input { 9695 __le16 req_type; 9696 __le16 cmpl_ring; 9697 __le16 seq_id; 9698 __le16 target_id; 9699 __le64 resp_addr; 9700 __le64 dest_data_addr; 9701 __le16 data_len; 9702 __le16 structure_id; 9703 __le16 subtype; 9704 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 9705 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 9706 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 9707 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 9708 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 9709 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 9710 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 9711 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 9712 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 9713 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_SUPPORTED 0x320UL 9714 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 0x321UL 9715 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_CLAIMS_ACTIVE 9716 u8 count; 9717 u8 unused_0; 9718}; 9719 9720/* hwrm_fw_get_structured_data_output (size:128b/16B) */ 9721struct hwrm_fw_get_structured_data_output { 9722 __le16 error_code; 9723 __le16 req_type; 9724 __le16 seq_id; 9725 __le16 resp_len; 9726 u8 hdr_cnt; 9727 u8 unused_0[6]; 9728 u8 valid; 9729}; 9730 9731/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 9732struct hwrm_fw_get_structured_data_cmd_err { 9733 u8 code; 9734 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 9735 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 9736 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 9737 u8 unused_0[7]; 9738}; 9739 9740/* hwrm_fw_livepatch_query_input (size:192b/24B) */ 9741struct hwrm_fw_livepatch_query_input { 9742 __le16 req_type; 9743 __le16 cmpl_ring; 9744 __le16 seq_id; 9745 __le16 target_id; 9746 __le64 resp_addr; 9747 u8 fw_target; 9748 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_COMMON_FW 0x1UL 9749 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 0x2UL 9750 #define FW_LIVEPATCH_QUERY_REQ_FW_TARGET_LAST FW_LIVEPATCH_QUERY_REQ_FW_TARGET_SECURE_FW 9751 u8 unused_0[7]; 9752}; 9753 9754/* hwrm_fw_livepatch_query_output (size:640b/80B) */ 9755struct hwrm_fw_livepatch_query_output { 9756 __le16 error_code; 9757 __le16 req_type; 9758 __le16 seq_id; 9759 __le16 resp_len; 9760 char install_ver[32]; 9761 char active_ver[32]; 9762 __le16 status_flags; 9763 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_INSTALL 0x1UL 9764 #define FW_LIVEPATCH_QUERY_RESP_STATUS_FLAGS_ACTIVE 0x2UL 9765 u8 unused_0[5]; 9766 u8 valid; 9767}; 9768 9769/* hwrm_fw_livepatch_input (size:256b/32B) */ 9770struct hwrm_fw_livepatch_input { 9771 __le16 req_type; 9772 __le16 cmpl_ring; 9773 __le16 seq_id; 9774 __le16 target_id; 9775 __le64 resp_addr; 9776 u8 opcode; 9777 #define FW_LIVEPATCH_REQ_OPCODE_ACTIVATE 0x1UL 9778 #define FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 0x2UL 9779 #define FW_LIVEPATCH_REQ_OPCODE_LAST FW_LIVEPATCH_REQ_OPCODE_DEACTIVATE 9780 u8 fw_target; 9781 #define FW_LIVEPATCH_REQ_FW_TARGET_COMMON_FW 0x1UL 9782 #define FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 0x2UL 9783 #define FW_LIVEPATCH_REQ_FW_TARGET_LAST FW_LIVEPATCH_REQ_FW_TARGET_SECURE_FW 9784 u8 loadtype; 9785 #define FW_LIVEPATCH_REQ_LOADTYPE_NVM_INSTALL 0x1UL 9786 #define FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 0x2UL 9787 #define FW_LIVEPATCH_REQ_LOADTYPE_LAST FW_LIVEPATCH_REQ_LOADTYPE_MEMORY_DIRECT 9788 u8 flags; 9789 __le32 patch_len; 9790 __le64 host_addr; 9791}; 9792 9793/* hwrm_fw_livepatch_output (size:128b/16B) */ 9794struct hwrm_fw_livepatch_output { 9795 __le16 error_code; 9796 __le16 req_type; 9797 __le16 seq_id; 9798 __le16 resp_len; 9799 u8 unused_0[7]; 9800 u8 valid; 9801}; 9802 9803/* hwrm_fw_livepatch_cmd_err (size:64b/8B) */ 9804struct hwrm_fw_livepatch_cmd_err { 9805 u8 code; 9806 #define FW_LIVEPATCH_CMD_ERR_CODE_UNKNOWN 0x0UL 9807 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_OPCODE 0x1UL 9808 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_TARGET 0x2UL 9809 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_SUPPORTED 0x3UL 9810 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_INSTALLED 0x4UL 9811 #define FW_LIVEPATCH_CMD_ERR_CODE_NOT_PATCHED 0x5UL 9812 #define FW_LIVEPATCH_CMD_ERR_CODE_AUTH_FAIL 0x6UL 9813 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_HEADER 0x7UL 9814 #define FW_LIVEPATCH_CMD_ERR_CODE_INVALID_SIZE 0x8UL 9815 #define FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 0x9UL 9816 #define FW_LIVEPATCH_CMD_ERR_CODE_LAST FW_LIVEPATCH_CMD_ERR_CODE_ALREADY_PATCHED 9817 u8 unused_0[7]; 9818}; 9819 9820/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 9821struct hwrm_exec_fwd_resp_input { 9822 __le16 req_type; 9823 __le16 cmpl_ring; 9824 __le16 seq_id; 9825 __le16 target_id; 9826 __le64 resp_addr; 9827 __le32 encap_request[26]; 9828 __le16 encap_resp_target_id; 9829 u8 unused_0[6]; 9830}; 9831 9832/* hwrm_exec_fwd_resp_output (size:128b/16B) */ 9833struct hwrm_exec_fwd_resp_output { 9834 __le16 error_code; 9835 __le16 req_type; 9836 __le16 seq_id; 9837 __le16 resp_len; 9838 u8 unused_0[7]; 9839 u8 valid; 9840}; 9841 9842/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 9843struct hwrm_reject_fwd_resp_input { 9844 __le16 req_type; 9845 __le16 cmpl_ring; 9846 __le16 seq_id; 9847 __le16 target_id; 9848 __le64 resp_addr; 9849 __le32 encap_request[26]; 9850 __le16 encap_resp_target_id; 9851 u8 unused_0[6]; 9852}; 9853 9854/* hwrm_reject_fwd_resp_output (size:128b/16B) */ 9855struct hwrm_reject_fwd_resp_output { 9856 __le16 error_code; 9857 __le16 req_type; 9858 __le16 seq_id; 9859 __le16 resp_len; 9860 u8 unused_0[7]; 9861 u8 valid; 9862}; 9863 9864/* hwrm_fwd_resp_input (size:1024b/128B) */ 9865struct hwrm_fwd_resp_input { 9866 __le16 req_type; 9867 __le16 cmpl_ring; 9868 __le16 seq_id; 9869 __le16 target_id; 9870 __le64 resp_addr; 9871 __le16 encap_resp_target_id; 9872 __le16 encap_resp_cmpl_ring; 9873 __le16 encap_resp_len; 9874 u8 unused_0; 9875 u8 unused_1; 9876 __le64 encap_resp_addr; 9877 __le32 encap_resp[24]; 9878}; 9879 9880/* hwrm_fwd_resp_output (size:128b/16B) */ 9881struct hwrm_fwd_resp_output { 9882 __le16 error_code; 9883 __le16 req_type; 9884 __le16 seq_id; 9885 __le16 resp_len; 9886 u8 unused_0[7]; 9887 u8 valid; 9888}; 9889 9890/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 9891struct hwrm_fwd_async_event_cmpl_input { 9892 __le16 req_type; 9893 __le16 cmpl_ring; 9894 __le16 seq_id; 9895 __le16 target_id; 9896 __le64 resp_addr; 9897 __le16 encap_async_event_target_id; 9898 u8 unused_0[6]; 9899 __le32 encap_async_event_cmpl[4]; 9900}; 9901 9902/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 9903struct hwrm_fwd_async_event_cmpl_output { 9904 __le16 error_code; 9905 __le16 req_type; 9906 __le16 seq_id; 9907 __le16 resp_len; 9908 u8 unused_0[7]; 9909 u8 valid; 9910}; 9911 9912/* hwrm_temp_monitor_query_input (size:128b/16B) */ 9913struct hwrm_temp_monitor_query_input { 9914 __le16 req_type; 9915 __le16 cmpl_ring; 9916 __le16 seq_id; 9917 __le16 target_id; 9918 __le64 resp_addr; 9919}; 9920 9921/* hwrm_temp_monitor_query_output (size:192b/24B) */ 9922struct hwrm_temp_monitor_query_output { 9923 __le16 error_code; 9924 __le16 req_type; 9925 __le16 seq_id; 9926 __le16 resp_len; 9927 u8 temp; 9928 u8 phy_temp; 9929 u8 om_temp; 9930 u8 flags; 9931 #define TEMP_MONITOR_QUERY_RESP_FLAGS_TEMP_NOT_AVAILABLE 0x1UL 9932 #define TEMP_MONITOR_QUERY_RESP_FLAGS_PHY_TEMP_NOT_AVAILABLE 0x2UL 9933 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_NOT_PRESENT 0x4UL 9934 #define TEMP_MONITOR_QUERY_RESP_FLAGS_OM_TEMP_NOT_AVAILABLE 0x8UL 9935 #define TEMP_MONITOR_QUERY_RESP_FLAGS_EXT_TEMP_FIELDS_AVAILABLE 0x10UL 9936 #define TEMP_MONITOR_QUERY_RESP_FLAGS_THRESHOLD_VALUES_AVAILABLE 0x20UL 9937 u8 temp2; 9938 u8 phy_temp2; 9939 u8 om_temp2; 9940 u8 warn_threshold; 9941 u8 critical_threshold; 9942 u8 fatal_threshold; 9943 u8 shutdown_threshold; 9944 u8 unused_0[4]; 9945 u8 valid; 9946}; 9947 9948/* hwrm_wol_filter_alloc_input (size:512b/64B) */ 9949struct hwrm_wol_filter_alloc_input { 9950 __le16 req_type; 9951 __le16 cmpl_ring; 9952 __le16 seq_id; 9953 __le16 target_id; 9954 __le64 resp_addr; 9955 __le32 flags; 9956 __le32 enables; 9957 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 9958 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 9959 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 9960 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 9961 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 9962 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 9963 __le16 port_id; 9964 u8 wol_type; 9965 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 9966 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 9967 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 9968 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 9969 u8 unused_0[5]; 9970 u8 mac_address[6]; 9971 __le16 pattern_offset; 9972 __le16 pattern_buf_size; 9973 __le16 pattern_mask_size; 9974 u8 unused_1[4]; 9975 __le64 pattern_buf_addr; 9976 __le64 pattern_mask_addr; 9977}; 9978 9979/* hwrm_wol_filter_alloc_output (size:128b/16B) */ 9980struct hwrm_wol_filter_alloc_output { 9981 __le16 error_code; 9982 __le16 req_type; 9983 __le16 seq_id; 9984 __le16 resp_len; 9985 u8 wol_filter_id; 9986 u8 unused_0[6]; 9987 u8 valid; 9988}; 9989 9990/* hwrm_wol_filter_free_input (size:256b/32B) */ 9991struct hwrm_wol_filter_free_input { 9992 __le16 req_type; 9993 __le16 cmpl_ring; 9994 __le16 seq_id; 9995 __le16 target_id; 9996 __le64 resp_addr; 9997 __le32 flags; 9998 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 9999 __le32 enables; 10000 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 10001 __le16 port_id; 10002 u8 wol_filter_id; 10003 u8 unused_0[5]; 10004}; 10005 10006/* hwrm_wol_filter_free_output (size:128b/16B) */ 10007struct hwrm_wol_filter_free_output { 10008 __le16 error_code; 10009 __le16 req_type; 10010 __le16 seq_id; 10011 __le16 resp_len; 10012 u8 unused_0[7]; 10013 u8 valid; 10014}; 10015 10016/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 10017struct hwrm_wol_filter_qcfg_input { 10018 __le16 req_type; 10019 __le16 cmpl_ring; 10020 __le16 seq_id; 10021 __le16 target_id; 10022 __le64 resp_addr; 10023 __le16 port_id; 10024 __le16 handle; 10025 u8 unused_0[4]; 10026 __le64 pattern_buf_addr; 10027 __le16 pattern_buf_size; 10028 u8 unused_1[6]; 10029 __le64 pattern_mask_addr; 10030 __le16 pattern_mask_size; 10031 u8 unused_2[6]; 10032}; 10033 10034/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 10035struct hwrm_wol_filter_qcfg_output { 10036 __le16 error_code; 10037 __le16 req_type; 10038 __le16 seq_id; 10039 __le16 resp_len; 10040 __le16 next_handle; 10041 u8 wol_filter_id; 10042 u8 wol_type; 10043 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 10044 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 10045 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 10046 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 10047 __le32 unused_0; 10048 u8 mac_address[6]; 10049 __le16 pattern_offset; 10050 __le16 pattern_size; 10051 __le16 pattern_mask_size; 10052 u8 unused_1[3]; 10053 u8 valid; 10054}; 10055 10056/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 10057struct hwrm_wol_reason_qcfg_input { 10058 __le16 req_type; 10059 __le16 cmpl_ring; 10060 __le16 seq_id; 10061 __le16 target_id; 10062 __le64 resp_addr; 10063 __le16 port_id; 10064 u8 unused_0[6]; 10065 __le64 wol_pkt_buf_addr; 10066 __le16 wol_pkt_buf_size; 10067 u8 unused_1[6]; 10068}; 10069 10070/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 10071struct hwrm_wol_reason_qcfg_output { 10072 __le16 error_code; 10073 __le16 req_type; 10074 __le16 seq_id; 10075 __le16 resp_len; 10076 u8 wol_filter_id; 10077 u8 wol_reason; 10078 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 10079 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 10080 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 10081 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 10082 u8 wol_pkt_len; 10083 u8 unused_0[4]; 10084 u8 valid; 10085}; 10086 10087/* hwrm_dbg_read_direct_input (size:256b/32B) */ 10088struct hwrm_dbg_read_direct_input { 10089 __le16 req_type; 10090 __le16 cmpl_ring; 10091 __le16 seq_id; 10092 __le16 target_id; 10093 __le64 resp_addr; 10094 __le64 host_dest_addr; 10095 __le32 read_addr; 10096 __le32 read_len32; 10097}; 10098 10099/* hwrm_dbg_read_direct_output (size:128b/16B) */ 10100struct hwrm_dbg_read_direct_output { 10101 __le16 error_code; 10102 __le16 req_type; 10103 __le16 seq_id; 10104 __le16 resp_len; 10105 __le32 crc32; 10106 u8 unused_0[3]; 10107 u8 valid; 10108}; 10109 10110/* hwrm_dbg_qcaps_input (size:192b/24B) */ 10111struct hwrm_dbg_qcaps_input { 10112 __le16 req_type; 10113 __le16 cmpl_ring; 10114 __le16 seq_id; 10115 __le16 target_id; 10116 __le64 resp_addr; 10117 __le16 fid; 10118 u8 unused_0[6]; 10119}; 10120 10121/* hwrm_dbg_qcaps_output (size:192b/24B) */ 10122struct hwrm_dbg_qcaps_output { 10123 __le16 error_code; 10124 __le16 req_type; 10125 __le16 seq_id; 10126 __le16 resp_len; 10127 __le16 fid; 10128 u8 unused_0[2]; 10129 __le32 coredump_component_disable_caps; 10130 #define DBG_QCAPS_RESP_COREDUMP_COMPONENT_DISABLE_CAPS_NVRAM 0x1UL 10131 __le32 flags; 10132 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_NVM 0x1UL 10133 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_HOST_DDR 0x2UL 10134 #define DBG_QCAPS_RESP_FLAGS_CRASHDUMP_SOC_DDR 0x4UL 10135 #define DBG_QCAPS_RESP_FLAGS_USEQ 0x8UL 10136 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_DDR 0x10UL 10137 #define DBG_QCAPS_RESP_FLAGS_COREDUMP_HOST_CAPTURE 0x20UL 10138 #define DBG_QCAPS_RESP_FLAGS_PTRACE 0x40UL 10139 #define DBG_QCAPS_RESP_FLAGS_REG_ACCESS_RESTRICTED 0x80UL 10140 u8 unused_1[3]; 10141 u8 valid; 10142}; 10143 10144/* hwrm_dbg_qcfg_input (size:192b/24B) */ 10145struct hwrm_dbg_qcfg_input { 10146 __le16 req_type; 10147 __le16 cmpl_ring; 10148 __le16 seq_id; 10149 __le16 target_id; 10150 __le64 resp_addr; 10151 __le16 fid; 10152 __le16 flags; 10153 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_MASK 0x3UL 10154 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_SFT 0 10155 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_NVM 0x0UL 10156 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_HOST_DDR 0x1UL 10157 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 0x2UL 10158 #define DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_LAST DBG_QCFG_REQ_FLAGS_CRASHDUMP_SIZE_FOR_DEST_DEST_SOC_DDR 10159 __le32 coredump_component_disable_flags; 10160 #define DBG_QCFG_REQ_COREDUMP_COMPONENT_DISABLE_FLAGS_NVRAM 0x1UL 10161}; 10162 10163/* hwrm_dbg_qcfg_output (size:256b/32B) */ 10164struct hwrm_dbg_qcfg_output { 10165 __le16 error_code; 10166 __le16 req_type; 10167 __le16 seq_id; 10168 __le16 resp_len; 10169 __le16 fid; 10170 u8 unused_0[2]; 10171 __le32 coredump_size; 10172 __le32 flags; 10173 #define DBG_QCFG_RESP_FLAGS_UART_LOG 0x1UL 10174 #define DBG_QCFG_RESP_FLAGS_UART_LOG_SECONDARY 0x2UL 10175 #define DBG_QCFG_RESP_FLAGS_FW_TRACE 0x4UL 10176 #define DBG_QCFG_RESP_FLAGS_FW_TRACE_SECONDARY 0x8UL 10177 #define DBG_QCFG_RESP_FLAGS_DEBUG_NOTIFY 0x10UL 10178 #define DBG_QCFG_RESP_FLAGS_JTAG_DEBUG 0x20UL 10179 __le16 async_cmpl_ring; 10180 u8 unused_2[2]; 10181 __le32 crashdump_size; 10182 u8 unused_3[3]; 10183 u8 valid; 10184}; 10185 10186/* hwrm_dbg_crashdump_medium_cfg_input (size:320b/40B) */ 10187struct hwrm_dbg_crashdump_medium_cfg_input { 10188 __le16 req_type; 10189 __le16 cmpl_ring; 10190 __le16 seq_id; 10191 __le16 target_id; 10192 __le64 resp_addr; 10193 __le16 output_dest_flags; 10194 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_TYPE_DDR 0x1UL 10195 __le16 pg_size_lvl; 10196 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_MASK 0x3UL 10197 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_SFT 0 10198 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_0 0x0UL 10199 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_1 0x1UL 10200 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 0x2UL 10201 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_LVL_LVL_2 10202 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_MASK 0x1cUL 10203 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_SFT 2 10204 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_4K (0x0UL << 2) 10205 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8K (0x1UL << 2) 10206 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_64K (0x2UL << 2) 10207 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_2M (0x3UL << 2) 10208 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_8M (0x4UL << 2) 10209 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G (0x5UL << 2) 10210 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_LAST DBG_CRASHDUMP_MEDIUM_CFG_REQ_PG_SIZE_PG_1G 10211 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_MASK 0xffe0UL 10212 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_UNUSED11_SFT 5 10213 __le32 size; 10214 __le32 coredump_component_disable_flags; 10215 #define DBG_CRASHDUMP_MEDIUM_CFG_REQ_NVRAM 0x1UL 10216 __le32 unused_0; 10217 __le64 pbl; 10218}; 10219 10220/* hwrm_dbg_crashdump_medium_cfg_output (size:128b/16B) */ 10221struct hwrm_dbg_crashdump_medium_cfg_output { 10222 __le16 error_code; 10223 __le16 req_type; 10224 __le16 seq_id; 10225 __le16 resp_len; 10226 u8 unused_1[7]; 10227 u8 valid; 10228}; 10229 10230/* coredump_segment_record (size:128b/16B) */ 10231struct coredump_segment_record { 10232 __le16 component_id; 10233 __le16 segment_id; 10234 __le16 max_instances; 10235 u8 version_hi; 10236 u8 version_low; 10237 u8 seg_flags; 10238 u8 compress_flags; 10239 #define SFLAG_COMPRESSED_ZLIB 0x1UL 10240 u8 unused_0[2]; 10241 __le32 segment_len; 10242}; 10243 10244/* hwrm_dbg_coredump_list_input (size:256b/32B) */ 10245struct hwrm_dbg_coredump_list_input { 10246 __le16 req_type; 10247 __le16 cmpl_ring; 10248 __le16 seq_id; 10249 __le16 target_id; 10250 __le64 resp_addr; 10251 __le64 host_dest_addr; 10252 __le32 host_buf_len; 10253 __le16 seq_no; 10254 u8 flags; 10255 #define DBG_COREDUMP_LIST_REQ_FLAGS_CRASHDUMP 0x1UL 10256 u8 unused_0[1]; 10257}; 10258 10259/* hwrm_dbg_coredump_list_output (size:128b/16B) */ 10260struct hwrm_dbg_coredump_list_output { 10261 __le16 error_code; 10262 __le16 req_type; 10263 __le16 seq_id; 10264 __le16 resp_len; 10265 u8 flags; 10266 #define DBG_COREDUMP_LIST_RESP_FLAGS_MORE 0x1UL 10267 u8 unused_0; 10268 __le16 total_segments; 10269 __le16 data_len; 10270 u8 unused_1; 10271 u8 valid; 10272}; 10273 10274/* hwrm_dbg_coredump_initiate_input (size:256b/32B) */ 10275struct hwrm_dbg_coredump_initiate_input { 10276 __le16 req_type; 10277 __le16 cmpl_ring; 10278 __le16 seq_id; 10279 __le16 target_id; 10280 __le64 resp_addr; 10281 __le16 component_id; 10282 __le16 segment_id; 10283 __le16 instance; 10284 __le16 unused_0; 10285 u8 seg_flags; 10286 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA 0x1UL 10287 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA 0x2UL 10288 #define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE 0x4UL 10289 u8 unused_1[7]; 10290}; 10291 10292/* hwrm_dbg_coredump_initiate_output (size:128b/16B) */ 10293struct hwrm_dbg_coredump_initiate_output { 10294 __le16 error_code; 10295 __le16 req_type; 10296 __le16 seq_id; 10297 __le16 resp_len; 10298 u8 unused_0[7]; 10299 u8 valid; 10300}; 10301 10302/* coredump_data_hdr (size:128b/16B) */ 10303struct coredump_data_hdr { 10304 __le32 address; 10305 __le32 flags_length; 10306 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 10307 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 10308 #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 10309 __le32 instance; 10310 __le32 next_offset; 10311}; 10312 10313/* hwrm_dbg_coredump_retrieve_input (size:448b/56B) */ 10314struct hwrm_dbg_coredump_retrieve_input { 10315 __le16 req_type; 10316 __le16 cmpl_ring; 10317 __le16 seq_id; 10318 __le16 target_id; 10319 __le64 resp_addr; 10320 __le64 host_dest_addr; 10321 __le32 host_buf_len; 10322 __le32 unused_0; 10323 __le16 component_id; 10324 __le16 segment_id; 10325 __le16 instance; 10326 __le16 unused_1; 10327 u8 seg_flags; 10328 u8 unused_2; 10329 __le16 unused_3; 10330 __le32 unused_4; 10331 __le32 seq_no; 10332 __le32 unused_5; 10333}; 10334 10335/* hwrm_dbg_coredump_retrieve_output (size:128b/16B) */ 10336struct hwrm_dbg_coredump_retrieve_output { 10337 __le16 error_code; 10338 __le16 req_type; 10339 __le16 seq_id; 10340 __le16 resp_len; 10341 u8 flags; 10342 #define DBG_COREDUMP_RETRIEVE_RESP_FLAGS_MORE 0x1UL 10343 u8 unused_0; 10344 __le16 data_len; 10345 u8 unused_1[3]; 10346 u8 valid; 10347}; 10348 10349/* hwrm_dbg_ring_info_get_input (size:192b/24B) */ 10350struct hwrm_dbg_ring_info_get_input { 10351 __le16 req_type; 10352 __le16 cmpl_ring; 10353 __le16 seq_id; 10354 __le16 target_id; 10355 __le64 resp_addr; 10356 u8 ring_type; 10357 #define DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL 0x0UL 10358 #define DBG_RING_INFO_GET_REQ_RING_TYPE_TX 0x1UL 10359 #define DBG_RING_INFO_GET_REQ_RING_TYPE_RX 0x2UL 10360 #define DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 0x3UL 10361 #define DBG_RING_INFO_GET_REQ_RING_TYPE_LAST DBG_RING_INFO_GET_REQ_RING_TYPE_NQ 10362 u8 unused_0[3]; 10363 __le32 fw_ring_id; 10364}; 10365 10366/* hwrm_dbg_ring_info_get_output (size:192b/24B) */ 10367struct hwrm_dbg_ring_info_get_output { 10368 __le16 error_code; 10369 __le16 req_type; 10370 __le16 seq_id; 10371 __le16 resp_len; 10372 __le32 producer_index; 10373 __le32 consumer_index; 10374 __le32 cag_vector_ctrl; 10375 __le16 st_tag; 10376 u8 unused_0; 10377 u8 valid; 10378}; 10379 10380/* hwrm_dbg_log_buffer_flush_input (size:192b/24B) */ 10381struct hwrm_dbg_log_buffer_flush_input { 10382 __le16 req_type; 10383 __le16 cmpl_ring; 10384 __le16 seq_id; 10385 __le16 target_id; 10386 __le64 resp_addr; 10387 __le16 type; 10388 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT_TRACE 0x0UL 10389 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_SRT2_TRACE 0x1UL 10390 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT_TRACE 0x2UL 10391 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CRT2_TRACE 0x3UL 10392 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP0_TRACE 0x4UL 10393 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_L2_HWRM_TRACE 0x5UL 10394 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ROCE_HWRM_TRACE 0x6UL 10395 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA0_TRACE 0x7UL 10396 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA1_TRACE 0x8UL 10397 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_CA2_TRACE 0x9UL 10398 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_RIGP1_TRACE 0xaUL 10399 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_AFM_KONG_HWRM_TRACE 0xbUL 10400 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 0xcUL 10401 #define DBG_LOG_BUFFER_FLUSH_REQ_TYPE_LAST DBG_LOG_BUFFER_FLUSH_REQ_TYPE_ERR_QPC_TRACE 10402 u8 unused_1[2]; 10403 __le32 flags; 10404 #define DBG_LOG_BUFFER_FLUSH_REQ_FLAGS_FLUSH_ALL_BUFFERS 0x1UL 10405}; 10406 10407/* hwrm_dbg_log_buffer_flush_output (size:128b/16B) */ 10408struct hwrm_dbg_log_buffer_flush_output { 10409 __le16 error_code; 10410 __le16 req_type; 10411 __le16 seq_id; 10412 __le16 resp_len; 10413 __le32 current_buffer_offset; 10414 u8 unused_1[3]; 10415 u8 valid; 10416}; 10417 10418/* hwrm_nvm_read_input (size:320b/40B) */ 10419struct hwrm_nvm_read_input { 10420 __le16 req_type; 10421 __le16 cmpl_ring; 10422 __le16 seq_id; 10423 __le16 target_id; 10424 __le64 resp_addr; 10425 __le64 host_dest_addr; 10426 __le16 dir_idx; 10427 u8 unused_0[2]; 10428 __le32 offset; 10429 __le32 len; 10430 u8 unused_1[4]; 10431}; 10432 10433/* hwrm_nvm_read_output (size:128b/16B) */ 10434struct hwrm_nvm_read_output { 10435 __le16 error_code; 10436 __le16 req_type; 10437 __le16 seq_id; 10438 __le16 resp_len; 10439 u8 unused_0[7]; 10440 u8 valid; 10441}; 10442 10443/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 10444struct hwrm_nvm_get_dir_entries_input { 10445 __le16 req_type; 10446 __le16 cmpl_ring; 10447 __le16 seq_id; 10448 __le16 target_id; 10449 __le64 resp_addr; 10450 __le64 host_dest_addr; 10451}; 10452 10453/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 10454struct hwrm_nvm_get_dir_entries_output { 10455 __le16 error_code; 10456 __le16 req_type; 10457 __le16 seq_id; 10458 __le16 resp_len; 10459 u8 unused_0[7]; 10460 u8 valid; 10461}; 10462 10463/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 10464struct hwrm_nvm_get_dir_info_input { 10465 __le16 req_type; 10466 __le16 cmpl_ring; 10467 __le16 seq_id; 10468 __le16 target_id; 10469 __le64 resp_addr; 10470}; 10471 10472/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 10473struct hwrm_nvm_get_dir_info_output { 10474 __le16 error_code; 10475 __le16 req_type; 10476 __le16 seq_id; 10477 __le16 resp_len; 10478 __le32 entries; 10479 __le32 entry_length; 10480 u8 unused_0[7]; 10481 u8 valid; 10482}; 10483 10484/* hwrm_nvm_write_input (size:448b/56B) */ 10485struct hwrm_nvm_write_input { 10486 __le16 req_type; 10487 __le16 cmpl_ring; 10488 __le16 seq_id; 10489 __le16 target_id; 10490 __le64 resp_addr; 10491 __le64 host_src_addr; 10492 __le16 dir_type; 10493 __le16 dir_ordinal; 10494 __le16 dir_ext; 10495 __le16 dir_attr; 10496 __le32 dir_data_length; 10497 __le16 option; 10498 __le16 flags; 10499 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 10500 #define NVM_WRITE_REQ_FLAGS_BATCH_MODE 0x2UL 10501 #define NVM_WRITE_REQ_FLAGS_BATCH_LAST 0x4UL 10502 #define NVM_WRITE_REQ_FLAGS_SKIP_CRID_CHECK 0x8UL 10503 __le32 dir_item_length; 10504 __le32 offset; 10505 __le32 len; 10506 __le32 unused_0; 10507}; 10508 10509/* hwrm_nvm_write_output (size:128b/16B) */ 10510struct hwrm_nvm_write_output { 10511 __le16 error_code; 10512 __le16 req_type; 10513 __le16 seq_id; 10514 __le16 resp_len; 10515 __le32 dir_item_length; 10516 __le16 dir_idx; 10517 u8 unused_0; 10518 u8 valid; 10519}; 10520 10521/* hwrm_nvm_write_cmd_err (size:64b/8B) */ 10522struct hwrm_nvm_write_cmd_err { 10523 u8 code; 10524 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 10525 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10526 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 10527 #define NVM_WRITE_CMD_ERR_CODE_WRITE_FAILED 0x3UL 10528 #define NVM_WRITE_CMD_ERR_CODE_REQD_ERASE_FAILED 0x4UL 10529 #define NVM_WRITE_CMD_ERR_CODE_VERIFY_FAILED 0x5UL 10530 #define NVM_WRITE_CMD_ERR_CODE_INVALID_HEADER 0x6UL 10531 #define NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 0x7UL 10532 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_UPDATE_DIGEST_FAILED 10533 u8 unused_0[7]; 10534}; 10535 10536/* hwrm_nvm_modify_input (size:320b/40B) */ 10537struct hwrm_nvm_modify_input { 10538 __le16 req_type; 10539 __le16 cmpl_ring; 10540 __le16 seq_id; 10541 __le16 target_id; 10542 __le64 resp_addr; 10543 __le64 host_src_addr; 10544 __le16 dir_idx; 10545 __le16 flags; 10546 #define NVM_MODIFY_REQ_FLAGS_BATCH_MODE 0x1UL 10547 #define NVM_MODIFY_REQ_FLAGS_BATCH_LAST 0x2UL 10548 __le32 offset; 10549 __le32 len; 10550 u8 unused_1[4]; 10551}; 10552 10553/* hwrm_nvm_modify_output (size:128b/16B) */ 10554struct hwrm_nvm_modify_output { 10555 __le16 error_code; 10556 __le16 req_type; 10557 __le16 seq_id; 10558 __le16 resp_len; 10559 u8 unused_0[7]; 10560 u8 valid; 10561}; 10562 10563/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 10564struct hwrm_nvm_find_dir_entry_input { 10565 __le16 req_type; 10566 __le16 cmpl_ring; 10567 __le16 seq_id; 10568 __le16 target_id; 10569 __le64 resp_addr; 10570 __le32 enables; 10571 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 10572 __le16 dir_idx; 10573 __le16 dir_type; 10574 __le16 dir_ordinal; 10575 __le16 dir_ext; 10576 u8 opt_ordinal; 10577 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 10578 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 10579 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 10580 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 10581 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 10582 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 10583 u8 unused_0[3]; 10584}; 10585 10586/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 10587struct hwrm_nvm_find_dir_entry_output { 10588 __le16 error_code; 10589 __le16 req_type; 10590 __le16 seq_id; 10591 __le16 resp_len; 10592 __le32 dir_item_length; 10593 __le32 dir_data_length; 10594 __le32 fw_ver; 10595 __le16 dir_ordinal; 10596 __le16 dir_idx; 10597 u8 unused_0[7]; 10598 u8 valid; 10599}; 10600 10601/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 10602struct hwrm_nvm_erase_dir_entry_input { 10603 __le16 req_type; 10604 __le16 cmpl_ring; 10605 __le16 seq_id; 10606 __le16 target_id; 10607 __le64 resp_addr; 10608 __le16 dir_idx; 10609 u8 unused_0[6]; 10610}; 10611 10612/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 10613struct hwrm_nvm_erase_dir_entry_output { 10614 __le16 error_code; 10615 __le16 req_type; 10616 __le16 seq_id; 10617 __le16 resp_len; 10618 u8 unused_0[7]; 10619 u8 valid; 10620}; 10621 10622/* hwrm_nvm_get_dev_info_input (size:192b/24B) */ 10623struct hwrm_nvm_get_dev_info_input { 10624 __le16 req_type; 10625 __le16 cmpl_ring; 10626 __le16 seq_id; 10627 __le16 target_id; 10628 __le64 resp_addr; 10629 u8 flags; 10630 #define NVM_GET_DEV_INFO_REQ_FLAGS_SECURITY_SOC_NVM 0x1UL 10631 u8 unused_0[7]; 10632}; 10633 10634/* hwrm_nvm_get_dev_info_output (size:768b/96B) */ 10635struct hwrm_nvm_get_dev_info_output { 10636 __le16 error_code; 10637 __le16 req_type; 10638 __le16 seq_id; 10639 __le16 resp_len; 10640 __le16 manufacturer_id; 10641 __le16 device_id; 10642 __le32 sector_size; 10643 __le32 nvram_size; 10644 __le32 reserved_size; 10645 __le32 available_size; 10646 u8 nvm_cfg_ver_maj; 10647 u8 nvm_cfg_ver_min; 10648 u8 nvm_cfg_ver_upd; 10649 u8 flags; 10650 #define NVM_GET_DEV_INFO_RESP_FLAGS_FW_VER_VALID 0x1UL 10651 char pkg_name[16]; 10652 __le16 hwrm_fw_major; 10653 __le16 hwrm_fw_minor; 10654 __le16 hwrm_fw_build; 10655 __le16 hwrm_fw_patch; 10656 __le16 mgmt_fw_major; 10657 __le16 mgmt_fw_minor; 10658 __le16 mgmt_fw_build; 10659 __le16 mgmt_fw_patch; 10660 __le16 roce_fw_major; 10661 __le16 roce_fw_minor; 10662 __le16 roce_fw_build; 10663 __le16 roce_fw_patch; 10664 __le16 netctrl_fw_major; 10665 __le16 netctrl_fw_minor; 10666 __le16 netctrl_fw_build; 10667 __le16 netctrl_fw_patch; 10668 __le16 srt2_fw_major; 10669 __le16 srt2_fw_minor; 10670 __le16 srt2_fw_build; 10671 __le16 srt2_fw_patch; 10672 u8 security_soc_fw_major; 10673 u8 security_soc_fw_minor; 10674 u8 security_soc_fw_build; 10675 u8 security_soc_fw_patch; 10676 u8 unused_0[3]; 10677 u8 valid; 10678}; 10679 10680/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 10681struct hwrm_nvm_mod_dir_entry_input { 10682 __le16 req_type; 10683 __le16 cmpl_ring; 10684 __le16 seq_id; 10685 __le16 target_id; 10686 __le64 resp_addr; 10687 __le32 enables; 10688 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 10689 __le16 dir_idx; 10690 __le16 dir_ordinal; 10691 __le16 dir_ext; 10692 __le16 dir_attr; 10693 __le32 checksum; 10694}; 10695 10696/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 10697struct hwrm_nvm_mod_dir_entry_output { 10698 __le16 error_code; 10699 __le16 req_type; 10700 __le16 seq_id; 10701 __le16 resp_len; 10702 u8 unused_0[7]; 10703 u8 valid; 10704}; 10705 10706/* hwrm_nvm_verify_update_input (size:192b/24B) */ 10707struct hwrm_nvm_verify_update_input { 10708 __le16 req_type; 10709 __le16 cmpl_ring; 10710 __le16 seq_id; 10711 __le16 target_id; 10712 __le64 resp_addr; 10713 __le16 dir_type; 10714 __le16 dir_ordinal; 10715 __le16 dir_ext; 10716 u8 unused_0[2]; 10717}; 10718 10719/* hwrm_nvm_verify_update_output (size:128b/16B) */ 10720struct hwrm_nvm_verify_update_output { 10721 __le16 error_code; 10722 __le16 req_type; 10723 __le16 seq_id; 10724 __le16 resp_len; 10725 u8 unused_0[7]; 10726 u8 valid; 10727}; 10728 10729/* hwrm_nvm_install_update_input (size:192b/24B) */ 10730struct hwrm_nvm_install_update_input { 10731 __le16 req_type; 10732 __le16 cmpl_ring; 10733 __le16 seq_id; 10734 __le16 target_id; 10735 __le64 resp_addr; 10736 __le32 install_type; 10737 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 10738 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 10739 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 10740 __le16 flags; 10741 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 10742 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 10743 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 10744 #define NVM_INSTALL_UPDATE_REQ_FLAGS_VERIFY_ONLY 0x8UL 10745 u8 unused_0[2]; 10746}; 10747 10748/* hwrm_nvm_install_update_output (size:192b/24B) */ 10749struct hwrm_nvm_install_update_output { 10750 __le16 error_code; 10751 __le16 req_type; 10752 __le16 seq_id; 10753 __le16 resp_len; 10754 __le64 installed_items; 10755 u8 result; 10756 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 10757 #define NVM_INSTALL_UPDATE_RESP_RESULT_FAILURE 0xffUL 10758 #define NVM_INSTALL_UPDATE_RESP_RESULT_MALLOC_FAILURE 0xfdUL 10759 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_INDEX_PARAMETER 0xfbUL 10760 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TYPE_PARAMETER 0xf3UL 10761 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PREREQUISITE 0xf2UL 10762 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_FILE_HEADER 0xecUL 10763 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_SIGNATURE 0xebUL 10764 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_STREAM 0xeaUL 10765 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_PROP_LENGTH 0xe9UL 10766 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_MANIFEST 0xe8UL 10767 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_TRAILER 0xe7UL 10768 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_CHECKSUM 0xe6UL 10769 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_ITEM_CHECKSUM 0xe5UL 10770 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DATA_LENGTH 0xe4UL 10771 #define NVM_INSTALL_UPDATE_RESP_RESULT_INVALID_DIRECTIVE 0xe1UL 10772 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_CHIP_REV 0xceUL 10773 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_DEVICE_ID 0xcdUL 10774 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_VENDOR 0xccUL 10775 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_SUBSYS_ID 0xcbUL 10776 #define NVM_INSTALL_UPDATE_RESP_RESULT_UNSUPPORTED_PLATFORM 0xc5UL 10777 #define NVM_INSTALL_UPDATE_RESP_RESULT_DUPLICATE_ITEM 0xc4UL 10778 #define NVM_INSTALL_UPDATE_RESP_RESULT_ZERO_LENGTH_ITEM 0xc3UL 10779 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_CHECKSUM_ERROR 0xb9UL 10780 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_DATA_ERROR 0xb8UL 10781 #define NVM_INSTALL_UPDATE_RESP_RESULT_INSTALL_AUTHENTICATION_ERROR 0xb7UL 10782 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_NOT_FOUND 0xb0UL 10783 #define NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 0xa7UL 10784 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_ITEM_LOCKED 10785 u8 problem_item; 10786 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 10787 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 10788 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 10789 u8 reset_required; 10790 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 10791 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 10792 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 10793 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 10794 u8 unused_0[4]; 10795 u8 valid; 10796}; 10797 10798/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 10799struct hwrm_nvm_install_update_cmd_err { 10800 u8 code; 10801 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 10802 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 10803 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 10804 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_ANTI_ROLLBACK 0x3UL 10805 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_VOLTREG_SUPPORT 0x4UL 10806 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_DEFRAG_FAILED 0x5UL 10807 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 0x6UL 10808 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN_DIR_ERR 10809 u8 unused_0[7]; 10810}; 10811 10812/* hwrm_nvm_get_variable_input (size:320b/40B) */ 10813struct hwrm_nvm_get_variable_input { 10814 __le16 req_type; 10815 __le16 cmpl_ring; 10816 __le16 seq_id; 10817 __le16 target_id; 10818 __le64 resp_addr; 10819 __le64 dest_data_addr; 10820 __le16 data_len; 10821 __le16 option_num; 10822 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10823 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10824 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10825 __le16 dimensions; 10826 __le16 index_0; 10827 __le16 index_1; 10828 __le16 index_2; 10829 __le16 index_3; 10830 u8 flags; 10831 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 10832 #define NVM_GET_VARIABLE_REQ_FLAGS_VALIDATE_OPT_VALUE 0x2UL 10833 u8 unused_0; 10834}; 10835 10836/* hwrm_nvm_get_variable_output (size:128b/16B) */ 10837struct hwrm_nvm_get_variable_output { 10838 __le16 error_code; 10839 __le16 req_type; 10840 __le16 seq_id; 10841 __le16 resp_len; 10842 __le16 data_len; 10843 __le16 option_num; 10844 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 10845 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 10846 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 10847 u8 flags; 10848 #define NVM_GET_VARIABLE_RESP_FLAGS_VALIDATE_OPT_VALUE 0x1UL 10849 u8 unused_0[2]; 10850 u8 valid; 10851}; 10852 10853/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 10854struct hwrm_nvm_get_variable_cmd_err { 10855 u8 code; 10856 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10857 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10858 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10859 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10860 #define NVM_GET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x4UL 10861 #define NVM_GET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x5UL 10862 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x6UL 10863 #define NVM_GET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x7UL 10864 #define NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x8UL 10865 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_NO_MEM 10866 u8 unused_0[7]; 10867}; 10868 10869/* hwrm_nvm_set_variable_input (size:320b/40B) */ 10870struct hwrm_nvm_set_variable_input { 10871 __le16 req_type; 10872 __le16 cmpl_ring; 10873 __le16 seq_id; 10874 __le16 target_id; 10875 __le64 resp_addr; 10876 __le64 src_data_addr; 10877 __le16 data_len; 10878 __le16 option_num; 10879 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 10880 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 10881 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 10882 __le16 dimensions; 10883 __le16 index_0; 10884 __le16 index_1; 10885 __le16 index_2; 10886 __le16 index_3; 10887 u8 flags; 10888 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 10889 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 10890 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 10891 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 10892 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 10893 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_AES256 (0x2UL << 1) 10894 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH (0x3UL << 1) 10895 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1_AUTH 10896 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_MASK 0x70UL 10897 #define NVM_SET_VARIABLE_REQ_FLAGS_FLAGS_UNUSED_0_SFT 4 10898 #define NVM_SET_VARIABLE_REQ_FLAGS_FACTORY_DEFAULT 0x80UL 10899 u8 unused_0; 10900}; 10901 10902/* hwrm_nvm_set_variable_output (size:128b/16B) */ 10903struct hwrm_nvm_set_variable_output { 10904 __le16 error_code; 10905 __le16 req_type; 10906 __le16 seq_id; 10907 __le16 resp_len; 10908 u8 unused_0[7]; 10909 u8 valid; 10910}; 10911 10912/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 10913struct hwrm_nvm_set_variable_cmd_err { 10914 u8 code; 10915 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 10916 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 10917 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 10918 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 10919 #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACTION_NOT_SUPPORTED 0x4UL 10920 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INDEX_INVALID 0x5UL 10921 #define NVM_SET_VARIABLE_CMD_ERR_CODE_ACCESS_DENIED 0x6UL 10922 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CB_FAILED 0x7UL 10923 #define NVM_SET_VARIABLE_CMD_ERR_CODE_INVALID_DATA_LEN 0x8UL 10924 #define NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 0x9UL 10925 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_NO_MEM 10926 u8 unused_0[7]; 10927}; 10928 10929/* hwrm_selftest_qlist_input (size:128b/16B) */ 10930struct hwrm_selftest_qlist_input { 10931 __le16 req_type; 10932 __le16 cmpl_ring; 10933 __le16 seq_id; 10934 __le16 target_id; 10935 __le64 resp_addr; 10936}; 10937 10938/* hwrm_selftest_qlist_output (size:2240b/280B) */ 10939struct hwrm_selftest_qlist_output { 10940 __le16 error_code; 10941 __le16 req_type; 10942 __le16 seq_id; 10943 __le16 resp_len; 10944 u8 num_tests; 10945 u8 available_tests; 10946 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 10947 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 10948 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 10949 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 10950 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 10951 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10952 u8 offline_tests; 10953 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 10954 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 10955 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 10956 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 10957 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 10958 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 10959 u8 unused_0; 10960 __le16 test_timeout; 10961 u8 unused_1[2]; 10962 char test_name[8][32]; 10963 u8 eyescope_target_BER_support; 10964 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E8_SUPPORTED 0x0UL 10965 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E9_SUPPORTED 0x1UL 10966 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E10_SUPPORTED 0x2UL 10967 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E11_SUPPORTED 0x3UL 10968 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 0x4UL 10969 #define SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_LAST SELFTEST_QLIST_RESP_EYESCOPE_TARGET_BER_SUPPORT_BER_1E12_SUPPORTED 10970 u8 unused_2[6]; 10971 u8 valid; 10972}; 10973 10974/* hwrm_selftest_exec_input (size:192b/24B) */ 10975struct hwrm_selftest_exec_input { 10976 __le16 req_type; 10977 __le16 cmpl_ring; 10978 __le16 seq_id; 10979 __le16 target_id; 10980 __le64 resp_addr; 10981 u8 flags; 10982 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 10983 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 10984 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 10985 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 10986 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 10987 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 10988 u8 unused_0[7]; 10989}; 10990 10991/* hwrm_selftest_exec_output (size:128b/16B) */ 10992struct hwrm_selftest_exec_output { 10993 __le16 error_code; 10994 __le16 req_type; 10995 __le16 seq_id; 10996 __le16 resp_len; 10997 u8 requested_tests; 10998 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 10999 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 11000 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 11001 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 11002 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 11003 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 11004 u8 test_success; 11005 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 11006 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 11007 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 11008 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 11009 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 11010 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 11011 u8 unused_0[5]; 11012 u8 valid; 11013}; 11014 11015/* hwrm_selftest_irq_input (size:128b/16B) */ 11016struct hwrm_selftest_irq_input { 11017 __le16 req_type; 11018 __le16 cmpl_ring; 11019 __le16 seq_id; 11020 __le16 target_id; 11021 __le64 resp_addr; 11022}; 11023 11024/* hwrm_selftest_irq_output (size:128b/16B) */ 11025struct hwrm_selftest_irq_output { 11026 __le16 error_code; 11027 __le16 req_type; 11028 __le16 seq_id; 11029 __le16 resp_len; 11030 u8 unused_0[7]; 11031 u8 valid; 11032}; 11033 11034/* dbc_dbc (size:64b/8B) */ 11035struct dbc_dbc { 11036 __le32 index; 11037 #define DBC_DBC_INDEX_MASK 0xffffffUL 11038 #define DBC_DBC_INDEX_SFT 0 11039 #define DBC_DBC_EPOCH 0x1000000UL 11040 #define DBC_DBC_TOGGLE_MASK 0x6000000UL 11041 #define DBC_DBC_TOGGLE_SFT 25 11042 __le32 type_path_xid; 11043 #define DBC_DBC_XID_MASK 0xfffffUL 11044 #define DBC_DBC_XID_SFT 0 11045 #define DBC_DBC_PATH_MASK 0x3000000UL 11046 #define DBC_DBC_PATH_SFT 24 11047 #define DBC_DBC_PATH_ROCE (0x0UL << 24) 11048 #define DBC_DBC_PATH_L2 (0x1UL << 24) 11049 #define DBC_DBC_PATH_ENGINE (0x2UL << 24) 11050 #define DBC_DBC_PATH_LAST DBC_DBC_PATH_ENGINE 11051 #define DBC_DBC_VALID 0x4000000UL 11052 #define DBC_DBC_DEBUG_TRACE 0x8000000UL 11053 #define DBC_DBC_TYPE_MASK 0xf0000000UL 11054 #define DBC_DBC_TYPE_SFT 28 11055 #define DBC_DBC_TYPE_SQ (0x0UL << 28) 11056 #define DBC_DBC_TYPE_RQ (0x1UL << 28) 11057 #define DBC_DBC_TYPE_SRQ (0x2UL << 28) 11058 #define DBC_DBC_TYPE_SRQ_ARM (0x3UL << 28) 11059 #define DBC_DBC_TYPE_CQ (0x4UL << 28) 11060 #define DBC_DBC_TYPE_CQ_ARMSE (0x5UL << 28) 11061 #define DBC_DBC_TYPE_CQ_ARMALL (0x6UL << 28) 11062 #define DBC_DBC_TYPE_CQ_ARMENA (0x7UL << 28) 11063 #define DBC_DBC_TYPE_SRQ_ARMENA (0x8UL << 28) 11064 #define DBC_DBC_TYPE_CQ_CUTOFF_ACK (0x9UL << 28) 11065 #define DBC_DBC_TYPE_NQ (0xaUL << 28) 11066 #define DBC_DBC_TYPE_NQ_ARM (0xbUL << 28) 11067 #define DBC_DBC_TYPE_NQ_MASK (0xeUL << 28) 11068 #define DBC_DBC_TYPE_NULL (0xfUL << 28) 11069 #define DBC_DBC_TYPE_LAST DBC_DBC_TYPE_NULL 11070}; 11071 11072/* db_push_start (size:64b/8B) */ 11073struct db_push_start { 11074 u64 db; 11075 #define DB_PUSH_START_DB_INDEX_MASK 0xffffffUL 11076 #define DB_PUSH_START_DB_INDEX_SFT 0 11077 #define DB_PUSH_START_DB_PI_LO_MASK 0xff000000UL 11078 #define DB_PUSH_START_DB_PI_LO_SFT 24 11079 #define DB_PUSH_START_DB_XID_MASK 0xfffff00000000ULL 11080 #define DB_PUSH_START_DB_XID_SFT 32 11081 #define DB_PUSH_START_DB_PI_HI_MASK 0xf0000000000000ULL 11082 #define DB_PUSH_START_DB_PI_HI_SFT 52 11083 #define DB_PUSH_START_DB_TYPE_MASK 0xf000000000000000ULL 11084 #define DB_PUSH_START_DB_TYPE_SFT 60 11085 #define DB_PUSH_START_DB_TYPE_PUSH_START (0xcULL << 60) 11086 #define DB_PUSH_START_DB_TYPE_PUSH_END (0xdULL << 60) 11087 #define DB_PUSH_START_DB_TYPE_LAST DB_PUSH_START_DB_TYPE_PUSH_END 11088}; 11089 11090/* db_push_end (size:64b/8B) */ 11091struct db_push_end { 11092 u64 db; 11093 #define DB_PUSH_END_DB_INDEX_MASK 0xffffffUL 11094 #define DB_PUSH_END_DB_INDEX_SFT 0 11095 #define DB_PUSH_END_DB_PI_LO_MASK 0xff000000UL 11096 #define DB_PUSH_END_DB_PI_LO_SFT 24 11097 #define DB_PUSH_END_DB_XID_MASK 0xfffff00000000ULL 11098 #define DB_PUSH_END_DB_XID_SFT 32 11099 #define DB_PUSH_END_DB_PI_HI_MASK 0xf0000000000000ULL 11100 #define DB_PUSH_END_DB_PI_HI_SFT 52 11101 #define DB_PUSH_END_DB_PATH_MASK 0x300000000000000ULL 11102 #define DB_PUSH_END_DB_PATH_SFT 56 11103 #define DB_PUSH_END_DB_PATH_ROCE (0x0ULL << 56) 11104 #define DB_PUSH_END_DB_PATH_L2 (0x1ULL << 56) 11105 #define DB_PUSH_END_DB_PATH_ENGINE (0x2ULL << 56) 11106 #define DB_PUSH_END_DB_PATH_LAST DB_PUSH_END_DB_PATH_ENGINE 11107 #define DB_PUSH_END_DB_DEBUG_TRACE 0x800000000000000ULL 11108 #define DB_PUSH_END_DB_TYPE_MASK 0xf000000000000000ULL 11109 #define DB_PUSH_END_DB_TYPE_SFT 60 11110 #define DB_PUSH_END_DB_TYPE_PUSH_START (0xcULL << 60) 11111 #define DB_PUSH_END_DB_TYPE_PUSH_END (0xdULL << 60) 11112 #define DB_PUSH_END_DB_TYPE_LAST DB_PUSH_END_DB_TYPE_PUSH_END 11113}; 11114 11115/* db_push_info (size:64b/8B) */ 11116struct db_push_info { 11117 u32 push_size_push_index; 11118 #define DB_PUSH_INFO_PUSH_INDEX_MASK 0xffffffUL 11119 #define DB_PUSH_INFO_PUSH_INDEX_SFT 0 11120 #define DB_PUSH_INFO_PUSH_SIZE_MASK 0x1f000000UL 11121 #define DB_PUSH_INFO_PUSH_SIZE_SFT 24 11122 u32 reserved32; 11123}; 11124 11125/* fw_status_reg (size:32b/4B) */ 11126struct fw_status_reg { 11127 u32 fw_status; 11128 #define FW_STATUS_REG_CODE_MASK 0xffffUL 11129 #define FW_STATUS_REG_CODE_SFT 0 11130 #define FW_STATUS_REG_CODE_READY 0x8000UL 11131 #define FW_STATUS_REG_CODE_LAST FW_STATUS_REG_CODE_READY 11132 #define FW_STATUS_REG_IMAGE_DEGRADED 0x10000UL 11133 #define FW_STATUS_REG_RECOVERABLE 0x20000UL 11134 #define FW_STATUS_REG_CRASHDUMP_ONGOING 0x40000UL 11135 #define FW_STATUS_REG_CRASHDUMP_COMPLETE 0x80000UL 11136 #define FW_STATUS_REG_SHUTDOWN 0x100000UL 11137 #define FW_STATUS_REG_CRASHED_NO_MASTER 0x200000UL 11138 #define FW_STATUS_REG_RECOVERING 0x400000UL 11139 #define FW_STATUS_REG_MANU_DEBUG_STATUS 0x800000UL 11140}; 11141 11142/* hcomm_status (size:64b/8B) */ 11143struct hcomm_status { 11144 u32 sig_ver; 11145 #define HCOMM_STATUS_VER_MASK 0xffUL 11146 #define HCOMM_STATUS_VER_SFT 0 11147 #define HCOMM_STATUS_VER_LATEST 0x1UL 11148 #define HCOMM_STATUS_VER_LAST HCOMM_STATUS_VER_LATEST 11149 #define HCOMM_STATUS_SIGNATURE_MASK 0xffffff00UL 11150 #define HCOMM_STATUS_SIGNATURE_SFT 8 11151 #define HCOMM_STATUS_SIGNATURE_VAL (0x484353UL << 8) 11152 #define HCOMM_STATUS_SIGNATURE_LAST HCOMM_STATUS_SIGNATURE_VAL 11153 u32 fw_status_loc; 11154 #define HCOMM_STATUS_TRUE_ADDR_SPACE_MASK 0x3UL 11155 #define HCOMM_STATUS_TRUE_ADDR_SPACE_SFT 0 11156 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_PCIE_CFG 0x0UL 11157 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_GRC 0x1UL 11158 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR0 0x2UL 11159 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 0x3UL 11160 #define HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_LAST HCOMM_STATUS_FW_STATUS_LOC_ADDR_SPACE_BAR1 11161 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 11162 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 11163}; 11164#define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 11165 11166#endif /* _BNXT_HSI_H_ */