Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
1/*
2 * Copyright 2013 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25#ifndef __PCIIDS_H__
26#define __PCIIDS_H__
27
28#ifdef __KERNEL__
29#define INTEL_PCI_DEVICE(_id, _info) { \
30 PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
31 .driver_data = (kernel_ulong_t)(_info), \
32}
33
34#define INTEL_VGA_DEVICE(_id, _info) { \
35 PCI_DEVICE(PCI_VENDOR_ID_INTEL, (_id)), \
36 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \
37 .driver_data = (kernel_ulong_t)(_info), \
38}
39
40#define INTEL_QUANTA_VGA_DEVICE(_info) { \
41 .vendor = PCI_VENDOR_ID_INTEL, .device = 0x16a, \
42 .subvendor = 0x152d, .subdevice = 0x8990, \
43 .class = PCI_BASE_CLASS_DISPLAY << 16, .class_mask = 0xff << 16, \
44 .driver_data = (kernel_ulong_t)(_info), \
45}
46#endif
47
48#define INTEL_I810_IDS(MACRO__, ...) \
49 MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \
50 MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \
51 MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */
52
53#define INTEL_I815_IDS(MACRO__, ...) \
54 MACRO__(0x1132, ## __VA_ARGS__) /* I815*/
55
56#define INTEL_I830_IDS(MACRO__, ...) \
57 MACRO__(0x3577, ## __VA_ARGS__)
58
59#define INTEL_I845G_IDS(MACRO__, ...) \
60 MACRO__(0x2562, ## __VA_ARGS__)
61
62#define INTEL_I85X_IDS(MACRO__, ...) \
63 MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \
64 MACRO__(0x358e, ## __VA_ARGS__)
65
66#define INTEL_I865G_IDS(MACRO__, ...) \
67 MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */
68
69#define INTEL_I915G_IDS(MACRO__, ...) \
70 MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \
71 MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */
72
73#define INTEL_I915GM_IDS(MACRO__, ...) \
74 MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */
75
76#define INTEL_I945G_IDS(MACRO__, ...) \
77 MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */
78
79#define INTEL_I945GM_IDS(MACRO__, ...) \
80 MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \
81 MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */
82
83#define INTEL_I965G_IDS(MACRO__, ...) \
84 MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \
85 MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \
86 MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \
87 MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */
88
89#define INTEL_G33_IDS(MACRO__, ...) \
90 MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \
91 MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \
92 MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */
93
94#define INTEL_I965GM_IDS(MACRO__, ...) \
95 MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \
96 MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */
97
98#define INTEL_GM45_IDS(MACRO__, ...) \
99 MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */
100
101#define INTEL_G45_IDS(MACRO__, ...) \
102 MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \
103 MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \
104 MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \
105 MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \
106 MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \
107 MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */
108
109#define INTEL_PNV_G_IDS(MACRO__, ...) \
110 MACRO__(0xa001, ## __VA_ARGS__)
111
112#define INTEL_PNV_M_IDS(MACRO__, ...) \
113 MACRO__(0xa011, ## __VA_ARGS__)
114
115#define INTEL_PNV_IDS(MACRO__, ...) \
116 INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \
117 INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__)
118
119#define INTEL_ILK_D_IDS(MACRO__, ...) \
120 MACRO__(0x0042, ## __VA_ARGS__)
121
122#define INTEL_ILK_M_IDS(MACRO__, ...) \
123 MACRO__(0x0046, ## __VA_ARGS__)
124
125#define INTEL_ILK_IDS(MACRO__, ...) \
126 INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \
127 INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__)
128
129#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \
130 MACRO__(0x0102, ## __VA_ARGS__), \
131 MACRO__(0x010A, ## __VA_ARGS__)
132
133#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \
134 MACRO__(0x0112, ## __VA_ARGS__), \
135 MACRO__(0x0122, ## __VA_ARGS__)
136
137#define INTEL_SNB_D_IDS(MACRO__, ...) \
138 INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
139 INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
140
141#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \
142 MACRO__(0x0106, ## __VA_ARGS__)
143
144#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \
145 MACRO__(0x0116, ## __VA_ARGS__), \
146 MACRO__(0x0126, ## __VA_ARGS__)
147
148#define INTEL_SNB_M_IDS(MACRO__, ...) \
149 INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
150 INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
151
152#define INTEL_SNB_IDS(MACRO__, ...) \
153 INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \
154 INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__)
155
156#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \
157 MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */
158
159#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \
160 MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */
161
162#define INTEL_IVB_M_IDS(MACRO__, ...) \
163 INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \
164 INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__)
165
166#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \
167 MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \
168 MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */
169
170#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \
171 MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \
172 MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */
173
174#define INTEL_IVB_D_IDS(MACRO__, ...) \
175 INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \
176 INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__)
177
178#define INTEL_IVB_IDS(MACRO__, ...) \
179 INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \
180 INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__)
181
182#define INTEL_IVB_Q_IDS(MACRO__, ...) \
183 INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */
184
185#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \
186 MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \
187 MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \
188 MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \
189 MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */
190
191#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \
192 MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */
193
194#define INTEL_HSW_GT1_IDS(MACRO__, ...) \
195 INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
196 INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
197 MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \
198 MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \
199 MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \
200 MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \
201 MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \
202 MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \
203 MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \
204 MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \
205 MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \
206 MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \
207 MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \
208 MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \
209 MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \
210 MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \
211 MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */
212
213#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \
214 MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \
215 MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \
216 MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \
217 MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \
218
219#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \
220 MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \
221
222#define INTEL_HSW_GT2_IDS(MACRO__, ...) \
223 INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
224 INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
225 MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \
226 MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \
227 MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \
228 MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \
229 MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \
230 MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \
231 MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \
232 MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \
233 MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \
234 MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \
235 MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \
236 MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \
237 MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \
238 MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \
239 MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */
240
241#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \
242 MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \
243 MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \
244 MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \
245 MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \
246 MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */
247
248#define INTEL_HSW_GT3_IDS(MACRO__, ...) \
249 INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
250 MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \
251 MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \
252 MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \
253 MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \
254 MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \
255 MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \
256 MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \
257 MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \
258 MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \
259 MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \
260 MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \
261 MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \
262 MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \
263 MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \
264 MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */
265
266#define INTEL_HSW_IDS(MACRO__, ...) \
267 INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
268 INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
269 INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__)
270
271#define INTEL_VLV_IDS(MACRO__, ...) \
272 MACRO__(0x0f30, ## __VA_ARGS__), \
273 MACRO__(0x0f31, ## __VA_ARGS__), \
274 MACRO__(0x0f32, ## __VA_ARGS__), \
275 MACRO__(0x0f33, ## __VA_ARGS__)
276
277#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \
278 MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \
279 MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */
280
281#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \
282 MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */
283
284#define INTEL_BDW_GT1_IDS(MACRO__, ...) \
285 INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
286 INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
287 MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \
288 MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \
289 MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */
290
291#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \
292 MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \
293 MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */
294
295#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \
296 MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */
297
298#define INTEL_BDW_GT2_IDS(MACRO__, ...) \
299 INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
300 INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
301 MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \
302 MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \
303 MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */
304
305#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \
306 MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \
307 MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \
308
309#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \
310 MACRO__(0x162E, ## __VA_ARGS__) /* ULX */
311
312#define INTEL_BDW_GT3_IDS(MACRO__, ...) \
313 INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
314 INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \
315 MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \
316 MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \
317 MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */
318
319#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \
320 MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \
321 MACRO__(0x163B, ## __VA_ARGS__) /* Iris */
322
323#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \
324 MACRO__(0x163E, ## __VA_ARGS__) /* ULX */
325
326#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \
327 INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
328 INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \
329 MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \
330 MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \
331 MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */
332
333#define INTEL_BDW_IDS(MACRO__, ...) \
334 INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \
335 INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \
336 INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \
337 INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__)
338
339#define INTEL_CHV_IDS(MACRO__, ...) \
340 MACRO__(0x22b0, ## __VA_ARGS__), \
341 MACRO__(0x22b1, ## __VA_ARGS__), \
342 MACRO__(0x22b2, ## __VA_ARGS__), \
343 MACRO__(0x22b3, ## __VA_ARGS__)
344
345#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \
346 MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \
347 MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */
348
349#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \
350 MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \
351 MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */
352
353#define INTEL_SKL_GT1_IDS(MACRO__, ...) \
354 INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
355 INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
356 MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \
357 MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \
358 MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \
359 MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */
360
361#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \
362 MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \
363 MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */
364
365#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \
366 MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */
367
368#define INTEL_SKL_GT2_IDS(MACRO__, ...) \
369 INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
370 INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
371 MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \
372 MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \
373 MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \
374 MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */
375
376#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \
377 MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \
378 MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \
379 MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */
380
381#define INTEL_SKL_GT3_IDS(MACRO__, ...) \
382 INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
383 MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \
384 MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \
385 MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */
386
387#define INTEL_SKL_GT4_IDS(MACRO__, ...) \
388 MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \
389 MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \
390 MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \
391 MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */
392
393#define INTEL_SKL_IDS(MACRO__, ...) \
394 INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
395 INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
396 INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
397 INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__)
398
399#define INTEL_BXT_IDS(MACRO__, ...) \
400 MACRO__(0x0A84, ## __VA_ARGS__), \
401 MACRO__(0x1A84, ## __VA_ARGS__), \
402 MACRO__(0x1A85, ## __VA_ARGS__), \
403 MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \
404 MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */
405
406#define INTEL_GLK_IDS(MACRO__, ...) \
407 MACRO__(0x3184, ## __VA_ARGS__), \
408 MACRO__(0x3185, ## __VA_ARGS__)
409
410#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \
411 MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \
412 MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */
413
414#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \
415 MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \
416 MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */
417
418#define INTEL_KBL_GT1_IDS(MACRO__, ...) \
419 INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \
420 INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \
421 MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \
422 MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \
423 MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \
424 MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */
425
426#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \
427 MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \
428 MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */
429
430#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \
431 MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */
432
433#define INTEL_KBL_GT2_IDS(MACRO__, ...) \
434 INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \
435 INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \
436 MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \
437 MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \
438 MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \
439 MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \
440 MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */
441
442#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \
443 MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */
444
445#define INTEL_KBL_GT3_IDS(MACRO__, ...) \
446 INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \
447 MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \
448 MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */
449
450#define INTEL_KBL_GT4_IDS(MACRO__, ...) \
451 MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */
452
453/* AML/KBL Y GT2 */
454#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \
455 MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \
456 MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */
457
458/* AML/CFL Y GT2 */
459#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \
460 MACRO__(0x87CA, ## __VA_ARGS__)
461
462/* CML GT1 */
463#define INTEL_CML_GT1_IDS(MACRO__, ...) \
464 MACRO__(0x9BA2, ## __VA_ARGS__), \
465 MACRO__(0x9BA4, ## __VA_ARGS__), \
466 MACRO__(0x9BA5, ## __VA_ARGS__), \
467 MACRO__(0x9BA8, ## __VA_ARGS__)
468
469#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \
470 MACRO__(0x9B21, ## __VA_ARGS__), \
471 MACRO__(0x9BAA, ## __VA_ARGS__), \
472 MACRO__(0x9BAC, ## __VA_ARGS__)
473
474/* CML GT2 */
475#define INTEL_CML_GT2_IDS(MACRO__, ...) \
476 MACRO__(0x9BC2, ## __VA_ARGS__), \
477 MACRO__(0x9BC4, ## __VA_ARGS__), \
478 MACRO__(0x9BC5, ## __VA_ARGS__), \
479 MACRO__(0x9BC6, ## __VA_ARGS__), \
480 MACRO__(0x9BC8, ## __VA_ARGS__), \
481 MACRO__(0x9BE6, ## __VA_ARGS__), \
482 MACRO__(0x9BF6, ## __VA_ARGS__)
483
484#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \
485 MACRO__(0x9B41, ## __VA_ARGS__), \
486 MACRO__(0x9BCA, ## __VA_ARGS__), \
487 MACRO__(0x9BCC, ## __VA_ARGS__)
488
489#define INTEL_CML_IDS(MACRO__, ...) \
490 INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \
491 INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \
492 INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
493 INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__)
494
495#define INTEL_KBL_IDS(MACRO__, ...) \
496 INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
497 INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \
498 INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \
499 INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \
500 INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__)
501
502/* CFL S */
503#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \
504 MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \
505 MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \
506 MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */
507
508#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \
509 MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \
510 MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \
511 MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \
512 MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \
513 MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */
514
515/* CFL H */
516#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \
517 MACRO__(0x3E9C, ## __VA_ARGS__)
518
519#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \
520 MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \
521 MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */
522
523/* CFL U GT2 */
524#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \
525 MACRO__(0x3EA9, ## __VA_ARGS__)
526
527/* CFL U GT3 */
528#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \
529 MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \
530 MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \
531 MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \
532 MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */
533
534#define INTEL_CFL_IDS(MACRO__, ...) \
535 INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \
536 INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \
537 INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \
538 INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \
539 INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
540 INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \
541 INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__)
542
543/* WHL/CFL U GT1 */
544#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \
545 MACRO__(0x3EA1, ## __VA_ARGS__), \
546 MACRO__(0x3EA4, ## __VA_ARGS__)
547
548/* WHL/CFL U GT2 */
549#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \
550 MACRO__(0x3EA0, ## __VA_ARGS__), \
551 MACRO__(0x3EA3, ## __VA_ARGS__)
552
553/* WHL/CFL U GT3 */
554#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \
555 MACRO__(0x3EA2, ## __VA_ARGS__)
556
557#define INTEL_WHL_IDS(MACRO__, ...) \
558 INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \
559 INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \
560 INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__)
561
562/* CNL */
563#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \
564 MACRO__(0x5A44, ## __VA_ARGS__), \
565 MACRO__(0x5A4C, ## __VA_ARGS__), \
566 MACRO__(0x5A54, ## __VA_ARGS__), \
567 MACRO__(0x5A5C, ## __VA_ARGS__)
568
569#define INTEL_CNL_IDS(MACRO__, ...) \
570 INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
571 MACRO__(0x5A40, ## __VA_ARGS__), \
572 MACRO__(0x5A41, ## __VA_ARGS__), \
573 MACRO__(0x5A42, ## __VA_ARGS__), \
574 MACRO__(0x5A49, ## __VA_ARGS__), \
575 MACRO__(0x5A4A, ## __VA_ARGS__), \
576 MACRO__(0x5A50, ## __VA_ARGS__), \
577 MACRO__(0x5A51, ## __VA_ARGS__), \
578 MACRO__(0x5A52, ## __VA_ARGS__), \
579 MACRO__(0x5A59, ## __VA_ARGS__), \
580 MACRO__(0x5A5A, ## __VA_ARGS__)
581
582/* ICL */
583#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \
584 MACRO__(0x8A50, ## __VA_ARGS__), \
585 MACRO__(0x8A52, ## __VA_ARGS__), \
586 MACRO__(0x8A53, ## __VA_ARGS__), \
587 MACRO__(0x8A54, ## __VA_ARGS__), \
588 MACRO__(0x8A56, ## __VA_ARGS__), \
589 MACRO__(0x8A57, ## __VA_ARGS__), \
590 MACRO__(0x8A58, ## __VA_ARGS__), \
591 MACRO__(0x8A59, ## __VA_ARGS__), \
592 MACRO__(0x8A5A, ## __VA_ARGS__), \
593 MACRO__(0x8A5B, ## __VA_ARGS__), \
594 MACRO__(0x8A5C, ## __VA_ARGS__), \
595 MACRO__(0x8A70, ## __VA_ARGS__), \
596 MACRO__(0x8A71, ## __VA_ARGS__)
597
598#define INTEL_ICL_IDS(MACRO__, ...) \
599 INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \
600 MACRO__(0x8A51, ## __VA_ARGS__), \
601 MACRO__(0x8A5D, ## __VA_ARGS__)
602
603/* EHL */
604#define INTEL_EHL_IDS(MACRO__, ...) \
605 MACRO__(0x4541, ## __VA_ARGS__), \
606 MACRO__(0x4551, ## __VA_ARGS__), \
607 MACRO__(0x4555, ## __VA_ARGS__), \
608 MACRO__(0x4557, ## __VA_ARGS__), \
609 MACRO__(0x4570, ## __VA_ARGS__), \
610 MACRO__(0x4571, ## __VA_ARGS__)
611
612/* JSL */
613#define INTEL_JSL_IDS(MACRO__, ...) \
614 MACRO__(0x4E51, ## __VA_ARGS__), \
615 MACRO__(0x4E55, ## __VA_ARGS__), \
616 MACRO__(0x4E57, ## __VA_ARGS__), \
617 MACRO__(0x4E61, ## __VA_ARGS__), \
618 MACRO__(0x4E71, ## __VA_ARGS__)
619
620/* TGL */
621#define INTEL_TGL_GT1_IDS(MACRO__, ...) \
622 MACRO__(0x9A60, ## __VA_ARGS__), \
623 MACRO__(0x9A68, ## __VA_ARGS__), \
624 MACRO__(0x9A70, ## __VA_ARGS__)
625
626#define INTEL_TGL_GT2_IDS(MACRO__, ...) \
627 MACRO__(0x9A40, ## __VA_ARGS__), \
628 MACRO__(0x9A49, ## __VA_ARGS__), \
629 MACRO__(0x9A59, ## __VA_ARGS__), \
630 MACRO__(0x9A78, ## __VA_ARGS__), \
631 MACRO__(0x9AC0, ## __VA_ARGS__), \
632 MACRO__(0x9AC9, ## __VA_ARGS__), \
633 MACRO__(0x9AD9, ## __VA_ARGS__), \
634 MACRO__(0x9AF8, ## __VA_ARGS__)
635
636#define INTEL_TGL_IDS(MACRO__, ...) \
637 INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \
638 INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
639
640/* RKL */
641#define INTEL_RKL_IDS(MACRO__, ...) \
642 MACRO__(0x4C80, ## __VA_ARGS__), \
643 MACRO__(0x4C8A, ## __VA_ARGS__), \
644 MACRO__(0x4C8B, ## __VA_ARGS__), \
645 MACRO__(0x4C8C, ## __VA_ARGS__), \
646 MACRO__(0x4C90, ## __VA_ARGS__), \
647 MACRO__(0x4C9A, ## __VA_ARGS__)
648
649/* DG1 */
650#define INTEL_DG1_IDS(MACRO__, ...) \
651 MACRO__(0x4905, ## __VA_ARGS__), \
652 MACRO__(0x4906, ## __VA_ARGS__), \
653 MACRO__(0x4907, ## __VA_ARGS__), \
654 MACRO__(0x4908, ## __VA_ARGS__), \
655 MACRO__(0x4909, ## __VA_ARGS__)
656
657/* ADL-S */
658#define INTEL_ADLS_IDS(MACRO__, ...) \
659 MACRO__(0x4680, ## __VA_ARGS__), \
660 MACRO__(0x4682, ## __VA_ARGS__), \
661 MACRO__(0x4688, ## __VA_ARGS__), \
662 MACRO__(0x468A, ## __VA_ARGS__), \
663 MACRO__(0x468B, ## __VA_ARGS__), \
664 MACRO__(0x4690, ## __VA_ARGS__), \
665 MACRO__(0x4692, ## __VA_ARGS__), \
666 MACRO__(0x4693, ## __VA_ARGS__)
667
668/* ADL-P */
669#define INTEL_ADLP_IDS(MACRO__, ...) \
670 MACRO__(0x46A0, ## __VA_ARGS__), \
671 MACRO__(0x46A1, ## __VA_ARGS__), \
672 MACRO__(0x46A2, ## __VA_ARGS__), \
673 MACRO__(0x46A3, ## __VA_ARGS__), \
674 MACRO__(0x46A6, ## __VA_ARGS__), \
675 MACRO__(0x46A8, ## __VA_ARGS__), \
676 MACRO__(0x46AA, ## __VA_ARGS__), \
677 MACRO__(0x462A, ## __VA_ARGS__), \
678 MACRO__(0x4626, ## __VA_ARGS__), \
679 MACRO__(0x4628, ## __VA_ARGS__), \
680 MACRO__(0x46B0, ## __VA_ARGS__), \
681 MACRO__(0x46B1, ## __VA_ARGS__), \
682 MACRO__(0x46B2, ## __VA_ARGS__), \
683 MACRO__(0x46B3, ## __VA_ARGS__), \
684 MACRO__(0x46C0, ## __VA_ARGS__), \
685 MACRO__(0x46C1, ## __VA_ARGS__), \
686 MACRO__(0x46C2, ## __VA_ARGS__), \
687 MACRO__(0x46C3, ## __VA_ARGS__)
688
689/* ADL-N */
690#define INTEL_ADLN_IDS(MACRO__, ...) \
691 MACRO__(0x46D0, ## __VA_ARGS__), \
692 MACRO__(0x46D1, ## __VA_ARGS__), \
693 MACRO__(0x46D2, ## __VA_ARGS__), \
694 MACRO__(0x46D3, ## __VA_ARGS__), \
695 MACRO__(0x46D4, ## __VA_ARGS__)
696
697/* RPL-S */
698#define INTEL_RPLS_IDS(MACRO__, ...) \
699 MACRO__(0xA780, ## __VA_ARGS__), \
700 MACRO__(0xA781, ## __VA_ARGS__), \
701 MACRO__(0xA782, ## __VA_ARGS__), \
702 MACRO__(0xA783, ## __VA_ARGS__), \
703 MACRO__(0xA788, ## __VA_ARGS__), \
704 MACRO__(0xA789, ## __VA_ARGS__), \
705 MACRO__(0xA78A, ## __VA_ARGS__), \
706 MACRO__(0xA78B, ## __VA_ARGS__)
707
708/* RPL-U */
709#define INTEL_RPLU_IDS(MACRO__, ...) \
710 MACRO__(0xA721, ## __VA_ARGS__), \
711 MACRO__(0xA7A1, ## __VA_ARGS__), \
712 MACRO__(0xA7A9, ## __VA_ARGS__), \
713 MACRO__(0xA7AC, ## __VA_ARGS__), \
714 MACRO__(0xA7AD, ## __VA_ARGS__)
715
716/* RPL-P */
717#define INTEL_RPLP_IDS(MACRO__, ...) \
718 MACRO__(0xA720, ## __VA_ARGS__), \
719 MACRO__(0xA7A0, ## __VA_ARGS__), \
720 MACRO__(0xA7A8, ## __VA_ARGS__), \
721 MACRO__(0xA7AA, ## __VA_ARGS__), \
722 MACRO__(0xA7AB, ## __VA_ARGS__)
723
724/* DG2 */
725#define INTEL_DG2_G10_D_IDS(MACRO__, ...) \
726 MACRO__(0x56A0, ## __VA_ARGS__), \
727 MACRO__(0x56A1, ## __VA_ARGS__), \
728 MACRO__(0x56A2, ## __VA_ARGS__)
729
730#define INTEL_DG2_G10_E_IDS(MACRO__, ...) \
731 MACRO__(0x56BE, ## __VA_ARGS__), \
732 MACRO__(0x56BF, ## __VA_ARGS__)
733
734#define INTEL_DG2_G10_M_IDS(MACRO__, ...) \
735 MACRO__(0x5690, ## __VA_ARGS__), \
736 MACRO__(0x5691, ## __VA_ARGS__), \
737 MACRO__(0x5692, ## __VA_ARGS__)
738
739#define INTEL_DG2_G10_IDS(MACRO__, ...) \
740 INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
741 INTEL_DG2_G10_E_IDS(MACRO__, ## __VA_ARGS__), \
742 INTEL_DG2_G10_M_IDS(MACRO__, ## __VA_ARGS__)
743
744#define INTEL_DG2_G11_D_IDS(MACRO__, ...) \
745 MACRO__(0x56A5, ## __VA_ARGS__), \
746 MACRO__(0x56A6, ## __VA_ARGS__), \
747 MACRO__(0x56B0, ## __VA_ARGS__), \
748 MACRO__(0x56B1, ## __VA_ARGS__)
749
750#define INTEL_DG2_G11_E_IDS(MACRO__, ...) \
751 MACRO__(0x56BA, ## __VA_ARGS__), \
752 MACRO__(0x56BB, ## __VA_ARGS__), \
753 MACRO__(0x56BC, ## __VA_ARGS__), \
754 MACRO__(0x56BD, ## __VA_ARGS__)
755
756#define INTEL_DG2_G11_M_IDS(MACRO__, ...) \
757 MACRO__(0x5693, ## __VA_ARGS__), \
758 MACRO__(0x5694, ## __VA_ARGS__), \
759 MACRO__(0x5695, ## __VA_ARGS__)
760
761#define INTEL_DG2_G11_IDS(MACRO__, ...) \
762 INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
763 INTEL_DG2_G11_E_IDS(MACRO__, ## __VA_ARGS__), \
764 INTEL_DG2_G11_M_IDS(MACRO__, ## __VA_ARGS__)
765
766#define INTEL_DG2_G12_D_IDS(MACRO__, ...) \
767 MACRO__(0x56A3, ## __VA_ARGS__), \
768 MACRO__(0x56A4, ## __VA_ARGS__), \
769 MACRO__(0x56B2, ## __VA_ARGS__), \
770 MACRO__(0x56B3, ## __VA_ARGS__)
771
772#define INTEL_DG2_G12_M_IDS(MACRO__, ...) \
773 MACRO__(0x5696, ## __VA_ARGS__), \
774 MACRO__(0x5697, ## __VA_ARGS__)
775
776#define INTEL_DG2_G12_IDS(MACRO__, ...) \
777 INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__), \
778 INTEL_DG2_G12_M_IDS(MACRO__, ## __VA_ARGS__)
779
780#define INTEL_DG2_D_IDS(MACRO__, ...) \
781 INTEL_DG2_G10_D_IDS(MACRO__, ## __VA_ARGS__), \
782 INTEL_DG2_G11_D_IDS(MACRO__, ## __VA_ARGS__), \
783 INTEL_DG2_G12_D_IDS(MACRO__, ## __VA_ARGS__)
784
785#define INTEL_DG2_IDS(MACRO__, ...) \
786 INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \
787 INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \
788 INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
789
790#define INTEL_ATS_M150_IDS(MACRO__, ...) \
791 MACRO__(0x56C0, ## __VA_ARGS__), \
792 MACRO__(0x56C2, ## __VA_ARGS__)
793
794#define INTEL_ATS_M75_IDS(MACRO__, ...) \
795 MACRO__(0x56C1, ## __VA_ARGS__)
796
797#define INTEL_ATS_M_IDS(MACRO__, ...) \
798 INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \
799 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
800
801/* ARL */
802#define INTEL_ARL_H_IDS(MACRO__, ...) \
803 MACRO__(0x7D51, ## __VA_ARGS__), \
804 MACRO__(0x7DD1, ## __VA_ARGS__)
805
806#define INTEL_ARL_U_IDS(MACRO__, ...) \
807 MACRO__(0x7D41, ## __VA_ARGS__) \
808
809#define INTEL_ARL_S_IDS(MACRO__, ...) \
810 MACRO__(0x7D67, ## __VA_ARGS__), \
811 MACRO__(0xB640, ## __VA_ARGS__)
812
813#define INTEL_ARL_IDS(MACRO__, ...) \
814 INTEL_ARL_H_IDS(MACRO__, ## __VA_ARGS__), \
815 INTEL_ARL_U_IDS(MACRO__, ## __VA_ARGS__), \
816 INTEL_ARL_S_IDS(MACRO__, ## __VA_ARGS__)
817
818/* MTL */
819#define INTEL_MTL_U_IDS(MACRO__, ...) \
820 MACRO__(0x7D40, ## __VA_ARGS__), \
821 MACRO__(0x7D45, ## __VA_ARGS__)
822
823#define INTEL_MTL_IDS(MACRO__, ...) \
824 INTEL_MTL_U_IDS(MACRO__, ## __VA_ARGS__), \
825 MACRO__(0x7D55, ## __VA_ARGS__), \
826 MACRO__(0x7D60, ## __VA_ARGS__), \
827 MACRO__(0x7DD5, ## __VA_ARGS__)
828
829/* PVC */
830#define INTEL_PVC_IDS(MACRO__, ...) \
831 MACRO__(0x0B69, ## __VA_ARGS__), \
832 MACRO__(0x0B6E, ## __VA_ARGS__), \
833 MACRO__(0x0BD4, ## __VA_ARGS__), \
834 MACRO__(0x0BD5, ## __VA_ARGS__), \
835 MACRO__(0x0BD6, ## __VA_ARGS__), \
836 MACRO__(0x0BD7, ## __VA_ARGS__), \
837 MACRO__(0x0BD8, ## __VA_ARGS__), \
838 MACRO__(0x0BD9, ## __VA_ARGS__), \
839 MACRO__(0x0BDA, ## __VA_ARGS__), \
840 MACRO__(0x0BDB, ## __VA_ARGS__), \
841 MACRO__(0x0BE0, ## __VA_ARGS__), \
842 MACRO__(0x0BE1, ## __VA_ARGS__), \
843 MACRO__(0x0BE5, ## __VA_ARGS__)
844
845/* LNL */
846#define INTEL_LNL_IDS(MACRO__, ...) \
847 MACRO__(0x6420, ## __VA_ARGS__), \
848 MACRO__(0x64A0, ## __VA_ARGS__), \
849 MACRO__(0x64B0, ## __VA_ARGS__)
850
851/* BMG */
852#define INTEL_BMG_G21_IDS(MACRO__, ...) \
853 MACRO__(0xE202, ## __VA_ARGS__), \
854 MACRO__(0xE209, ## __VA_ARGS__), \
855 MACRO__(0xE20B, ## __VA_ARGS__), \
856 MACRO__(0xE20C, ## __VA_ARGS__), \
857 MACRO__(0xE20D, ## __VA_ARGS__), \
858 MACRO__(0xE210, ## __VA_ARGS__), \
859 MACRO__(0xE211, ## __VA_ARGS__), \
860 MACRO__(0xE212, ## __VA_ARGS__), \
861 MACRO__(0xE216, ## __VA_ARGS__)
862
863#define INTEL_BMG_IDS(MACRO__, ...) \
864 INTEL_BMG_G21_IDS(MACRO__, ## __VA_ARGS__), \
865 MACRO__(0xE220, ## __VA_ARGS__), \
866 MACRO__(0xE221, ## __VA_ARGS__), \
867 MACRO__(0xE222, ## __VA_ARGS__), \
868 MACRO__(0xE223, ## __VA_ARGS__)
869
870/* PTL */
871#define INTEL_PTL_IDS(MACRO__, ...) \
872 MACRO__(0xB080, ## __VA_ARGS__), \
873 MACRO__(0xB081, ## __VA_ARGS__), \
874 MACRO__(0xB082, ## __VA_ARGS__), \
875 MACRO__(0xB083, ## __VA_ARGS__), \
876 MACRO__(0xB084, ## __VA_ARGS__), \
877 MACRO__(0xB085, ## __VA_ARGS__), \
878 MACRO__(0xB086, ## __VA_ARGS__), \
879 MACRO__(0xB087, ## __VA_ARGS__), \
880 MACRO__(0xB08F, ## __VA_ARGS__), \
881 MACRO__(0xB090, ## __VA_ARGS__), \
882 MACRO__(0xB0A0, ## __VA_ARGS__), \
883 MACRO__(0xB0B0, ## __VA_ARGS__)
884
885/* WCL */
886#define INTEL_WCL_IDS(MACRO__, ...) \
887 MACRO__(0xFD80, ## __VA_ARGS__), \
888 MACRO__(0xFD81, ## __VA_ARGS__)
889
890/* NVL-S */
891#define INTEL_NVLS_IDS(MACRO__, ...) \
892 MACRO__(0xD740, ## __VA_ARGS__), \
893 MACRO__(0xD741, ## __VA_ARGS__), \
894 MACRO__(0xD742, ## __VA_ARGS__), \
895 MACRO__(0xD743, ## __VA_ARGS__), \
896 MACRO__(0xD744, ## __VA_ARGS__), \
897 MACRO__(0xD745, ## __VA_ARGS__)
898
899/* CRI */
900#define INTEL_CRI_IDS(MACRO__, ...) \
901 MACRO__(0x674C, ## __VA_ARGS__)
902
903#endif /* __PCIIDS_H__ */