Linux kernel mirror (for testing)
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1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_H_
24#define _DRM_DP_H_
25
26#include <linux/types.h>
27
28/*
29 * Unless otherwise noted, all values are from the DP 1.1a spec. Note that
30 * DP and DPCD versions are independent. Differences from 1.0 are not noted,
31 * 1.0 devices basically don't exist in the wild.
32 *
33 * Abbreviations, in chronological order:
34 *
35 * eDP: Embedded DisplayPort version 1
36 * DPI: DisplayPort Interoperability Guideline v1.1a
37 * 1.2: DisplayPort 1.2
38 * MST: Multistream Transport - part of DP 1.2a
39 *
40 * 1.2 formally includes both eDP and DPI definitions.
41 */
42
43/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
44#define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
45#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN (1 << 8)
46#define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
47#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE (1 << 9)
48#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE (3 << 9)
49/* bits per component for non-RAW */
50#define DP_MSA_MISC_6_BPC (0 << 5)
51#define DP_MSA_MISC_8_BPC (1 << 5)
52#define DP_MSA_MISC_10_BPC (2 << 5)
53#define DP_MSA_MISC_12_BPC (3 << 5)
54#define DP_MSA_MISC_16_BPC (4 << 5)
55/* bits per component for RAW */
56#define DP_MSA_MISC_RAW_6_BPC (1 << 5)
57#define DP_MSA_MISC_RAW_7_BPC (2 << 5)
58#define DP_MSA_MISC_RAW_8_BPC (3 << 5)
59#define DP_MSA_MISC_RAW_10_BPC (4 << 5)
60#define DP_MSA_MISC_RAW_12_BPC (5 << 5)
61#define DP_MSA_MISC_RAW_14_BPC (6 << 5)
62#define DP_MSA_MISC_RAW_16_BPC (7 << 5)
63/* pixel encoding/colorimetry format */
64#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
65 ((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
66#define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67#define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70#define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71#define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72#define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
73#define DP_MSA_MISC_COLOR_YCBCR_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 1, 1)
74#define DP_MSA_MISC_COLOR_YCBCR_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 1, 0)
75#define DP_MSA_MISC_COLOR_YCBCR_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 1, 1)
76#define DP_MSA_MISC_COLOR_XVYCC_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 0, 0)
77#define DP_MSA_MISC_COLOR_XVYCC_422_BT709 _DP_MSA_MISC_COLOR(0, 1, 0, 1)
78#define DP_MSA_MISC_COLOR_XVYCC_444_BT601 _DP_MSA_MISC_COLOR(0, 2, 0, 0)
79#define DP_MSA_MISC_COLOR_XVYCC_444_BT709 _DP_MSA_MISC_COLOR(0, 2, 0, 1)
80#define DP_MSA_MISC_COLOR_OPRGB _DP_MSA_MISC_COLOR(0, 0, 1, 1)
81#define DP_MSA_MISC_COLOR_DCI_P3 _DP_MSA_MISC_COLOR(0, 3, 1, 0)
82#define DP_MSA_MISC_COLOR_COLOR_PROFILE _DP_MSA_MISC_COLOR(0, 3, 1, 1)
83#define DP_MSA_MISC_COLOR_VSC_SDP (1 << 14)
84
85#define DP_AUX_MAX_PAYLOAD_BYTES 16
86
87#define DP_AUX_I2C_WRITE 0x0
88#define DP_AUX_I2C_READ 0x1
89#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
90#define DP_AUX_I2C_MOT 0x4
91#define DP_AUX_NATIVE_WRITE 0x8
92#define DP_AUX_NATIVE_READ 0x9
93
94#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0)
95#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0)
96#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0)
97#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0)
98
99#define DP_AUX_I2C_REPLY_ACK (0x0 << 2)
100#define DP_AUX_I2C_REPLY_NACK (0x1 << 2)
101#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2)
102#define DP_AUX_I2C_REPLY_MASK (0x3 << 2)
103
104/* DPCD Field Address Mapping */
105
106/* Receiver Capability */
107#define DP_DPCD_REV 0x000
108# define DP_DPCD_REV_10 0x10
109# define DP_DPCD_REV_11 0x11
110# define DP_DPCD_REV_12 0x12
111# define DP_DPCD_REV_13 0x13
112# define DP_DPCD_REV_14 0x14
113
114#define DP_MAX_LINK_RATE 0x001
115
116#define DP_MAX_LANE_COUNT 0x002
117# define DP_MAX_LANE_COUNT_MASK 0x1f
118# define DP_POST_LT_ADJ_REQ_SUPPORTED (1 << 5) /* 1.3 */
119# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */
120# define DP_ENHANCED_FRAME_CAP (1 << 7)
121
122#define DP_MAX_DOWNSPREAD 0x003
123# define DP_MAX_DOWNSPREAD_0_5 (1 << 0)
124# define DP_STREAM_REGENERATION_STATUS_CAP (1 << 1) /* 2.0 */
125# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
126# define DP_TPS4_SUPPORTED (1 << 7)
127
128#define DP_NORP 0x004
129
130#define DP_DOWNSTREAMPORT_PRESENT 0x005
131# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
132# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
133# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1)
134# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1)
135# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1)
136# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1)
137# define DP_FORMAT_CONVERSION (1 << 3)
138# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */
139
140#define DP_MAIN_LINK_CHANNEL_CODING 0x006
141# define DP_CAP_ANSI_8B10B (1 << 0)
142# define DP_CAP_ANSI_128B132B (1 << 1) /* 2.0 */
143
144#define DP_DOWN_STREAM_PORT_COUNT 0x007
145# define DP_PORT_COUNT_MASK 0x0f
146# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
147# define DP_OUI_SUPPORT (1 << 7)
148
149#define DP_RECEIVE_PORT_0_CAP_0 0x008
150# define DP_LOCAL_EDID_PRESENT (1 << 1)
151# define DP_ASSOCIATED_TO_PRECEDING_PORT (1 << 2)
152# define DP_HBLANK_EXPANSION_CAPABLE (1 << 3)
153
154#define DP_RECEIVE_PORT_0_BUFFER_SIZE 0x009
155
156#define DP_RECEIVE_PORT_1_CAP_0 0x00a
157#define DP_RECEIVE_PORT_1_BUFFER_SIZE 0x00b
158
159#define DP_I2C_SPEED_CAP 0x00c /* DPI */
160# define DP_I2C_SPEED_1K 0x01
161# define DP_I2C_SPEED_5K 0x02
162# define DP_I2C_SPEED_10K 0x04
163# define DP_I2C_SPEED_100K 0x08
164# define DP_I2C_SPEED_400K 0x10
165# define DP_I2C_SPEED_1M 0x20
166
167#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
168# define DP_ALTERNATE_SCRAMBLER_RESET_CAP (1 << 0)
169# define DP_FRAMING_CHANGE_CAP (1 << 1)
170# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
171
172#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
173# define DP_TRAINING_AUX_RD_MASK 0x7F /* DP 1.3 */
174# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7) /* DP 1.3 */
175
176#define DP_ADAPTER_CAP 0x00f /* 1.2 */
177# define DP_FORCE_LOAD_SENSE_CAP (1 << 0)
178# define DP_ALTERNATE_I2C_PATTERN_CAP (1 << 1)
179
180#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
181# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
182
183/* Multiple stream transport */
184#define DP_FAUX_CAP 0x020 /* 1.2 */
185# define DP_FAUX_CAP_1 (1 << 0)
186
187#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 /* 2.0 */
188# define DP_FALLBACK_1024x768_60HZ_24BPP (1 << 0)
189# define DP_FALLBACK_1280x720_60HZ_24BPP (1 << 1)
190# define DP_FALLBACK_1920x1080_60HZ_24BPP (1 << 2)
191
192#define DP_MSTM_CAP 0x021 /* 1.2 */
193# define DP_MST_CAP (1 << 0)
194# define DP_SINGLE_STREAM_SIDEBAND_MSG (1 << 1) /* 2.0 */
195
196#define DP_NUMBER_OF_AUDIO_ENDPOINTS 0x022 /* 1.2 */
197
198/* AV_SYNC_DATA_BLOCK 1.2 */
199#define DP_AV_GRANULARITY 0x023
200# define DP_AG_FACTOR_MASK (0xf << 0)
201# define DP_AG_FACTOR_3MS (0 << 0)
202# define DP_AG_FACTOR_2MS (1 << 0)
203# define DP_AG_FACTOR_1MS (2 << 0)
204# define DP_AG_FACTOR_500US (3 << 0)
205# define DP_AG_FACTOR_200US (4 << 0)
206# define DP_AG_FACTOR_100US (5 << 0)
207# define DP_AG_FACTOR_10US (6 << 0)
208# define DP_AG_FACTOR_1US (7 << 0)
209# define DP_VG_FACTOR_MASK (0xf << 4)
210# define DP_VG_FACTOR_3MS (0 << 4)
211# define DP_VG_FACTOR_2MS (1 << 4)
212# define DP_VG_FACTOR_1MS (2 << 4)
213# define DP_VG_FACTOR_500US (3 << 4)
214# define DP_VG_FACTOR_200US (4 << 4)
215# define DP_VG_FACTOR_100US (5 << 4)
216
217#define DP_AUD_DEC_LAT0 0x024
218#define DP_AUD_DEC_LAT1 0x025
219
220#define DP_AUD_PP_LAT0 0x026
221#define DP_AUD_PP_LAT1 0x027
222
223#define DP_VID_INTER_LAT 0x028
224
225#define DP_VID_PROG_LAT 0x029
226
227#define DP_REP_LAT 0x02a
228
229#define DP_AUD_DEL_INS0 0x02b
230#define DP_AUD_DEL_INS1 0x02c
231#define DP_AUD_DEL_INS2 0x02d
232/* End of AV_SYNC_DATA_BLOCK */
233
234#define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */
235# define DP_ALPM_CAP (1 << 0)
236# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */
237# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */
238
239#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */
240# define DP_AUX_FRAME_SYNC_CAP (1 << 0)
241
242#define DP_GUID 0x030 /* 1.2 */
243
244#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */
245# define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0)
246# define DP_DSC_PASSTHROUGH_IS_SUPPORTED (1 << 1)
247# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2)
248# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3)
249
250#define DP_DSC_REV 0x061
251# define DP_DSC_MAJOR_MASK (0xf << 0)
252# define DP_DSC_MINOR_MASK (0xf << 4)
253# define DP_DSC_MAJOR_SHIFT 0
254# define DP_DSC_MINOR_SHIFT 4
255
256#define DP_DSC_RC_BUF_BLK_SIZE 0x062
257# define DP_DSC_RC_BUF_BLK_SIZE_1 0x0
258# define DP_DSC_RC_BUF_BLK_SIZE_4 0x1
259# define DP_DSC_RC_BUF_BLK_SIZE_16 0x2
260# define DP_DSC_RC_BUF_BLK_SIZE_64 0x3
261# define DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT 3 /* DP 2.1a, in units of 2 MPixels/sec */
262# define DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK (0x1f << DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT)
263
264#define DP_DSC_RC_BUF_SIZE 0x063
265
266#define DP_DSC_SLICE_CAP_1 0x064
267# define DP_DSC_1_PER_DP_DSC_SINK (1 << 0)
268# define DP_DSC_2_PER_DP_DSC_SINK (1 << 1)
269# define DP_DSC_4_PER_DP_DSC_SINK (1 << 3)
270# define DP_DSC_6_PER_DP_DSC_SINK (1 << 4)
271# define DP_DSC_8_PER_DP_DSC_SINK (1 << 5)
272# define DP_DSC_10_PER_DP_DSC_SINK (1 << 6)
273# define DP_DSC_12_PER_DP_DSC_SINK (1 << 7)
274
275#define DP_DSC_LINE_BUF_BIT_DEPTH 0x065
276# define DP_DSC_LINE_BUF_BIT_DEPTH_MASK (0xf << 0)
277# define DP_DSC_LINE_BUF_BIT_DEPTH_9 0x0
278# define DP_DSC_LINE_BUF_BIT_DEPTH_10 0x1
279# define DP_DSC_LINE_BUF_BIT_DEPTH_11 0x2
280# define DP_DSC_LINE_BUF_BIT_DEPTH_12 0x3
281# define DP_DSC_LINE_BUF_BIT_DEPTH_13 0x4
282# define DP_DSC_LINE_BUF_BIT_DEPTH_14 0x5
283# define DP_DSC_LINE_BUF_BIT_DEPTH_15 0x6
284# define DP_DSC_LINE_BUF_BIT_DEPTH_16 0x7
285# define DP_DSC_LINE_BUF_BIT_DEPTH_8 0x8
286
287#define DP_DSC_BLK_PREDICTION_SUPPORT 0x066
288# define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0)
289# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1)
290
291#define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */
292
293#define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */
294# define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0)
295# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK (0x3 << 5) /* eDP 1.5 & DP 2.0 */
296# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY (1 << 7) /* eDP 1.5 & DP 2.0 */
297
298#define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069
299# define DP_DSC_RGB (1 << 0)
300# define DP_DSC_YCbCr444 (1 << 1)
301# define DP_DSC_YCbCr422_Simple (1 << 2)
302# define DP_DSC_YCbCr422_Native (1 << 3)
303# define DP_DSC_YCbCr420_Native (1 << 4)
304
305#define DP_DSC_DEC_COLOR_DEPTH_CAP 0x06A
306# define DP_DSC_8_BPC (1 << 1)
307# define DP_DSC_10_BPC (1 << 2)
308# define DP_DSC_12_BPC (1 << 3)
309
310#define DP_DSC_PEAK_THROUGHPUT 0x06B
311# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
312# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
313# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
314# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
315# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
316# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
317# define DP_DSC_THROUGHPUT_MODE_0_500 (4 << 0)
318# define DP_DSC_THROUGHPUT_MODE_0_550 (5 << 0)
319# define DP_DSC_THROUGHPUT_MODE_0_600 (6 << 0)
320# define DP_DSC_THROUGHPUT_MODE_0_650 (7 << 0)
321# define DP_DSC_THROUGHPUT_MODE_0_700 (8 << 0)
322# define DP_DSC_THROUGHPUT_MODE_0_750 (9 << 0)
323# define DP_DSC_THROUGHPUT_MODE_0_800 (10 << 0)
324# define DP_DSC_THROUGHPUT_MODE_0_850 (11 << 0)
325# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
326# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
327# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
328# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */
329# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
330# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
331# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
332# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
333# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
334# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
335# define DP_DSC_THROUGHPUT_MODE_1_500 (4 << 4)
336# define DP_DSC_THROUGHPUT_MODE_1_550 (5 << 4)
337# define DP_DSC_THROUGHPUT_MODE_1_600 (6 << 4)
338# define DP_DSC_THROUGHPUT_MODE_1_650 (7 << 4)
339# define DP_DSC_THROUGHPUT_MODE_1_700 (8 << 4)
340# define DP_DSC_THROUGHPUT_MODE_1_750 (9 << 4)
341# define DP_DSC_THROUGHPUT_MODE_1_800 (10 << 4)
342# define DP_DSC_THROUGHPUT_MODE_1_850 (11 << 4)
343# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
344# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
345# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
346# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
347
348#define DP_DSC_MAX_SLICE_WIDTH 0x06C
349#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
350#define DP_DSC_SLICE_WIDTH_MULTIPLIER 320
351
352#define DP_DSC_SLICE_CAP_2 0x06D
353# define DP_DSC_16_PER_DP_DSC_SINK (1 << 0)
354# define DP_DSC_20_PER_DP_DSC_SINK (1 << 1)
355# define DP_DSC_24_PER_DP_DSC_SINK (1 << 2)
356
357#define DP_DSC_BITS_PER_PIXEL_INC 0x06F
358# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f
359# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0
360# define DP_DSC_BITS_PER_PIXEL_1_16 0x0
361# define DP_DSC_BITS_PER_PIXEL_1_8 0x1
362# define DP_DSC_BITS_PER_PIXEL_1_4 0x2
363# define DP_DSC_BITS_PER_PIXEL_1_2 0x3
364# define DP_DSC_BITS_PER_PIXEL_1_1 0x4
365# define DP_DSC_BITS_PER_PIXEL_MASK 0x7
366
367#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */
368# define DP_PSR_IS_SUPPORTED 1
369# define DP_PSR2_IS_SUPPORTED 2 /* eDP 1.4 */
370# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */
371# define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */
372
373#define DP_PSR_CAPS 0x071 /* XXX 1.2? */
374# define DP_PSR_NO_TRAIN_ON_EXIT 1
375# define DP_PSR_SETUP_TIME_330 (0 << 1)
376# define DP_PSR_SETUP_TIME_275 (1 << 1)
377# define DP_PSR_SETUP_TIME_220 (2 << 1)
378# define DP_PSR_SETUP_TIME_165 (3 << 1)
379# define DP_PSR_SETUP_TIME_110 (4 << 1)
380# define DP_PSR_SETUP_TIME_55 (5 << 1)
381# define DP_PSR_SETUP_TIME_0 (6 << 1)
382# define DP_PSR_SETUP_TIME_MASK (7 << 1)
383# define DP_PSR_SETUP_TIME_SHIFT 1
384# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */
385# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */
386# define DP_PSR2_SU_AUX_FRAME_SYNC_NOT_NEEDED (1 << 6)/* eDP 1.5, adopted eDP 1.4b SCR */
387
388#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */
389#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */
390
391/*
392 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
393 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
394 * each port's descriptor is one byte wide. If it was set, each port's is
395 * four bytes wide, starting with the one byte from the base info. As of
396 * DP interop v1.1a only VGA defines additional detail.
397 */
398
399/* offset 0 */
400#define DP_DOWNSTREAM_PORT_0 0x80
401# define DP_DS_PORT_TYPE_MASK (7 << 0)
402# define DP_DS_PORT_TYPE_DP 0
403# define DP_DS_PORT_TYPE_VGA 1
404# define DP_DS_PORT_TYPE_DVI 2
405# define DP_DS_PORT_TYPE_HDMI 3
406# define DP_DS_PORT_TYPE_NON_EDID 4
407# define DP_DS_PORT_TYPE_DP_DUALMODE 5
408# define DP_DS_PORT_TYPE_WIRELESS 6
409# define DP_DS_PORT_HPD (1 << 3)
410# define DP_DS_NON_EDID_MASK (0xf << 4)
411# define DP_DS_NON_EDID_720x480i_60 (1 << 4)
412# define DP_DS_NON_EDID_720x480i_50 (2 << 4)
413# define DP_DS_NON_EDID_1920x1080i_60 (3 << 4)
414# define DP_DS_NON_EDID_1920x1080i_50 (4 << 4)
415# define DP_DS_NON_EDID_1280x720_60 (5 << 4)
416# define DP_DS_NON_EDID_1280x720_50 (7 << 4)
417/* offset 1 for VGA is maximum megapixels per second / 8 */
418/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
419/* offset 2 for VGA/DVI/HDMI */
420# define DP_DS_MAX_BPC_MASK (3 << 0)
421# define DP_DS_8BPC 0
422# define DP_DS_10BPC 1
423# define DP_DS_12BPC 2
424# define DP_DS_16BPC 3
425/* HDMI2.1 PCON FRL CONFIGURATION */
426# define DP_PCON_MAX_FRL_BW (7 << 2)
427# define DP_PCON_MAX_0GBPS (0 << 2)
428# define DP_PCON_MAX_9GBPS (1 << 2)
429# define DP_PCON_MAX_18GBPS (2 << 2)
430# define DP_PCON_MAX_24GBPS (3 << 2)
431# define DP_PCON_MAX_32GBPS (4 << 2)
432# define DP_PCON_MAX_40GBPS (5 << 2)
433# define DP_PCON_MAX_48GBPS (6 << 2)
434# define DP_PCON_SOURCE_CTL_MODE (1 << 5)
435
436/* offset 3 for DVI */
437# define DP_DS_DVI_DUAL_LINK (1 << 1)
438# define DP_DS_DVI_HIGH_COLOR_DEPTH (1 << 2)
439/* offset 3 for HDMI */
440# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
441# define DP_DS_HDMI_YCBCR422_PASS_THROUGH (1 << 1)
442# define DP_DS_HDMI_YCBCR420_PASS_THROUGH (1 << 2)
443# define DP_DS_HDMI_YCBCR444_TO_422_CONV (1 << 3)
444# define DP_DS_HDMI_YCBCR444_TO_420_CONV (1 << 4)
445
446/*
447 * VESA DP-to-HDMI PCON Specification adds caps for colorspace
448 * conversion in DFP cap DPCD 83h. Sec6.1 Table-3.
449 * Based on the available support the source can enable
450 * color conversion by writing into PROTOCOL_COVERTER_CONTROL_2
451 * DPCD 3052h.
452 */
453# define DP_DS_HDMI_BT601_RGB_YCBCR_CONV (1 << 5)
454# define DP_DS_HDMI_BT709_RGB_YCBCR_CONV (1 << 6)
455# define DP_DS_HDMI_BT2020_RGB_YCBCR_CONV (1 << 7)
456
457#define DP_MAX_DOWNSTREAM_PORTS 0x10
458
459/* DP Forward error Correction Registers */
460#define DP_FEC_CAPABILITY 0x090 /* 1.4 */
461# define DP_FEC_CAPABLE (1 << 0)
462# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
463# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
464# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
465#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
466
467/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
468#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xD /* 0x92 through 0x9E */
469#define DP_PCON_DSC_ENCODER 0x092
470# define DP_PCON_DSC_ENCODER_SUPPORTED (1 << 0)
471# define DP_PCON_DSC_PPS_ENC_OVERRIDE (1 << 1)
472
473/* DP-HDMI2.1 PCON DSC Version */
474#define DP_PCON_DSC_VERSION 0x093
475# define DP_PCON_DSC_MAJOR_MASK (0xF << 0)
476# define DP_PCON_DSC_MINOR_MASK (0xF << 4)
477# define DP_PCON_DSC_MAJOR_SHIFT 0
478# define DP_PCON_DSC_MINOR_SHIFT 4
479
480/* DP-HDMI2.1 PCON DSC RC Buffer block size */
481#define DP_PCON_DSC_RC_BUF_BLK_INFO 0x094
482# define DP_PCON_DSC_RC_BUF_BLK_SIZE (0x3 << 0)
483# define DP_PCON_DSC_RC_BUF_BLK_1KB 0
484# define DP_PCON_DSC_RC_BUF_BLK_4KB 1
485# define DP_PCON_DSC_RC_BUF_BLK_16KB 2
486# define DP_PCON_DSC_RC_BUF_BLK_64KB 3
487
488/* DP-HDMI2.1 PCON DSC RC Buffer size */
489#define DP_PCON_DSC_RC_BUF_SIZE 0x095
490
491/* DP-HDMI2.1 PCON DSC Slice capabilities-1 */
492#define DP_PCON_DSC_SLICE_CAP_1 0x096
493# define DP_PCON_DSC_1_PER_DSC_ENC (0x1 << 0)
494# define DP_PCON_DSC_2_PER_DSC_ENC (0x1 << 1)
495# define DP_PCON_DSC_4_PER_DSC_ENC (0x1 << 3)
496# define DP_PCON_DSC_6_PER_DSC_ENC (0x1 << 4)
497# define DP_PCON_DSC_8_PER_DSC_ENC (0x1 << 5)
498# define DP_PCON_DSC_10_PER_DSC_ENC (0x1 << 6)
499# define DP_PCON_DSC_12_PER_DSC_ENC (0x1 << 7)
500
501#define DP_PCON_DSC_BUF_BIT_DEPTH 0x097
502# define DP_PCON_DSC_BIT_DEPTH_MASK (0xF << 0)
503# define DP_PCON_DSC_DEPTH_9_BITS 0
504# define DP_PCON_DSC_DEPTH_10_BITS 1
505# define DP_PCON_DSC_DEPTH_11_BITS 2
506# define DP_PCON_DSC_DEPTH_12_BITS 3
507# define DP_PCON_DSC_DEPTH_13_BITS 4
508# define DP_PCON_DSC_DEPTH_14_BITS 5
509# define DP_PCON_DSC_DEPTH_15_BITS 6
510# define DP_PCON_DSC_DEPTH_16_BITS 7
511# define DP_PCON_DSC_DEPTH_8_BITS 8
512
513#define DP_PCON_DSC_BLOCK_PREDICTION 0x098
514# define DP_PCON_DSC_BLOCK_PRED_SUPPORT (0x1 << 0)
515
516#define DP_PCON_DSC_ENC_COLOR_FMT_CAP 0x099
517# define DP_PCON_DSC_ENC_RGB (0x1 << 0)
518# define DP_PCON_DSC_ENC_YUV444 (0x1 << 1)
519# define DP_PCON_DSC_ENC_YUV422_S (0x1 << 2)
520# define DP_PCON_DSC_ENC_YUV422_N (0x1 << 3)
521# define DP_PCON_DSC_ENC_YUV420_N (0x1 << 4)
522
523#define DP_PCON_DSC_ENC_COLOR_DEPTH_CAP 0x09A
524# define DP_PCON_DSC_ENC_8BPC (0x1 << 1)
525# define DP_PCON_DSC_ENC_10BPC (0x1 << 2)
526# define DP_PCON_DSC_ENC_12BPC (0x1 << 3)
527
528#define DP_PCON_DSC_MAX_SLICE_WIDTH 0x09B
529
530/* DP-HDMI2.1 PCON DSC Slice capabilities-2 */
531#define DP_PCON_DSC_SLICE_CAP_2 0x09C
532# define DP_PCON_DSC_16_PER_DSC_ENC (0x1 << 0)
533# define DP_PCON_DSC_20_PER_DSC_ENC (0x1 << 1)
534# define DP_PCON_DSC_24_PER_DSC_ENC (0x1 << 2)
535
536/* DP-HDMI2.1 PCON HDMI TX Encoder Bits/pixel increment */
537#define DP_PCON_DSC_BPP_INCR 0x09E
538# define DP_PCON_DSC_BPP_INCR_MASK (0x7 << 0)
539# define DP_PCON_DSC_ONE_16TH_BPP 0
540# define DP_PCON_DSC_ONE_8TH_BPP 1
541# define DP_PCON_DSC_ONE_4TH_BPP 2
542# define DP_PCON_DSC_ONE_HALF_BPP 3
543# define DP_PCON_DSC_ONE_BPP 4
544
545/* DP Extended DSC Capabilities */
546#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
547#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
548#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
549
550/* DFP Capability Extension */
551#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
552
553#define DP_PANEL_REPLAY_CAP_SUPPORT 0x0b0 /* DP 2.0 */
554# define DP_PANEL_REPLAY_SUPPORT (1 << 0)
555# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1)
556# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* eDP 1.5 */
557
558#define DP_PANEL_REPLAY_CAP_SIZE 7
559
560#define DP_PANEL_REPLAY_CAP_CAPABILITY 0xb1
561# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT 1 /* DP 2.1a */
562# define DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_MASK (3 << DP_PANEL_REPLAY_DSC_DECODE_CAPABILITY_IN_PR_SHIFT)
563# define DP_DSC_DECODE_CAPABILITY_IN_PR_SUPPORTED 0x00
564# define DP_DSC_DECODE_CAPABILITY_IN_PR_FULL_FRAME_ONLY 0x01
565# define DP_DSC_DECODE_CAPABILITY_IN_PR_NOT_SUPPORTED 0x02
566# define DP_DSC_DECODE_CAPABILITY_IN_PR_RESERVED 0x03
567# define DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR (1 << 3)
568# define DP_PANEL_REPLAY_DSC_CRC_OF_MULTIPLE_SUS_SUPPORTED (1 << 4)
569# define DP_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5)
570# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_SUPPORTED (1 << 6)
571# define DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP (1 << 7)
572
573#define DP_PANEL_REPLAY_CAP_X_GRANULARITY 0xb2
574#define DP_PANEL_REPLAY_CAP_Y_GRANULARITY 0xb4
575
576/* Link Configuration */
577#define DP_LINK_BW_SET 0x100
578# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
579# define DP_LINK_BW_1_62 0x06
580# define DP_LINK_BW_2_7 0x0a
581# define DP_LINK_BW_5_4 0x14 /* 1.2 */
582# define DP_LINK_BW_8_1 0x1e /* 1.4 */
583# define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */
584# define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */
585# define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */
586
587#define DP_LANE_COUNT_SET 0x101
588# define DP_LANE_COUNT_MASK 0x0f
589# define DP_POST_LT_ADJ_REQ_GRANTED (1 << 5) /* 1.3 */
590# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
591
592#define DP_TRAINING_PATTERN_SET 0x102
593# define DP_TRAINING_PATTERN_DISABLE 0
594# define DP_TRAINING_PATTERN_1 1
595# define DP_TRAINING_PATTERN_2 2
596# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
597# define DP_TRAINING_PATTERN_3 3 /* 1.2 */
598# define DP_TRAINING_PATTERN_4 7 /* 1.4 */
599# define DP_TRAINING_PATTERN_MASK 0x3
600# define DP_TRAINING_PATTERN_MASK_1_4 0xf
601
602/* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
603# define DP_LINK_QUAL_PATTERN_11_DISABLE (0 << 2)
604# define DP_LINK_QUAL_PATTERN_11_D10_2 (1 << 2)
605# define DP_LINK_QUAL_PATTERN_11_ERROR_RATE (2 << 2)
606# define DP_LINK_QUAL_PATTERN_11_PRBS7 (3 << 2)
607# define DP_LINK_QUAL_PATTERN_11_MASK (3 << 2)
608
609# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
610# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
611
612# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
613# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
614# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
615# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
616
617#define DP_TRAINING_LANE0_SET 0x103
618#define DP_TRAINING_LANE1_SET 0x104
619#define DP_TRAINING_LANE2_SET 0x105
620#define DP_TRAINING_LANE3_SET 0x106
621
622# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
623# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
624# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
625# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
626# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0)
627# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0)
628# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0)
629
630# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
631# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3)
632# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3)
633# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3)
634# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
635
636# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
637# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
638
639# define DP_TX_FFE_PRESET_VALUE_MASK (0xf << 0) /* 2.0 128b/132b Link Layer */
640
641#define DP_DOWNSPREAD_CTRL 0x107
642# define DP_SPREAD_AMP_0_5 (1 << 4)
643# define DP_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE (1 << 6)
644# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */
645
646#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
647# define DP_SET_ANSI_8B10B (1 << 0)
648# define DP_SET_ANSI_128B132B (1 << 1)
649
650#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */
651/* bitmask as for DP_I2C_SPEED_CAP */
652
653#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */
654# define DP_ALTERNATE_SCRAMBLER_RESET_ENABLE (1 << 0)
655# define DP_FRAMING_CHANGE_ENABLE (1 << 1)
656# define DP_PANEL_SELF_TEST_ENABLE (1 << 7)
657
658#define DP_LINK_QUAL_LANE0_SET 0x10b /* DPCD >= 1.2 */
659#define DP_LINK_QUAL_LANE1_SET 0x10c
660#define DP_LINK_QUAL_LANE2_SET 0x10d
661#define DP_LINK_QUAL_LANE3_SET 0x10e
662# define DP_LINK_QUAL_PATTERN_DISABLE 0
663# define DP_LINK_QUAL_PATTERN_D10_2 1
664# define DP_LINK_QUAL_PATTERN_ERROR_RATE 2
665# define DP_LINK_QUAL_PATTERN_PRBS7 3
666# define DP_LINK_QUAL_PATTERN_80BIT_CUSTOM 4
667# define DP_LINK_QUAL_PATTERN_CP2520_PAT_1 5
668# define DP_LINK_QUAL_PATTERN_CP2520_PAT_2 6
669# define DP_LINK_QUAL_PATTERN_CP2520_PAT_3 7
670/* DP 2.0 UHBR10, UHBR13.5, UHBR20 */
671# define DP_LINK_QUAL_PATTERN_128B132B_TPS1 0x08
672# define DP_LINK_QUAL_PATTERN_128B132B_TPS2 0x10
673# define DP_LINK_QUAL_PATTERN_PRSBS9 0x18
674# define DP_LINK_QUAL_PATTERN_PRSBS11 0x20
675# define DP_LINK_QUAL_PATTERN_PRSBS15 0x28
676# define DP_LINK_QUAL_PATTERN_PRSBS23 0x30
677# define DP_LINK_QUAL_PATTERN_PRSBS31 0x38
678# define DP_LINK_QUAL_PATTERN_CUSTOM 0x40
679# define DP_LINK_QUAL_PATTERN_SQUARE 0x48
680# define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DISABLED 0x49
681# define DP_LINK_QUAL_PATTERN_SQUARE_DEEMPHASIS_DISABLED 0x4a
682# define DP_LINK_QUAL_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED 0x4b
683
684#define DP_TRAINING_LANE0_1_SET2 0x10f
685#define DP_TRAINING_LANE2_3_SET2 0x110
686# define DP_LANE02_POST_CURSOR2_SET_MASK (3 << 0)
687# define DP_LANE02_MAX_POST_CURSOR2_REACHED (1 << 2)
688# define DP_LANE13_POST_CURSOR2_SET_MASK (3 << 4)
689# define DP_LANE13_MAX_POST_CURSOR2_REACHED (1 << 6)
690
691#define DP_MSTM_CTRL 0x111 /* 1.2 */
692# define DP_MST_EN (1 << 0)
693# define DP_UP_REQ_EN (1 << 1)
694# define DP_UPSTREAM_IS_SRC (1 << 2)
695
696#define DP_AUDIO_DELAY0 0x112 /* 1.2 */
697#define DP_AUDIO_DELAY1 0x113
698#define DP_AUDIO_DELAY2 0x114
699
700#define DP_LINK_RATE_SET 0x115 /* eDP 1.4 */
701# define DP_LINK_RATE_SET_SHIFT 0
702# define DP_LINK_RATE_SET_MASK (7 << 0)
703
704#define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */
705# define DP_ALPM_ENABLE (1 << 0)
706# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */
707# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */
708
709#define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */
710# define DP_AUX_FRAME_SYNC_ENABLE (1 << 0)
711# define DP_IRQ_HPD_ENABLE (1 << 1)
712
713#define DP_UPSTREAM_DEVICE_DP_PWR_NEED 0x118 /* 1.2 */
714# define DP_PWR_NOT_NEEDED (1 << 0)
715
716#define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT 0x119 /* 1.4a */
717# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED (1 << 0)
718
719#define DP_FEC_CONFIGURATION 0x120 /* 1.4 */
720# define DP_FEC_READY (1 << 0)
721# define DP_FEC_ERR_COUNT_SEL_MASK (7 << 1)
722# define DP_FEC_ERR_COUNT_DIS (0 << 1)
723# define DP_FEC_UNCORR_BLK_ERROR_COUNT (1 << 1)
724# define DP_FEC_CORR_BLK_ERROR_COUNT (2 << 1)
725# define DP_FEC_BIT_ERROR_COUNT (3 << 1)
726# define DP_FEC_LANE_SELECT_MASK (3 << 4)
727# define DP_FEC_LANE_0_SELECT (0 << 4)
728# define DP_FEC_LANE_1_SELECT (1 << 4)
729# define DP_FEC_LANE_2_SELECT (2 << 4)
730# define DP_FEC_LANE_3_SELECT (3 << 4)
731
732#define DP_SDP_ERROR_DETECTION_CONFIGURATION 0x121 /* DP 2.0 E11 */
733#define DP_SDP_CRC16_128B132B_EN BIT(0)
734
735#define DP_AUX_FRAME_SYNC_VALUE 0x15c /* eDP 1.4 */
736# define DP_AUX_FRAME_SYNC_VALID (1 << 0)
737
738#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
739# define DP_DECOMPRESSION_EN (1 << 0)
740# define DP_DSC_PASSTHROUGH_EN (1 << 1)
741#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
742
743#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
744# define DP_PSR_ENABLE BIT(0)
745# define DP_PSR_MAIN_LINK_ACTIVE BIT(1)
746# define DP_PSR_CRC_VERIFICATION BIT(2)
747# define DP_PSR_FRAME_CAPTURE BIT(3)
748# define DP_PSR_SU_REGION_SCANLINE_CAPTURE BIT(4) /* eDP 1.4a */
749# define DP_PSR_IRQ_HPD_WITH_CRC_ERRORS BIT(5) /* eDP 1.4a */
750# define DP_PSR_ENABLE_PSR2 BIT(6) /* eDP 1.4a */
751# define DP_PSR_ENABLE_SU_REGION_ET BIT(7) /* eDP 1.5 */
752
753#define DP_ADAPTER_CTRL 0x1a0
754# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0)
755
756#define DP_BRANCH_DEVICE_CTRL 0x1a1
757# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
758
759#define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */
760# define DP_PANEL_REPLAY_ENABLE (1 << 0)
761# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 */
762# define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3)
763# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4)
764# define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5)
765# define DP_PANEL_REPLAY_SU_ENABLE (1 << 6)
766# define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1 << 7) /* DP 2.1 */
767
768#define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */
769# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0)
770# define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1)
771# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2)
772# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3
773# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3)
774# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7)
775
776#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
777#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
778#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
779
780/* Link/Sink Device Status */
781#define DP_SINK_COUNT 0x200
782/* prior to 1.2 bit 7 was reserved mbz */
783# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f))
784# define DP_SINK_CP_READY (1 << 6)
785
786#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
787# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
788# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
789# define DP_CP_IRQ (1 << 2)
790# define DP_MCCS_IRQ (1 << 3)
791# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */
792# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */
793# define DP_SINK_SPECIFIC_IRQ (1 << 6)
794
795#define DP_LANE0_1_STATUS 0x202
796#define DP_LANE2_3_STATUS 0x203
797# define DP_LANE_CR_DONE (1 << 0)
798# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
799# define DP_LANE_SYMBOL_LOCKED (1 << 2)
800
801#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
802 DP_LANE_CHANNEL_EQ_DONE | \
803 DP_LANE_SYMBOL_LOCKED)
804
805#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
806#define DP_INTERLANE_ALIGN_DONE (1 << 0)
807#define DP_POST_LT_ADJ_REQ_IN_PROGRESS (1 << 1) /* 1.3 */
808#define DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE (1 << 2) /* 2.0 E11 */
809#define DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE (1 << 3) /* 2.0 E11 */
810#define DP_128B132B_LT_FAILED (1 << 4) /* 2.0 E11 */
811#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
812#define DP_LINK_STATUS_UPDATED (1 << 7)
813
814#define DP_SINK_STATUS 0x205
815# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
816# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
817# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
818# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
819
820#define DP_ADJUST_REQUEST_LANE0_1 0x206
821#define DP_ADJUST_REQUEST_LANE2_3 0x207
822# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
823# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
824# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
825# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
826# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
827# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
828# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
829# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
830
831/* DP 2.0 128b/132b Link Layer */
832# define DP_ADJUST_TX_FFE_PRESET_LANE0_MASK (0xf << 0)
833# define DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT 0
834# define DP_ADJUST_TX_FFE_PRESET_LANE1_MASK (0xf << 4)
835# define DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT 4
836
837#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c
838# define DP_ADJUST_POST_CURSOR2_LANE0_MASK 0x03
839# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
840# define DP_ADJUST_POST_CURSOR2_LANE1_MASK 0x0c
841# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
842# define DP_ADJUST_POST_CURSOR2_LANE2_MASK 0x30
843# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
844# define DP_ADJUST_POST_CURSOR2_LANE3_MASK 0xc0
845# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
846
847#define DP_TEST_REQUEST 0x218
848# define DP_TEST_LINK_TRAINING (1 << 0)
849# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1)
850# define DP_TEST_LINK_EDID_READ (1 << 2)
851# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
852# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */
853# define DP_TEST_LINK_AUDIO_PATTERN (1 << 5) /* DPCD >= 1.2 */
854# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO (1 << 6) /* DPCD >= 1.2 */
855
856#define DP_TEST_LINK_RATE 0x219
857# define DP_LINK_RATE_162 (0x6)
858# define DP_LINK_RATE_27 (0xa)
859
860#define DP_TEST_LANE_COUNT 0x220
861
862#define DP_TEST_PATTERN 0x221
863# define DP_NO_TEST_PATTERN 0x0
864# define DP_COLOR_RAMP 0x1
865# define DP_BLACK_AND_WHITE_VERTICAL_LINES 0x2
866# define DP_COLOR_SQUARE 0x3
867
868#define DP_TEST_H_TOTAL_HI 0x222
869#define DP_TEST_H_TOTAL_LO 0x223
870
871#define DP_TEST_V_TOTAL_HI 0x224
872#define DP_TEST_V_TOTAL_LO 0x225
873
874#define DP_TEST_H_START_HI 0x226
875#define DP_TEST_H_START_LO 0x227
876
877#define DP_TEST_V_START_HI 0x228
878#define DP_TEST_V_START_LO 0x229
879
880#define DP_TEST_HSYNC_HI 0x22A
881# define DP_TEST_HSYNC_POLARITY (1 << 7)
882# define DP_TEST_HSYNC_WIDTH_HI_MASK (127 << 0)
883#define DP_TEST_HSYNC_WIDTH_LO 0x22B
884
885#define DP_TEST_VSYNC_HI 0x22C
886# define DP_TEST_VSYNC_POLARITY (1 << 7)
887# define DP_TEST_VSYNC_WIDTH_HI_MASK (127 << 0)
888#define DP_TEST_VSYNC_WIDTH_LO 0x22D
889
890#define DP_TEST_H_WIDTH_HI 0x22E
891#define DP_TEST_H_WIDTH_LO 0x22F
892
893#define DP_TEST_V_HEIGHT_HI 0x230
894#define DP_TEST_V_HEIGHT_LO 0x231
895
896#define DP_TEST_MISC0 0x232
897# define DP_TEST_SYNC_CLOCK (1 << 0)
898# define DP_TEST_COLOR_FORMAT_MASK (3 << 1)
899# define DP_TEST_COLOR_FORMAT_SHIFT 1
900# define DP_COLOR_FORMAT_RGB (0 << 1)
901# define DP_COLOR_FORMAT_YCbCr422 (1 << 1)
902# define DP_COLOR_FORMAT_YCbCr444 (2 << 1)
903# define DP_TEST_DYNAMIC_RANGE_VESA (0 << 3)
904# define DP_TEST_DYNAMIC_RANGE_CEA (1 << 3)
905# define DP_TEST_YCBCR_COEFFICIENTS (1 << 4)
906# define DP_YCBCR_COEFFICIENTS_ITU601 (0 << 4)
907# define DP_YCBCR_COEFFICIENTS_ITU709 (1 << 4)
908# define DP_TEST_BIT_DEPTH_MASK (7 << 5)
909# define DP_TEST_BIT_DEPTH_SHIFT 5
910# define DP_TEST_BIT_DEPTH_6 (0 << 5)
911# define DP_TEST_BIT_DEPTH_8 (1 << 5)
912# define DP_TEST_BIT_DEPTH_10 (2 << 5)
913# define DP_TEST_BIT_DEPTH_12 (3 << 5)
914# define DP_TEST_BIT_DEPTH_16 (4 << 5)
915
916#define DP_TEST_MISC1 0x233
917# define DP_TEST_REFRESH_DENOMINATOR (1 << 0)
918# define DP_TEST_INTERLACED (1 << 1)
919
920#define DP_TEST_REFRESH_RATE_NUMERATOR 0x234
921
922#define DP_TEST_MISC0 0x232
923
924#define DP_TEST_CRC_R_CR 0x240
925#define DP_TEST_CRC_G_Y 0x242
926#define DP_TEST_CRC_B_CB 0x244
927
928#define DP_TEST_SINK_MISC 0x246
929# define DP_TEST_CRC_SUPPORTED (1 << 5)
930# define DP_TEST_COUNT_MASK 0xf
931
932#define DP_PHY_TEST_PATTERN 0x248
933# define DP_PHY_TEST_PATTERN_SEL_MASK 0x7
934# define DP_PHY_TEST_PATTERN_NONE 0x0
935# define DP_PHY_TEST_PATTERN_D10_2 0x1
936# define DP_PHY_TEST_PATTERN_ERROR_COUNT 0x2
937# define DP_PHY_TEST_PATTERN_PRBS7 0x3
938# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
939# define DP_PHY_TEST_PATTERN_CP2520 0x5
940
941#define DP_PHY_SQUARE_PATTERN 0x249
942
943#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
944#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
945#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
946#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
947#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253
948#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254
949#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255
950#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256
951#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257
952#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258
953#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259
954
955#define DP_TEST_RESPONSE 0x260
956# define DP_TEST_ACK (1 << 0)
957# define DP_TEST_NAK (1 << 1)
958# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
959
960#define DP_TEST_EDID_CHECKSUM 0x261
961
962#define DP_TEST_SINK 0x270
963# define DP_TEST_SINK_START (1 << 0)
964#define DP_TEST_AUDIO_MODE 0x271
965#define DP_TEST_AUDIO_PATTERN_TYPE 0x272
966#define DP_TEST_AUDIO_PERIOD_CH1 0x273
967#define DP_TEST_AUDIO_PERIOD_CH2 0x274
968#define DP_TEST_AUDIO_PERIOD_CH3 0x275
969#define DP_TEST_AUDIO_PERIOD_CH4 0x276
970#define DP_TEST_AUDIO_PERIOD_CH5 0x277
971#define DP_TEST_AUDIO_PERIOD_CH6 0x278
972#define DP_TEST_AUDIO_PERIOD_CH7 0x279
973#define DP_TEST_AUDIO_PERIOD_CH8 0x27A
974
975#define DP_FEC_STATUS 0x280 /* 1.4 */
976# define DP_FEC_DECODE_EN_DETECTED (1 << 0)
977# define DP_FEC_DECODE_DIS_DETECTED (1 << 1)
978
979#define DP_FEC_ERROR_COUNT_LSB 0x0281 /* 1.4 */
980
981#define DP_FEC_ERROR_COUNT_MSB 0x0282 /* 1.4 */
982# define DP_FEC_ERROR_COUNT_MASK 0x7F
983# define DP_FEC_ERR_COUNT_VALID (1 << 7)
984
985#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */
986# define DP_PAYLOAD_TABLE_UPDATED (1 << 0)
987# define DP_PAYLOAD_ACT_HANDLED (1 << 1)
988
989#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */
990/* up to ID_SLOT_63 at 0x2ff */
991
992/* Source Device-specific */
993#define DP_SOURCE_OUI 0x300
994
995/* Sink Device-specific */
996#define DP_SINK_OUI 0x400
997
998/* Branch Device-specific */
999#define DP_BRANCH_OUI 0x500
1000#define DP_BRANCH_ID 0x503
1001#define DP_BRANCH_REVISION_START 0x509
1002#define DP_BRANCH_HW_REV 0x509
1003#define DP_BRANCH_SW_REV 0x50A
1004
1005/* Link/Sink Device Power Control */
1006#define DP_SET_POWER 0x600
1007# define DP_SET_POWER_D0 0x1
1008# define DP_SET_POWER_D3 0x2
1009# define DP_SET_POWER_MASK 0x3
1010# define DP_SET_POWER_D3_AUX_ON 0x5
1011
1012/* eDP-specific */
1013#define DP_EDP_DPCD_REV 0x700 /* eDP 1.2 */
1014# define DP_EDP_11 0x00
1015# define DP_EDP_12 0x01
1016# define DP_EDP_13 0x02
1017# define DP_EDP_14 0x03
1018# define DP_EDP_14a 0x04 /* eDP 1.4a */
1019# define DP_EDP_14b 0x05 /* eDP 1.4b */
1020# define DP_EDP_15 0x06 /* eDP 1.5 */
1021
1022#define DP_EDP_GENERAL_CAP_1 0x701
1023# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
1024# define DP_EDP_BACKLIGHT_PIN_ENABLE_CAP (1 << 1)
1025# define DP_EDP_BACKLIGHT_AUX_ENABLE_CAP (1 << 2)
1026# define DP_EDP_PANEL_SELF_TEST_PIN_ENABLE_CAP (1 << 3)
1027# define DP_EDP_PANEL_SELF_TEST_AUX_ENABLE_CAP (1 << 4)
1028# define DP_EDP_FRC_ENABLE_CAP (1 << 5)
1029# define DP_EDP_COLOR_ENGINE_CAP (1 << 6)
1030# define DP_EDP_SET_POWER_CAP (1 << 7)
1031
1032#define DP_EDP_BACKLIGHT_ADJUSTMENT_CAP 0x702
1033# define DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP (1 << 0)
1034# define DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP (1 << 1)
1035# define DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT (1 << 2)
1036# define DP_EDP_BACKLIGHT_AUX_PWM_PRODUCT_CAP (1 << 3)
1037# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_CAP (1 << 4)
1038# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5)
1039# define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6)
1040# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7)
1041
1042#define DP_EDP_GENERAL_CAP_2 0x703
1043# define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0)
1044# define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4)
1045# define DP_EDP_SMOOTH_BRIGHTNESS_CAPABLE (1 << 6) /* eDP 2.0 */
1046
1047#define DP_EDP_GENERAL_CAP_3 0x704 /* eDP 1.4 */
1048# define DP_EDP_X_REGION_CAP_MASK (0xf << 0)
1049# define DP_EDP_X_REGION_CAP_SHIFT 0
1050# define DP_EDP_Y_REGION_CAP_MASK (0xf << 4)
1051# define DP_EDP_Y_REGION_CAP_SHIFT 4
1052
1053#define DP_EDP_DISPLAY_CONTROL_REGISTER 0x720
1054# define DP_EDP_BACKLIGHT_ENABLE (1 << 0)
1055# define DP_EDP_BLACK_VIDEO_ENABLE (1 << 1)
1056# define DP_EDP_FRC_ENABLE (1 << 2)
1057# define DP_EDP_COLOR_ENGINE_ENABLE (1 << 3)
1058# define DP_EDP_VBLANK_BACKLIGHT_UPDATE_ENABLE (1 << 7)
1059
1060#define DP_EDP_BACKLIGHT_MODE_SET_REGISTER 0x721
1061# define DP_EDP_BACKLIGHT_CONTROL_MODE_MASK (3 << 0)
1062# define DP_EDP_BACKLIGHT_CONTROL_MODE_PWM (0 << 0)
1063# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET (1 << 0)
1064# define DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD (2 << 0)
1065# define DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT (3 << 0)
1066# define DP_EDP_BACKLIGHT_FREQ_PWM_PIN_PASSTHRU_ENABLE (1 << 2)
1067# define DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE (1 << 3)
1068# define DP_EDP_DYNAMIC_BACKLIGHT_ENABLE (1 << 4)
1069# define DP_EDP_REGIONAL_BACKLIGHT_ENABLE (1 << 5)
1070# define DP_EDP_UPDATE_REGION_BRIGHTNESS (1 << 6) /* eDP 1.4 */
1071# define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7)
1072
1073#define DP_EDP_BACKLIGHT_BRIGHTNESS_MSB 0x722
1074#define DP_EDP_BACKLIGHT_BRIGHTNESS_LSB 0x723
1075
1076#define DP_EDP_PWMGEN_BIT_COUNT 0x724
1077#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN 0x725
1078#define DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX 0x726
1079# define DP_EDP_PWMGEN_BIT_COUNT_MASK (0x1f << 0)
1080
1081#define DP_EDP_BACKLIGHT_CONTROL_STATUS 0x727
1082
1083#define DP_EDP_BACKLIGHT_FREQ_SET 0x728
1084# define DP_EDP_BACKLIGHT_FREQ_BASE_KHZ 27000
1085
1086#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MSB 0x72a
1087#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_MID 0x72b
1088#define DP_EDP_BACKLIGHT_FREQ_CAP_MIN_LSB 0x72c
1089
1090#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MSB 0x72d
1091#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_MID 0x72e
1092#define DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB 0x72f
1093
1094#define DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET 0x732
1095#define DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET 0x733
1096#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734
1097
1098#define DP_EDP_REGIONAL_BACKLIGHT_BASE 0x740 /* eDP 1.4 */
1099#define DP_EDP_REGIONAL_BACKLIGHT_0 0x741 /* eDP 1.4 */
1100
1101#define DP_EDP_MSO_LINK_CAPABILITIES 0x7a4 /* eDP 1.4 */
1102# define DP_EDP_MSO_NUMBER_OF_LINKS_MASK (7 << 0)
1103# define DP_EDP_MSO_NUMBER_OF_LINKS_SHIFT 0
1104# define DP_EDP_MSO_INDEPENDENT_LINK_BIT (1 << 3)
1105
1106/* Sideband MSG Buffers */
1107#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
1108#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
1109#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
1110#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */
1111
1112/* DPRX Event Status Indicator */
1113#define DP_SINK_COUNT_ESI 0x2002 /* same as 0x200 */
1114#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* same as 0x201 */
1115
1116#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
1117# define DP_RX_GTC_MSTR_REQ_STATUS_CHANGE (1 << 0)
1118# define DP_LOCK_ACQUISITION_REQUEST (1 << 1)
1119# define DP_CEC_IRQ (1 << 2)
1120
1121#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */
1122# define RX_CAP_CHANGED (1 << 0)
1123# define LINK_STATUS_CHANGED (1 << 1)
1124# define STREAM_STATUS_CHANGED (1 << 2)
1125# define HDMI_LINK_STATUS_CHANGED (1 << 3)
1126# define CONNECTED_OFF_ENTRY_REQUESTED (1 << 4)
1127# define DP_TUNNELING_IRQ (1 << 5)
1128
1129#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */
1130# define DP_PSR_LINK_CRC_ERROR (1 << 0)
1131# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
1132# define DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2) /* eDP 1.4 */
1133
1134#define DP_PSR_ESI 0x2007 /* XXX 1.2? */
1135# define DP_PSR_CAPS_CHANGE (1 << 0)
1136
1137#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */
1138# define DP_PSR_SINK_INACTIVE 0
1139# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
1140# define DP_PSR_SINK_ACTIVE_RFB 2
1141# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
1142# define DP_PSR_SINK_ACTIVE_RESYNC 4
1143# define DP_PSR_SINK_INTERNAL_ERROR 7
1144# define DP_PSR_SINK_STATE_MASK 0x07
1145
1146#define DP_SYNCHRONIZATION_LATENCY_IN_SINK 0x2009 /* edp 1.4 */
1147# define DP_MAX_RESYNC_FRAME_COUNT_MASK (0xf << 0)
1148# define DP_MAX_RESYNC_FRAME_COUNT_SHIFT 0
1149# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_MASK (0xf << 4)
1150# define DP_LAST_ACTUAL_SYNCHRONIZATION_LATENCY_SHIFT 4
1151
1152#define DP_LAST_RECEIVED_PSR_SDP 0x200a /* eDP 1.2 */
1153# define DP_PSR_STATE_BIT (1 << 0) /* eDP 1.2 */
1154# define DP_UPDATE_RFB_BIT (1 << 1) /* eDP 1.2 */
1155# define DP_CRC_VALID_BIT (1 << 2) /* eDP 1.2 */
1156# define DP_SU_VALID (1 << 3) /* eDP 1.4 */
1157# define DP_FIRST_SCAN_LINE_SU_REGION (1 << 4) /* eDP 1.4 */
1158# define DP_LAST_SCAN_LINE_SU_REGION (1 << 5) /* eDP 1.4 */
1159# define DP_Y_COORDINATE_VALID (1 << 6) /* eDP 1.4a */
1160
1161#define DP_RECEIVER_ALPM_STATUS 0x200b /* eDP 1.4 */
1162# define DP_ALPM_LOCK_TIMEOUT_ERROR (1 << 0)
1163
1164#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */
1165#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */
1166#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */
1167#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */
1168
1169#define DP_PANEL_REPLAY_ERROR_STATUS 0x2020 /* DP 2.1*/
1170# define DP_PANEL_REPLAY_LINK_CRC_ERROR (1 << 0)
1171# define DP_PANEL_REPLAY_RFB_STORAGE_ERROR (1 << 1)
1172# define DP_PANEL_REPLAY_VSC_SDP_UNCORRECTABLE_ERROR (1 << 2)
1173
1174#define DP_SINK_DEVICE_PR_AND_FRAME_LOCK_STATUS 0x2022 /* DP 2.1 */
1175# define DP_SINK_DEVICE_PANEL_REPLAY_STATUS_MASK (7 << 0)
1176# define DP_SINK_FRAME_LOCKED_SHIFT 3
1177# define DP_SINK_FRAME_LOCKED_MASK (3 << 3)
1178# define DP_SINK_FRAME_LOCKED_STATUS_VALID_SHIFT 5
1179# define DP_SINK_FRAME_LOCKED_STATUS_VALID_MASK (1 << 5)
1180
1181/* Extended Receiver Capability: See DP_DPCD_REV for definitions */
1182#define DP_DP13_DPCD_REV 0x2200
1183
1184#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */
1185# define DP_GTC_CAP (1 << 0) /* DP 1.3 */
1186# define DP_SST_SPLIT_SDP_CAP (1 << 1) /* DP 1.4 */
1187# define DP_AV_SYNC_CAP (1 << 2) /* DP 1.3 */
1188# define DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED (1 << 3) /* DP 1.3 */
1189# define DP_VSC_EXT_VESA_SDP_SUPPORTED (1 << 4) /* DP 1.4 */
1190# define DP_VSC_EXT_VESA_SDP_CHAINING_SUPPORTED (1 << 5) /* DP 1.4 */
1191# define DP_VSC_EXT_CEA_SDP_SUPPORTED (1 << 6) /* DP 1.4 */
1192# define DP_VSC_EXT_CEA_SDP_CHAINING_SUPPORTED (1 << 7) /* DP 1.4 */
1193
1194#define DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST 0x2211 /* 1.4a */
1195# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_MASK 0xff
1196# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS 0x00
1197# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS 0x01
1198# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS 0x02
1199# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS 0x03
1200# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS 0x04
1201# define DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS 0x05
1202
1203#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */
1204# define DP_ADAPTIVE_SYNC_SDP_SUPPORTED (1 << 0)
1205# define DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE GENMASK(1, 0)
1206# define DP_ADAPTIVE_SYNC_SDP_LENGTH GENMASK(5, 0)
1207# define DP_AS_SDP_FIRST_HALF_LINE_OR_3840_PIXEL_CYCLE_WINDOW_NOT_SUPPORTED (1 << 1)
1208# define DP_VSC_EXT_SDP_FRAMEWORK_VERSION_1_SUPPORTED (1 << 4)
1209
1210#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */
1211# define DP_UHBR10 (1 << 0)
1212# define DP_UHBR20 (1 << 1)
1213# define DP_UHBR13_5 (1 << 2)
1214
1215#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
1216# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
1217# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
1218# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US 0x00
1219# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
1220# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS 0x02
1221# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS 0x03
1222# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS 0x04
1223# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS 0x05
1224# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS 0x06
1225
1226#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
1227#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
1228
1229/* DSC Extended Capability Branch Total DSC Resources */
1230#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
1231# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
1232# define DP_DSC_DECODER_COUNT_SHIFT 5
1233#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
1234# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
1235# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
1236# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
1237
1238/* Protocol Converter Extension */
1239/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
1240#define DP_CEC_TUNNELING_CAPABILITY 0x3000
1241# define DP_CEC_TUNNELING_CAPABLE (1 << 0)
1242# define DP_CEC_SNOOPING_CAPABLE (1 << 1)
1243# define DP_CEC_MULTIPLE_LA_CAPABLE (1 << 2)
1244
1245#define DP_CEC_TUNNELING_CONTROL 0x3001
1246# define DP_CEC_TUNNELING_ENABLE (1 << 0)
1247# define DP_CEC_SNOOPING_ENABLE (1 << 1)
1248
1249#define DP_CEC_RX_MESSAGE_INFO 0x3002
1250# define DP_CEC_RX_MESSAGE_LEN_MASK (0xf << 0)
1251# define DP_CEC_RX_MESSAGE_LEN_SHIFT 0
1252# define DP_CEC_RX_MESSAGE_HPD_STATE (1 << 4)
1253# define DP_CEC_RX_MESSAGE_HPD_LOST (1 << 5)
1254# define DP_CEC_RX_MESSAGE_ACKED (1 << 6)
1255# define DP_CEC_RX_MESSAGE_ENDED (1 << 7)
1256
1257#define DP_CEC_TX_MESSAGE_INFO 0x3003
1258# define DP_CEC_TX_MESSAGE_LEN_MASK (0xf << 0)
1259# define DP_CEC_TX_MESSAGE_LEN_SHIFT 0
1260# define DP_CEC_TX_RETRY_COUNT_MASK (0x7 << 4)
1261# define DP_CEC_TX_RETRY_COUNT_SHIFT 4
1262# define DP_CEC_TX_MESSAGE_SEND (1 << 7)
1263
1264#define DP_CEC_TUNNELING_IRQ_FLAGS 0x3004
1265# define DP_CEC_RX_MESSAGE_INFO_VALID (1 << 0)
1266# define DP_CEC_RX_MESSAGE_OVERFLOW (1 << 1)
1267# define DP_CEC_TX_MESSAGE_SENT (1 << 4)
1268# define DP_CEC_TX_LINE_ERROR (1 << 5)
1269# define DP_CEC_TX_ADDRESS_NACK_ERROR (1 << 6)
1270# define DP_CEC_TX_DATA_NACK_ERROR (1 << 7)
1271
1272#define DP_CEC_LOGICAL_ADDRESS_MASK 0x300E /* 0x300F word */
1273# define DP_CEC_LOGICAL_ADDRESS_0 (1 << 0)
1274# define DP_CEC_LOGICAL_ADDRESS_1 (1 << 1)
1275# define DP_CEC_LOGICAL_ADDRESS_2 (1 << 2)
1276# define DP_CEC_LOGICAL_ADDRESS_3 (1 << 3)
1277# define DP_CEC_LOGICAL_ADDRESS_4 (1 << 4)
1278# define DP_CEC_LOGICAL_ADDRESS_5 (1 << 5)
1279# define DP_CEC_LOGICAL_ADDRESS_6 (1 << 6)
1280# define DP_CEC_LOGICAL_ADDRESS_7 (1 << 7)
1281#define DP_CEC_LOGICAL_ADDRESS_MASK_2 0x300F /* 0x300E word */
1282# define DP_CEC_LOGICAL_ADDRESS_8 (1 << 0)
1283# define DP_CEC_LOGICAL_ADDRESS_9 (1 << 1)
1284# define DP_CEC_LOGICAL_ADDRESS_10 (1 << 2)
1285# define DP_CEC_LOGICAL_ADDRESS_11 (1 << 3)
1286# define DP_CEC_LOGICAL_ADDRESS_12 (1 << 4)
1287# define DP_CEC_LOGICAL_ADDRESS_13 (1 << 5)
1288# define DP_CEC_LOGICAL_ADDRESS_14 (1 << 6)
1289# define DP_CEC_LOGICAL_ADDRESS_15 (1 << 7)
1290
1291#define DP_CEC_RX_MESSAGE_BUFFER 0x3010
1292#define DP_CEC_TX_MESSAGE_BUFFER 0x3020
1293#define DP_CEC_MESSAGE_BUFFER_LENGTH 0x10
1294
1295/* PCON CONFIGURE-1 FRL FOR HDMI SINK */
1296#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A
1297# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0)
1298# define DP_PCON_ENABLE_MAX_BW_0GBPS 0
1299# define DP_PCON_ENABLE_MAX_BW_9GBPS 1
1300# define DP_PCON_ENABLE_MAX_BW_18GBPS 2
1301# define DP_PCON_ENABLE_MAX_BW_24GBPS 3
1302# define DP_PCON_ENABLE_MAX_BW_32GBPS 4
1303# define DP_PCON_ENABLE_MAX_BW_40GBPS 5
1304# define DP_PCON_ENABLE_MAX_BW_48GBPS 6
1305# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3)
1306# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4)
1307# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4)
1308# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5)
1309# define DP_PCON_ENABLE_HPD_READY (1 << 6)
1310# define DP_PCON_ENABLE_HDMI_LINK (1 << 7)
1311
1312/* PCON CONFIGURE-2 FRL FOR HDMI SINK */
1313#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B
1314# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0)
1315# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0)
1316# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1)
1317# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2)
1318# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3)
1319# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4)
1320# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5)
1321# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6)
1322# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6)
1323
1324/* PCON HDMI LINK STATUS */
1325#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B
1326# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0)
1327# define DP_PCON_FRL_READY (1 << 1)
1328
1329/* PCON HDMI POST FRL STATUS */
1330#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036
1331# define DP_PCON_HDMI_LINK_MODE (1 << 0)
1332# define DP_PCON_HDMI_MODE_TMDS 0
1333# define DP_PCON_HDMI_MODE_FRL 1
1334# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1)
1335# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1)
1336# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2)
1337# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3)
1338# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4)
1339# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5)
1340# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6)
1341
1342#define DP_PROTOCOL_CONVERTER_CONTROL_0 0x3050 /* DP 1.3 */
1343# define DP_HDMI_DVI_OUTPUT_CONFIG (1 << 0) /* DP 1.3 */
1344#define DP_PROTOCOL_CONVERTER_CONTROL_1 0x3051 /* DP 1.3 */
1345# define DP_CONVERSION_TO_YCBCR420_ENABLE (1 << 0) /* DP 1.3 */
1346# define DP_HDMI_EDID_PROCESSING_DISABLE (1 << 1) /* DP 1.4 */
1347# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE (1 << 2) /* DP 1.4 */
1348# define DP_HDMI_FORCE_SCRAMBLING (1 << 3) /* DP 1.4 */
1349#define DP_PROTOCOL_CONVERTER_CONTROL_2 0x3052 /* DP 1.3 */
1350# define DP_CONVERSION_TO_YCBCR422_ENABLE (1 << 0) /* DP 1.3 */
1351# define DP_PCON_ENABLE_DSC_ENCODER (1 << 1)
1352# define DP_PCON_ENCODER_PPS_OVERRIDE_MASK (0x3 << 2)
1353# define DP_PCON_ENC_PPS_OVERRIDE_DISABLED 0
1354# define DP_PCON_ENC_PPS_OVERRIDE_EN_PARAMS 1
1355# define DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER 2
1356# define DP_CONVERSION_RGB_YCBCR_MASK (7 << 4)
1357# define DP_CONVERSION_BT601_RGB_YCBCR_ENABLE (1 << 4)
1358# define DP_CONVERSION_BT709_RGB_YCBCR_ENABLE (1 << 5)
1359# define DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE (1 << 6)
1360
1361/* PCON Downstream HDMI ERROR Status per Lane */
1362#define DP_PCON_HDMI_ERROR_STATUS_LN0 0x3037
1363#define DP_PCON_HDMI_ERROR_STATUS_LN1 0x3038
1364#define DP_PCON_HDMI_ERROR_STATUS_LN2 0x3039
1365#define DP_PCON_HDMI_ERROR_STATUS_LN3 0x303A
1366# define DP_PCON_HDMI_ERROR_COUNT_MASK (0x7 << 0)
1367# define DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS (1 << 0)
1368# define DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS (1 << 1)
1369# define DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS (1 << 2)
1370
1371/* PCON HDMI CONFIG PPS Override Buffer
1372 * Valid Offsets to be added to Base : 0-127
1373 */
1374#define DP_PCON_HDMI_PPS_OVERRIDE_BASE 0x3100
1375
1376/* PCON HDMI CONFIG PPS Override Parameter: Slice height
1377 * Offset-0 8LSBs of the Slice height.
1378 * Offset-1 8MSBs of the Slice height.
1379 */
1380#define DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT 0x3180
1381
1382/* PCON HDMI CONFIG PPS Override Parameter: Slice width
1383 * Offset-0 8LSBs of the Slice width.
1384 * Offset-1 8MSBs of the Slice width.
1385 */
1386#define DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH 0x3182
1387
1388/* PCON HDMI CONFIG PPS Override Parameter: bits_per_pixel
1389 * Offset-0 8LSBs of the bits_per_pixel.
1390 * Offset-1 2MSBs of the bits_per_pixel.
1391 */
1392#define DP_PCON_HDMI_PPS_OVRD_BPP 0x3184
1393
1394/* HDCP 1.3 and HDCP 2.2 */
1395#define DP_AUX_HDCP_BKSV 0x68000
1396#define DP_AUX_HDCP_RI_PRIME 0x68005
1397#define DP_AUX_HDCP_AKSV 0x68007
1398#define DP_AUX_HDCP_AN 0x6800C
1399#define DP_AUX_HDCP_V_PRIME(h) (0x68014 + h * 4)
1400#define DP_AUX_HDCP_BCAPS 0x68028
1401# define DP_BCAPS_REPEATER_PRESENT BIT(1)
1402# define DP_BCAPS_HDCP_CAPABLE BIT(0)
1403#define DP_AUX_HDCP_BSTATUS 0x68029
1404# define DP_BSTATUS_REAUTH_REQ BIT(3)
1405# define DP_BSTATUS_LINK_FAILURE BIT(2)
1406# define DP_BSTATUS_R0_PRIME_READY BIT(1)
1407# define DP_BSTATUS_READY BIT(0)
1408#define DP_AUX_HDCP_BINFO 0x6802A
1409#define DP_AUX_HDCP_KSV_FIFO 0x6802C
1410#define DP_AUX_HDCP_AINFO 0x6803B
1411
1412/* DP HDCP2.2 parameter offsets in DPCD address space */
1413#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000
1414#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008
1415#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B
1416#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215
1417#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D
1418#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220
1419#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0
1420#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0
1421#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0
1422#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0
1423#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0
1424#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8
1425#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318
1426#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328
1427#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330
1428#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332
1429#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335
1430#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345
1431#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0
1432#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0
1433#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3
1434#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5
1435#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473
1436#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493
1437#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494
1438#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518
1439
1440/* DP-tunneling */
1441#define DP_TUNNELING_OUI 0xe0000
1442#define DP_TUNNELING_OUI_BYTES 3
1443
1444#define DP_TUNNELING_DEV_ID 0xe0003
1445#define DP_TUNNELING_DEV_ID_BYTES 6
1446
1447#define DP_TUNNELING_HW_REV 0xe0009
1448#define DP_TUNNELING_HW_REV_MAJOR_SHIFT 4
1449#define DP_TUNNELING_HW_REV_MAJOR_MASK (0xf << DP_TUNNELING_HW_REV_MAJOR_SHIFT)
1450#define DP_TUNNELING_HW_REV_MINOR_SHIFT 0
1451#define DP_TUNNELING_HW_REV_MINOR_MASK (0xf << DP_TUNNELING_HW_REV_MINOR_SHIFT)
1452
1453#define DP_TUNNELING_SW_REV_MAJOR 0xe000a
1454#define DP_TUNNELING_SW_REV_MINOR 0xe000b
1455
1456#define DP_TUNNELING_CAPABILITIES 0xe000d
1457#define DP_IN_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
1458#define DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT (1 << 6)
1459#define DP_TUNNELING_SUPPORT (1 << 0)
1460
1461#define DP_IN_ADAPTER_INFO 0xe000e
1462#define DP_IN_ADAPTER_NUMBER_BITS 7
1463#define DP_IN_ADAPTER_NUMBER_MASK ((1 << DP_IN_ADAPTER_NUMBER_BITS) - 1)
1464
1465#define DP_USB4_DRIVER_ID 0xe000f
1466#define DP_USB4_DRIVER_ID_BITS 4
1467#define DP_USB4_DRIVER_ID_MASK ((1 << DP_USB4_DRIVER_ID_BITS) - 1)
1468
1469#define DP_USB4_DRIVER_BW_CAPABILITY 0xe0020
1470#define DP_USB4_DRIVER_BW_ALLOCATION_MODE_SUPPORT (1 << 7)
1471
1472#define DP_IN_ADAPTER_TUNNEL_INFORMATION 0xe0021
1473#define DP_GROUP_ID_BITS 3
1474#define DP_GROUP_ID_MASK ((1 << DP_GROUP_ID_BITS) - 1)
1475
1476#define DP_BW_GRANULARITY 0xe0022
1477#define DP_BW_GRANULARITY_MASK 0x3
1478
1479#define DP_ESTIMATED_BW 0xe0023
1480#define DP_ALLOCATED_BW 0xe0024
1481
1482#define DP_TUNNELING_STATUS 0xe0025
1483#define DP_BW_ALLOCATION_CAPABILITY_CHANGED (1 << 3)
1484#define DP_ESTIMATED_BW_CHANGED (1 << 2)
1485#define DP_BW_REQUEST_SUCCEEDED (1 << 1)
1486#define DP_BW_REQUEST_FAILED (1 << 0)
1487
1488#define DP_TUNNELING_MAX_LINK_RATE 0xe0028
1489
1490#define DP_TUNNELING_MAX_LANE_COUNT 0xe0029
1491#define DP_TUNNELING_MAX_LANE_COUNT_MASK 0x1f
1492
1493#define DP_DPTX_BW_ALLOCATION_MODE_CONTROL 0xe0030
1494#define DP_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE (1 << 7)
1495#define DP_UNMASK_BW_ALLOCATION_IRQ (1 << 6)
1496
1497#define DP_REQUEST_BW 0xe0031
1498#define MAX_DP_REQUEST_BW 255
1499
1500/* LTTPR: Link Training (LT)-tunable PHY Repeaters */
1501#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1502#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */
1503#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */
1504#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */
1505#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
1506#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
1507#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
1508# define DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK 0x7f
1509# define DP_EXTENDED_WAKE_TIMEOUT_GRANT (1 << 7)
1510#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xf0006 /* 2.0 */
1511# define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
1512/* See DP_128B132B_SUPPORTED_LINK_RATES for values */
1513#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */
1514#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0 E11 */
1515
1516enum drm_dp_phy {
1517 DP_PHY_DPRX,
1518
1519 DP_PHY_LTTPR1,
1520 DP_PHY_LTTPR2,
1521 DP_PHY_LTTPR3,
1522 DP_PHY_LTTPR4,
1523 DP_PHY_LTTPR5,
1524 DP_PHY_LTTPR6,
1525 DP_PHY_LTTPR7,
1526 DP_PHY_LTTPR8,
1527
1528 DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
1529};
1530
1531#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
1532
1533#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
1534#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
1535#define DP_LTTPR_BASE(dp_phy) \
1536 (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
1537 ((dp_phy) - DP_PHY_LTTPR1))
1538
1539#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
1540 (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
1541
1542#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
1543#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
1544 DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
1545
1546#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
1547#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
1548 DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
1549
1550#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
1551#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
1552#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
1553#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
1554#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1555 DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1556
1557#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
1558# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
1559# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
1560
1561#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0022 /* 2.0 */
1562#define DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
1563 DP_LTTPR_REG(dp_phy, DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
1564/* see DP_128B132B_TRAINING_AUX_RD_INTERVAL for values */
1565
1566#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
1567#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
1568 DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
1569
1570#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
1571
1572#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
1573#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
1574#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
1575#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035 /* 1.3 */
1576#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037 /* 1.3 */
1577#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039 /* 1.3 */
1578#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b /* 1.3 */
1579
1580#define DP_OUI_PHY_REPEATER1 0xf003d /* 1.3 */
1581#define DP_OUI_PHY_REPEATER(dp_phy) \
1582 DP_LTTPR_REG(dp_phy, DP_OUI_PHY_REPEATER1)
1583
1584#define __DP_FEC1_BASE 0xf0290 /* 1.4 */
1585#define __DP_FEC2_BASE 0xf0298 /* 1.4 */
1586#define DP_FEC_BASE(dp_phy) \
1587 (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \
1588 ((dp_phy) - DP_PHY_LTTPR1)))
1589
1590#define DP_FEC_REG(dp_phy, fec1_reg) \
1591 (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg)
1592
1593#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */
1594#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \
1595 DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1)
1596
1597#define DP_FEC_ERROR_COUNT_PHY_REPEATER1 0xf0291 /* 1.4 */
1598#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a */
1599
1600#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */
1601
1602#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */
1603
1604/* Repeater modes */
1605#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */
1606#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */
1607
1608/* DP HDCP message start offsets in DPCD address space */
1609#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET
1610#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET
1611#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1612#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1613#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET
1614#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1615 DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1616#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET
1617#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET
1618#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1619#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET
1620#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET
1621#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1622#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET
1623
1624#define HDCP_2_2_DP_RXSTATUS_LEN 1
1625#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0))
1626#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1))
1627#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2))
1628#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3))
1629#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4))
1630
1631/* DP 1.2 Sideband message defines */
1632/* peer device type - DP 1.2a Table 2-92 */
1633#define DP_PEER_DEVICE_NONE 0x0
1634#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1
1635#define DP_PEER_DEVICE_MST_BRANCHING 0x2
1636#define DP_PEER_DEVICE_SST_SINK 0x3
1637#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4
1638
1639/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1640#define DP_GET_MSG_TRANSACTION_VERSION 0x00 /* DP 1.3 */
1641#define DP_LINK_ADDRESS 0x01
1642#define DP_CONNECTION_STATUS_NOTIFY 0x02
1643#define DP_ENUM_PATH_RESOURCES 0x10
1644#define DP_ALLOCATE_PAYLOAD 0x11
1645#define DP_QUERY_PAYLOAD 0x12
1646#define DP_RESOURCE_STATUS_NOTIFY 0x13
1647#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14
1648#define DP_REMOTE_DPCD_READ 0x20
1649#define DP_REMOTE_DPCD_WRITE 0x21
1650#define DP_REMOTE_I2C_READ 0x22
1651#define DP_REMOTE_I2C_WRITE 0x23
1652#define DP_POWER_UP_PHY 0x24
1653#define DP_POWER_DOWN_PHY 0x25
1654#define DP_SINK_EVENT_NOTIFY 0x30
1655#define DP_QUERY_STREAM_ENC_STATUS 0x38
1656#define DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST 0
1657#define DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE 1
1658#define DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE 2
1659
1660/* DP 1.2 MST sideband reply types */
1661#define DP_SIDEBAND_REPLY_ACK 0x00
1662#define DP_SIDEBAND_REPLY_NAK 0x01
1663
1664/* DP 1.2 MST sideband nak reasons - table 2.84 */
1665#define DP_NAK_WRITE_FAILURE 0x01
1666#define DP_NAK_INVALID_READ 0x02
1667#define DP_NAK_CRC_FAILURE 0x03
1668#define DP_NAK_BAD_PARAM 0x04
1669#define DP_NAK_DEFER 0x05
1670#define DP_NAK_LINK_FAILURE 0x06
1671#define DP_NAK_NO_RESOURCES 0x07
1672#define DP_NAK_DPCD_FAIL 0x08
1673#define DP_NAK_I2C_NAK 0x09
1674#define DP_NAK_ALLOCATE_FAIL 0x0a
1675
1676#define MODE_I2C_START 1
1677#define MODE_I2C_WRITE 2
1678#define MODE_I2C_READ 4
1679#define MODE_I2C_STOP 8
1680
1681/* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
1682#define DP_MST_PHYSICAL_PORT_0 0
1683#define DP_MST_LOGICAL_PORT_0 8
1684
1685#define DP_LINK_CONSTANT_N_VALUE 0x8000
1686#define DP_LINK_STATUS_SIZE 6
1687
1688#define DP_BRANCH_OUI_HEADER_SIZE 0xc
1689#define DP_RECEIVER_CAP_SIZE 0xf
1690#define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60 through 0x6F */
1691#define DP_DSC_BRANCH_CAP_SIZE 3
1692#define EDP_PSR_RECEIVER_CAP_SIZE 2
1693#define EDP_DISPLAY_CTL_CAP_SIZE 5
1694#define DP_LTTPR_COMMON_CAP_SIZE 8
1695#define DP_LTTPR_PHY_CAP_SIZE 3
1696
1697#define DP_SDP_AUDIO_TIMESTAMP 0x01
1698#define DP_SDP_AUDIO_STREAM 0x02
1699#define DP_SDP_EXTENSION 0x04 /* DP 1.1 */
1700#define DP_SDP_AUDIO_COPYMANAGEMENT 0x05 /* DP 1.2 */
1701#define DP_SDP_ISRC 0x06 /* DP 1.2 */
1702#define DP_SDP_VSC 0x07 /* DP 1.2 */
1703#define DP_SDP_ADAPTIVE_SYNC 0x22 /* DP 1.4 */
1704#define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
1705#define DP_SDP_PPS 0x10 /* DP 1.4 */
1706#define DP_SDP_VSC_EXT_VESA 0x20 /* DP 1.4 */
1707#define DP_SDP_VSC_EXT_CEA 0x21 /* DP 1.4 */
1708
1709/* 0x80+ CEA-861 infoframe types */
1710
1711#define DP_SDP_AUDIO_INFOFRAME_HB2 0x1b
1712
1713/**
1714 * struct dp_sdp_header - DP secondary data packet header
1715 * @HB0: Secondary Data Packet ID
1716 * @HB1: Secondary Data Packet Type
1717 * @HB2: Secondary Data Packet Specific header, Byte 0
1718 * @HB3: Secondary Data packet Specific header, Byte 1
1719 */
1720struct dp_sdp_header {
1721 u8 HB0;
1722 u8 HB1;
1723 u8 HB2;
1724 u8 HB3;
1725} __packed;
1726
1727#define EDP_SDP_HEADER_REVISION_MASK 0x1F
1728#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F
1729#define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
1730
1731/**
1732 * struct dp_sdp - DP secondary data packet
1733 * @sdp_header: DP secondary data packet header
1734 * @db: DP secondaray data packet data blocks
1735 * VSC SDP Payload for PSR
1736 * db[0]: Stereo Interface
1737 * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1738 * db[2]: CRC value bits 7:0 of the R or Cr component
1739 * db[3]: CRC value bits 15:8 of the R or Cr component
1740 * db[4]: CRC value bits 7:0 of the G or Y component
1741 * db[5]: CRC value bits 15:8 of the G or Y component
1742 * db[6]: CRC value bits 7:0 of the B or Cb component
1743 * db[7]: CRC value bits 15:8 of the B or Cb component
1744 * db[8] - db[31]: Reserved
1745 * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1746 * db[0] - db[15]: Reserved
1747 * db[16]: Pixel Encoding and Colorimetry Formats
1748 * db[17]: Dynamic Range and Component Bit Depth
1749 * db[18]: Content Type
1750 * db[19] - db[31]: Reserved
1751 */
1752struct dp_sdp {
1753 struct dp_sdp_header sdp_header;
1754 u8 db[32];
1755} __packed;
1756
1757#define EDP_VSC_PSR_STATE_ACTIVE (1<<0)
1758#define EDP_VSC_PSR_UPDATE_RFB (1<<1)
1759#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2)
1760
1761/**
1762 * enum dp_pixelformat - drm DP Pixel encoding formats
1763 *
1764 * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1765 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1766 * DB18]
1767 *
1768 * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1769 * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1770 * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1771 * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1772 * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1773 * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1774 * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1775 */
1776enum dp_pixelformat {
1777 DP_PIXELFORMAT_RGB = 0,
1778 DP_PIXELFORMAT_YUV444 = 0x1,
1779 DP_PIXELFORMAT_YUV422 = 0x2,
1780 DP_PIXELFORMAT_YUV420 = 0x3,
1781 DP_PIXELFORMAT_Y_ONLY = 0x4,
1782 DP_PIXELFORMAT_RAW = 0x5,
1783 DP_PIXELFORMAT_RESERVED = 0x6,
1784};
1785
1786/**
1787 * enum dp_colorimetry - drm DP Colorimetry formats
1788 *
1789 * This enum is used to indicate DP VSC SDP Colorimetry formats.
1790 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1791 * DB18] and a name of enum member follows enum drm_colorimetry definition.
1792 *
1793 * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1794 * ITU-R BT.601 colorimetry format
1795 * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1796 * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1797 * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1798 * (scRGB (IEC 61966-2-2)) colorimetry format
1799 * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1800 * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1801 * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1802 * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1803 * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1804 * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1805 * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1806 * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1807 * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1808 * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1809 */
1810enum dp_colorimetry {
1811 DP_COLORIMETRY_DEFAULT = 0,
1812 DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1813 DP_COLORIMETRY_BT709_YCC = 0x1,
1814 DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1815 DP_COLORIMETRY_XVYCC_601 = 0x2,
1816 DP_COLORIMETRY_OPRGB = 0x3,
1817 DP_COLORIMETRY_XVYCC_709 = 0x3,
1818 DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1819 DP_COLORIMETRY_SYCC_601 = 0x4,
1820 DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1821 DP_COLORIMETRY_OPYCC_601 = 0x5,
1822 DP_COLORIMETRY_BT2020_RGB = 0x6,
1823 DP_COLORIMETRY_BT2020_CYCC = 0x6,
1824 DP_COLORIMETRY_BT2020_YCC = 0x7,
1825};
1826
1827/**
1828 * enum dp_dynamic_range - drm DP Dynamic Range
1829 *
1830 * This enum is used to indicate DP VSC SDP Dynamic Range.
1831 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1832 * DB18]
1833 *
1834 * @DP_DYNAMIC_RANGE_VESA: VESA range
1835 * @DP_DYNAMIC_RANGE_CTA: CTA range
1836 */
1837enum dp_dynamic_range {
1838 DP_DYNAMIC_RANGE_VESA = 0,
1839 DP_DYNAMIC_RANGE_CTA = 1,
1840};
1841
1842/**
1843 * enum dp_content_type - drm DP Content Type
1844 *
1845 * This enum is used to indicate DP VSC SDP Content Types.
1846 * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1847 * DB18]
1848 * CTA-861-G defines content types and expected processing by a sink device
1849 *
1850 * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1851 * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1852 * @DP_CONTENT_TYPE_PHOTO: Photo type
1853 * @DP_CONTENT_TYPE_VIDEO: Video type
1854 * @DP_CONTENT_TYPE_GAME: Game type
1855 */
1856enum dp_content_type {
1857 DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1858 DP_CONTENT_TYPE_GRAPHICS = 0x01,
1859 DP_CONTENT_TYPE_PHOTO = 0x02,
1860 DP_CONTENT_TYPE_VIDEO = 0x03,
1861 DP_CONTENT_TYPE_GAME = 0x04,
1862};
1863
1864enum operation_mode {
1865 DP_AS_SDP_AVT_DYNAMIC_VTOTAL = 0x00,
1866 DP_AS_SDP_AVT_FIXED_VTOTAL = 0x01,
1867 DP_AS_SDP_FAVT_TRR_NOT_REACHED = 0x02,
1868 DP_AS_SDP_FAVT_TRR_REACHED = 0x03
1869};
1870
1871#endif /* _DRM_DP_H_ */