tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * PIC32 watchdog driver
4 *
5 * Joshua Henderson <joshua.henderson@microchip.com>
6 * Copyright (c) 2016, Microchip Technology Inc.
7 */
8#include <linux/clk.h>
9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/of.h>
15#include <linux/platform_data/pic32.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/watchdog.h>
19
20/* Watchdog Timer Registers */
21#define WDTCON_REG 0x00
22
23/* Watchdog Timer Control Register fields */
24#define WDTCON_WIN_EN BIT(0)
25#define WDTCON_RMCS_MASK 0x0003
26#define WDTCON_RMCS_SHIFT 0x0006
27#define WDTCON_RMPS_MASK 0x001F
28#define WDTCON_RMPS_SHIFT 0x0008
29#define WDTCON_ON BIT(15)
30#define WDTCON_CLR_KEY 0x5743
31
32/* Reset Control Register fields for watchdog */
33#define RESETCON_TIMEOUT_IDLE BIT(2)
34#define RESETCON_TIMEOUT_SLEEP BIT(3)
35#define RESETCON_WDT_TIMEOUT BIT(4)
36
37struct pic32_wdt {
38 void __iomem *regs;
39 void __iomem *rst_base;
40 struct clk *clk;
41};
42
43static inline bool pic32_wdt_is_win_enabled(struct pic32_wdt *wdt)
44{
45 return !!(readl(wdt->regs + WDTCON_REG) & WDTCON_WIN_EN);
46}
47
48static inline u32 pic32_wdt_get_post_scaler(struct pic32_wdt *wdt)
49{
50 u32 v = readl(wdt->regs + WDTCON_REG);
51
52 return (v >> WDTCON_RMPS_SHIFT) & WDTCON_RMPS_MASK;
53}
54
55static inline u32 pic32_wdt_get_clk_id(struct pic32_wdt *wdt)
56{
57 u32 v = readl(wdt->regs + WDTCON_REG);
58
59 return (v >> WDTCON_RMCS_SHIFT) & WDTCON_RMCS_MASK;
60}
61
62static int pic32_wdt_bootstatus(struct pic32_wdt *wdt)
63{
64 u32 v = readl(wdt->rst_base);
65
66 writel(RESETCON_WDT_TIMEOUT, PIC32_CLR(wdt->rst_base));
67
68 return v & RESETCON_WDT_TIMEOUT;
69}
70
71static u32 pic32_wdt_get_timeout_secs(struct pic32_wdt *wdt, struct device *dev)
72{
73 unsigned long rate;
74 u32 period, ps, terminal;
75
76 rate = clk_get_rate(wdt->clk);
77
78 dev_dbg(dev, "wdt: clk_id %d, clk_rate %lu (prescale)\n",
79 pic32_wdt_get_clk_id(wdt), rate);
80
81 /* default, prescaler of 32 (i.e. div-by-32) is implicit. */
82 rate >>= 5;
83 if (!rate)
84 return 0;
85
86 /* calculate terminal count from postscaler. */
87 ps = pic32_wdt_get_post_scaler(wdt);
88 terminal = BIT(ps);
89
90 /* find time taken (in secs) to reach terminal count */
91 period = terminal / rate;
92 dev_dbg(dev,
93 "wdt: clk_rate %lu (postscale) / terminal %d, timeout %dsec\n",
94 rate, terminal, period);
95
96 return period;
97}
98
99static void pic32_wdt_keepalive(struct pic32_wdt *wdt)
100{
101 /* write key through single half-word */
102 writew(WDTCON_CLR_KEY, wdt->regs + WDTCON_REG + 2);
103}
104
105static int pic32_wdt_start(struct watchdog_device *wdd)
106{
107 struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
108
109 writel(WDTCON_ON, PIC32_SET(wdt->regs + WDTCON_REG));
110 pic32_wdt_keepalive(wdt);
111
112 return 0;
113}
114
115static int pic32_wdt_stop(struct watchdog_device *wdd)
116{
117 struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
118
119 writel(WDTCON_ON, PIC32_CLR(wdt->regs + WDTCON_REG));
120
121 /*
122 * Cannot touch registers in the CPU cycle following clearing the
123 * ON bit.
124 */
125 nop();
126
127 return 0;
128}
129
130static int pic32_wdt_ping(struct watchdog_device *wdd)
131{
132 struct pic32_wdt *wdt = watchdog_get_drvdata(wdd);
133
134 pic32_wdt_keepalive(wdt);
135
136 return 0;
137}
138
139static const struct watchdog_ops pic32_wdt_fops = {
140 .owner = THIS_MODULE,
141 .start = pic32_wdt_start,
142 .stop = pic32_wdt_stop,
143 .ping = pic32_wdt_ping,
144};
145
146static const struct watchdog_info pic32_wdt_ident = {
147 .options = WDIOF_KEEPALIVEPING |
148 WDIOF_MAGICCLOSE | WDIOF_CARDRESET,
149 .identity = "PIC32 Watchdog",
150};
151
152static struct watchdog_device pic32_wdd = {
153 .info = &pic32_wdt_ident,
154 .ops = &pic32_wdt_fops,
155};
156
157static const struct of_device_id pic32_wdt_dt_ids[] = {
158 { .compatible = "microchip,pic32mzda-wdt", },
159 { /* sentinel */ }
160};
161MODULE_DEVICE_TABLE(of, pic32_wdt_dt_ids);
162
163static int pic32_wdt_drv_probe(struct platform_device *pdev)
164{
165 struct device *dev = &pdev->dev;
166 int ret;
167 struct watchdog_device *wdd = &pic32_wdd;
168 struct pic32_wdt *wdt;
169
170 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
171 if (!wdt)
172 return -ENOMEM;
173
174 wdt->regs = devm_platform_ioremap_resource(pdev, 0);
175 if (IS_ERR(wdt->regs))
176 return PTR_ERR(wdt->regs);
177
178 wdt->rst_base = devm_ioremap(dev, PIC32_BASE_RESET, 0x10);
179 if (!wdt->rst_base)
180 return -ENOMEM;
181
182 wdt->clk = devm_clk_get_enabled(dev, NULL);
183 if (IS_ERR(wdt->clk)) {
184 dev_err(dev, "clk not found\n");
185 return PTR_ERR(wdt->clk);
186 }
187
188 if (pic32_wdt_is_win_enabled(wdt)) {
189 dev_err(dev, "windowed-clear mode is not supported.\n");
190 return -ENODEV;
191 }
192
193 wdd->timeout = pic32_wdt_get_timeout_secs(wdt, dev);
194 if (!wdd->timeout) {
195 dev_err(dev, "failed to read watchdog register timeout\n");
196 return -EINVAL;
197 }
198
199 dev_info(dev, "timeout %d\n", wdd->timeout);
200
201 wdd->bootstatus = pic32_wdt_bootstatus(wdt) ? WDIOF_CARDRESET : 0;
202
203 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
204 watchdog_set_drvdata(wdd, wdt);
205
206 ret = devm_watchdog_register_device(dev, wdd);
207 if (ret)
208 return ret;
209
210 platform_set_drvdata(pdev, wdd);
211
212 return 0;
213}
214
215static struct platform_driver pic32_wdt_driver = {
216 .probe = pic32_wdt_drv_probe,
217 .driver = {
218 .name = "pic32-wdt",
219 .of_match_table = of_match_ptr(pic32_wdt_dt_ids),
220 }
221};
222
223module_platform_driver(pic32_wdt_driver);
224
225MODULE_AUTHOR("Joshua Henderson <joshua.henderson@microchip.com>");
226MODULE_DESCRIPTION("Microchip PIC32 Watchdog Timer");
227MODULE_LICENSE("GPL");