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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Axiado SPI controller driver (Host mode only)
4 *
5 * Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).
6 */
7
8#ifndef SPI_AXIADO_H
9#define SPI_AXIADO_H
10
11/* Name of this driver */
12#define AX_SPI_NAME "axiado-db-spi"
13
14/* Axiado - SPI Digital Blocks IP design registers */
15#define AX_SPI_TX_FAETR 0x18 // TX-FAETR
16#define ALMOST_EMPTY_TRESHOLD 0x00 // Programmed threshold value
17#define AX_SPI_RX_FAFTR 0x28 // RX-FAETR
18#define ALMOST_FULL_TRESHOLD 0x0c // Programmed threshold value
19#define FIFO_DEPTH 256 // 256 bytes
20
21#define AX_SPI_CR1 0x00 // CR1
22#define AX_SPI_CR1_CLR 0x00 // CR1 - Clear
23#define AX_SPI_CR1_SCR 0x01 // CR1 - controller reset
24#define AX_SPI_CR1_SCE 0x02 // CR1 - Controller Enable/Disable
25#define AX_SPI_CR1_CPHA 0x08 // CR1 - CPH
26#define AX_SPI_CR1_CPOL 0x10 // CR1 - CPO
27
28#define AX_SPI_CR2 0x04 // CR2
29#define AX_SPI_CR2_SWD 0x04 // CR2 - Write Enabel/Disable
30#define AX_SPI_CR2_SRD 0x08 // CR2 - Read Enable/Disable
31#define AX_SPI_CR2_SRI 0x10 // CR2 - Read First Byte Ignore
32#define AX_SPI_CR2_HTE 0x40 // CR2 - Host Transmit Enable
33#define AX_SPI_CR3 0x08 // CR3
34#define AX_SPI_CR3_SDL 0x00 // CR3 - Data lines
35#define AX_SPI_CR3_QUAD 0x02 // CR3 - Data lines
36
37/* As per Digital Blocks datasheet clock frequency range
38 * Min - 244KHz
39 * Max - 62.5MHz
40 * SCK Clock Divider Register Values
41 */
42#define AX_SPI_RX_FBCAR 0x24 // RX_FBCAR
43#define AX_SPI_TX_FBCAR 0x14 // TX_FBCAR
44#define AX_SPI_SCDR 0x2c // SCDR
45#define AX_SPI_SCD_MIN 0x1fe // Valid SCD (SCK Clock Divider Register)
46#define AX_SPI_SCD_DEFAULT 0x06 // Default SCD (SCK Clock Divider Register)
47#define AX_SPI_SCD_MAX 0x00 // Valid SCD (SCK Clock Divider Register)
48#define AX_SPI_SCDR_SCS 0x0200 // SCDR - AMBA Bus Clock source
49
50#define AX_SPI_IMR 0x34 // IMR
51#define AX_SPI_IMR_CLR 0x00 // IMR - Clear
52#define AX_SPI_IMR_TFOM 0x02 // IMR - TFO
53#define AX_SPI_IMR_MTCM 0x40 // IMR - MTC
54#define AX_SPI_IMR_TFEM 0x10 // IMR - TFE
55#define AX_SPI_IMR_RFFM 0x20 // IMR - RFFM
56
57#define AX_SPI_ISR 0x30 // ISR
58#define AX_SPI_ISR_CLR 0xff // ISR - Clear
59#define AX_SPI_ISR_MTC 0x40 // ISR - MTC
60#define AX_SPI_ISR_TFE 0x10 // ISR - TFE
61#define AX_SPI_ISR_RFF 0x20 // ISR - RFF
62
63#define AX_SPI_IVR 0x38 // IVR
64#define AX_SPI_IVR_TFOV 0x02 // IVR - TFOV
65#define AX_SPI_IVR_MTCV 0x40 // IVR - MTCV
66#define AX_SPI_IVR_TFEV 0x10 // IVR - TFEV
67#define AX_SPI_IVR_RFFV 0x20 // IVR - RFFV
68
69#define AX_SPI_TXFIFO 0x0c // TX_FIFO
70#define AX_SPI_TX_RX_FBCR 0x10 // TX_RX_FBCR
71#define AX_SPI_RXFIFO 0x1c // RX_FIFO
72
73#define AX_SPI_TS0 0x00 // Target select 0
74#define AX_SPI_TS1 0x01 // Target select 1
75#define AX_SPI_TS2 0x10 // Target select 2
76#define AX_SPI_TS3 0x11 // Target select 3
77
78#define SPI_AUTOSUSPEND_TIMEOUT 3000
79
80/* Default number of chip select lines also used as maximum number of chip select lines */
81#define AX_SPI_DEFAULT_NUM_CS 4
82
83/* Default number of command buffer size */
84#define AX_SPI_COMMAND_BUFFER_SIZE 16 //Command + address bytes
85
86/* Target select mask
87 * 00 – TS0
88 * 01 – TS1
89 * 10 – TS2
90 * 11 – TS3
91 */
92#define AX_SPI_DEFAULT_TS_MASK 0x03
93
94#define AX_SPI_RX_FIFO_DRAIN_LIMIT 24
95#define AX_SPI_TRX_FIFO_TIMEOUT 1000
96/**
97 * struct ax_spi - This definition defines spi driver instance
98 * @regs: Virtual address of the SPI controller registers
99 * @ref_clk: Pointer to the peripheral clock
100 * @pclk: Pointer to the APB clock
101 * @speed_hz: Current SPI bus clock speed in Hz
102 * @txbuf: Pointer to the TX buffer
103 * @rxbuf: Pointer to the RX buffer
104 * @tx_bytes: Number of bytes left to transfer
105 * @rx_bytes: Number of bytes requested
106 * @tx_fifo_depth: Depth of the TX FIFO
107 * @current_rx_fifo_word: Buffers the 32-bit word read from RXFIFO
108 * @bytes_left_in_current_rx_word: Bytes to be extracted from current 32-bit word
109 * @current_rx_fifo_word_for_irq: Buffers the 32-bit word read from RXFIFO for IRQ
110 * @bytes_left_in_current_rx_word_for_irq: IRQ bytes to be extracted from current 32-bit word
111 * @rx_discard: Number of bytes to discard
112 * @rx_copy_remaining: Number of bytes to copy
113 */
114struct ax_spi {
115 void __iomem *regs;
116 struct clk *ref_clk;
117 struct clk *pclk;
118 unsigned int clk_rate;
119 u32 speed_hz;
120 const u8 *tx_buf;
121 u8 *rx_buf;
122 int tx_bytes;
123 int rx_bytes;
124 unsigned int tx_fifo_depth;
125 u32 current_rx_fifo_word;
126 int bytes_left_in_current_rx_word;
127 u32 current_rx_fifo_word_for_irq;
128 int bytes_left_in_current_rx_word_for_irq;
129 int rx_discard;
130 int rx_copy_remaining;
131};
132
133#endif /* SPI_AXIADO_H */