tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1# SPDX-License-Identifier: GPL-2.0-only
2if ARCH_TEGRA
3
4# 32-bit ARM SoCs
5if ARM
6
7config ARCH_TEGRA_2x_SOC
8 bool "Enable support for Tegra20 family"
9 default ARCH_TEGRA
10 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
11 select ARM_ERRATA_720789
12 select ARM_ERRATA_754327 if SMP
13 select ARM_ERRATA_764369 if SMP
14 select PINCTRL_TEGRA20
15 select PL310_ERRATA_727915 if CACHE_L2X0
16 select PL310_ERRATA_769419 if CACHE_L2X0
17 select SOC_TEGRA_FLOWCTRL
18 select SOC_TEGRA_PMC
19 select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR
20 select TEGRA_TIMER
21 help
22 Support for NVIDIA Tegra AP20 and T20 processors, based on the
23 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
24
25config ARCH_TEGRA_3x_SOC
26 bool "Enable support for Tegra30 family"
27 default ARCH_TEGRA
28 select ARM_ERRATA_754322
29 select ARM_ERRATA_764369 if SMP
30 select PINCTRL_TEGRA30
31 select PL310_ERRATA_769419 if CACHE_L2X0
32 select SOC_TEGRA_FLOWCTRL
33 select SOC_TEGRA_PMC
34 select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR
35 select TEGRA_TIMER
36 help
37 Support for NVIDIA Tegra T30 processor family, based on the
38 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
39
40config ARCH_TEGRA_114_SOC
41 bool "Enable support for Tegra114 family"
42 default ARCH_TEGRA
43 select ARM_ERRATA_798181 if SMP
44 select HAVE_ARM_ARCH_TIMER
45 select PINCTRL_TEGRA114
46 select SOC_TEGRA_FLOWCTRL
47 select SOC_TEGRA_PMC
48 select TEGRA_TIMER
49 help
50 Support for NVIDIA Tegra T114 processor family, based on the
51 ARM CortexA15MP CPU
52
53config ARCH_TEGRA_124_SOC
54 bool "Enable support for Tegra124 family"
55 default ARCH_TEGRA
56 select HAVE_ARM_ARCH_TIMER
57 select PINCTRL_TEGRA124
58 select SOC_TEGRA_FLOWCTRL
59 select SOC_TEGRA_PMC
60 select TEGRA_TIMER
61 help
62 Support for NVIDIA Tegra T124 processor family, based on the
63 ARM CortexA15MP CPU
64
65endif
66
67# 64-bit ARM SoCs
68if ARM64
69
70config ARCH_TEGRA_132_SOC
71 bool "NVIDIA Tegra132 SoC"
72 default ARCH_TEGRA
73 select PINCTRL_TEGRA124
74 select SOC_TEGRA_FLOWCTRL
75 select SOC_TEGRA_PMC
76 help
77 Enable support for NVIDIA Tegra132 SoC, based on the Denver
78 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
79 but contains an NVIDIA Denver CPU complex in place of
80 Tegra124's "4+1" Cortex-A15 CPU complex.
81
82config ARCH_TEGRA_210_SOC
83 bool "NVIDIA Tegra210 SoC"
84 default ARCH_TEGRA
85 select PINCTRL_TEGRA210
86 select SOC_TEGRA_FLOWCTRL
87 select SOC_TEGRA_PMC
88 select TEGRA_TIMER
89 help
90 Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
91 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
92 cores in a switched configuration. It features a GPU of the Maxwell
93 architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
94 and providing 256 CUDA cores. It supports hardware-accelerated en-
95 and decoding of various video standards including H.265, H.264 and
96 VP8 at 4K resolution and up to 60 fps.
97
98 Besides the multimedia features it also comes with a variety of I/O
99 controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
100 name only a few.
101
102config ARCH_TEGRA_186_SOC
103 bool "NVIDIA Tegra186 SoC"
104 default ARCH_TEGRA
105 depends on !CPU_BIG_ENDIAN
106 select PINCTRL_TEGRA186
107 select MAILBOX
108 select SOC_TEGRA_PMC
109 help
110 Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
111 combination of Denver and Cortex-A57 CPU cores and a GPU based on
112 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
113 used for audio processing, hardware video encoders/decoders with
114 multi-format support, ISP for image capture processing and BPMP for
115 power management.
116
117config ARCH_TEGRA_194_SOC
118 bool "NVIDIA Tegra194 SoC"
119 default ARCH_TEGRA
120 depends on !CPU_BIG_ENDIAN
121 select MAILBOX
122 select PINCTRL_TEGRA194
123 select SOC_TEGRA_PMC
124 help
125 Enable support for the NVIDIA Tegra194 SoC.
126
127config ARCH_TEGRA_234_SOC
128 bool "NVIDIA Tegra234 SoC"
129 default ARCH_TEGRA
130 depends on !CPU_BIG_ENDIAN
131 select MAILBOX
132 select PINCTRL_TEGRA234
133 select SOC_TEGRA_PMC
134 help
135 Enable support for the NVIDIA Tegra234 SoC.
136
137config ARCH_TEGRA_238_SOC
138 bool "NVIDIA Tegra238 SoC"
139 default ARCH_TEGRA
140 depends on !CPU_BIG_ENDIAN
141 select MAILBOX
142 select SOC_TEGRA_PMC
143 help
144 Enable support for the NVIDIA Tegra238 SoC.
145
146config ARCH_TEGRA_241_SOC
147 bool "NVIDIA Tegra241 SoC"
148 default ARCH_TEGRA
149 help
150 Enable support for the NVIDIA Tegra241 SoC.
151
152config ARCH_TEGRA_264_SOC
153 bool "NVIDIA Tegra264 SoC"
154 default ARCH_TEGRA
155 depends on !CPU_BIG_ENDIAN
156 select MAILBOX
157 select SOC_TEGRA_PMC
158 help
159 Enable support for the NVIDIA Tegra264 SoC.
160
161endif
162endif
163
164config SOC_TEGRA_FUSE
165 def_bool y
166 depends on ARCH_TEGRA
167 select SOC_BUS
168
169config SOC_TEGRA_FLOWCTRL
170 bool
171
172config SOC_TEGRA_PMC
173 bool
174 select GENERIC_PINCONF
175 select IRQ_DOMAIN_HIERARCHY
176 select PM_OPP
177 select PM_GENERIC_DOMAINS
178 select REGMAP
179
180config SOC_TEGRA20_VOLTAGE_COUPLER
181 bool "Voltage scaling support for Tegra20 SoCs"
182 depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
183 depends on REGULATOR
184
185config SOC_TEGRA30_VOLTAGE_COUPLER
186 bool "Voltage scaling support for Tegra30 SoCs"
187 depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
188 depends on REGULATOR
189
190config SOC_TEGRA_CBB
191 tristate "Tegra driver to handle error from CBB"
192 depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
193 default y
194 help
195 Support for handling error from Tegra Control Backbone(CBB).
196 This driver handles the errors from CBB and prints debug
197 information about the failed transactions.