tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Pinctrl data for the NVIDIA Tegra186 pinmux
4 *
5 * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17#include <linux/init.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22
23#include "pinctrl-tegra.h"
24
25/* Define unique ID for each pins */
26enum {
27 TEGRA_PIN_PEX_L0_RST_N_PA0,
28 TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
29 TEGRA_PIN_PEX_WAKE_N_PA2,
30 TEGRA_PIN_PEX_L1_RST_N_PA3,
31 TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
32 TEGRA_PIN_PEX_L2_RST_N_PA5,
33 TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
34 TEGRA_PIN_UART4_TX_PB0,
35 TEGRA_PIN_UART4_RX_PB1,
36 TEGRA_PIN_UART4_RTS_PB2,
37 TEGRA_PIN_UART4_CTS_PB3,
38 TEGRA_PIN_GPIO_WAN1_PB4,
39 TEGRA_PIN_GPIO_WAN2_PB5,
40 TEGRA_PIN_GPIO_WAN3_PB6,
41 TEGRA_PIN_GPIO_WAN4_PC0,
42 TEGRA_PIN_DAP2_SCLK_PC1,
43 TEGRA_PIN_DAP2_DOUT_PC2,
44 TEGRA_PIN_DAP2_DIN_PC3,
45 TEGRA_PIN_DAP2_FS_PC4,
46 TEGRA_PIN_GEN1_I2C_SCL_PC5,
47 TEGRA_PIN_GEN1_I2C_SDA_PC6,
48 TEGRA_PIN_SDMMC1_CLK_PD0,
49 TEGRA_PIN_SDMMC1_CMD_PD1,
50 TEGRA_PIN_SDMMC1_DAT0_PD2,
51 TEGRA_PIN_SDMMC1_DAT1_PD3,
52 TEGRA_PIN_SDMMC1_DAT2_PD4,
53 TEGRA_PIN_SDMMC1_DAT3_PD5,
54 TEGRA_PIN_EQOS_TXC_PE0,
55 TEGRA_PIN_EQOS_TD0_PE1,
56 TEGRA_PIN_EQOS_TD1_PE2,
57 TEGRA_PIN_EQOS_TD2_PE3,
58 TEGRA_PIN_EQOS_TD3_PE4,
59 TEGRA_PIN_EQOS_TX_CTL_PE5,
60 TEGRA_PIN_EQOS_RD0_PE6,
61 TEGRA_PIN_EQOS_RD1_PE7,
62 TEGRA_PIN_EQOS_RD2_PF0,
63 TEGRA_PIN_EQOS_RD3_PF1,
64 TEGRA_PIN_EQOS_RX_CTL_PF2,
65 TEGRA_PIN_EQOS_RXC_PF3,
66 TEGRA_PIN_EQOS_MDIO_PF4,
67 TEGRA_PIN_EQOS_MDC_PF5,
68 TEGRA_PIN_SDMMC3_CLK_PG0,
69 TEGRA_PIN_SDMMC3_CMD_PG1,
70 TEGRA_PIN_SDMMC3_DAT0_PG2,
71 TEGRA_PIN_SDMMC3_DAT1_PG3,
72 TEGRA_PIN_SDMMC3_DAT2_PG4,
73 TEGRA_PIN_SDMMC3_DAT3_PG5,
74 TEGRA_PIN_GPIO_WAN5_PH0,
75 TEGRA_PIN_GPIO_WAN6_PH1,
76 TEGRA_PIN_GPIO_WAN7_PH2,
77 TEGRA_PIN_GPIO_WAN8_PH3,
78 TEGRA_PIN_BCPU_PWR_REQ_PH4,
79 TEGRA_PIN_MCPU_PWR_REQ_PH5,
80 TEGRA_PIN_GPU_PWR_REQ_PH6,
81 TEGRA_PIN_GPIO_PQ0_PI0,
82 TEGRA_PIN_GPIO_PQ1_PI1,
83 TEGRA_PIN_GPIO_PQ2_PI2,
84 TEGRA_PIN_GPIO_PQ3_PI3,
85 TEGRA_PIN_GPIO_PQ4_PI4,
86 TEGRA_PIN_GPIO_PQ5_PI5,
87 TEGRA_PIN_GPIO_PQ6_PI6,
88 TEGRA_PIN_GPIO_PQ7_PI7,
89 TEGRA_PIN_DAP1_SCLK_PJ0,
90 TEGRA_PIN_DAP1_DOUT_PJ1,
91 TEGRA_PIN_DAP1_DIN_PJ2,
92 TEGRA_PIN_DAP1_FS_PJ3,
93 TEGRA_PIN_AUD_MCLK_PJ4,
94 TEGRA_PIN_GPIO_AUD0_PJ5,
95 TEGRA_PIN_GPIO_AUD1_PJ6,
96 TEGRA_PIN_GPIO_AUD2_PJ7,
97 TEGRA_PIN_GPIO_AUD3_PK0,
98 TEGRA_PIN_GEN7_I2C_SCL_PL0,
99 TEGRA_PIN_GEN7_I2C_SDA_PL1,
100 TEGRA_PIN_GEN9_I2C_SCL_PL2,
101 TEGRA_PIN_GEN9_I2C_SDA_PL3,
102 TEGRA_PIN_USB_VBUS_EN0_PL4,
103 TEGRA_PIN_USB_VBUS_EN1_PL5,
104 TEGRA_PIN_GP_PWM6_PL6,
105 TEGRA_PIN_GP_PWM7_PL7,
106 TEGRA_PIN_DMIC1_DAT_PM0,
107 TEGRA_PIN_DMIC1_CLK_PM1,
108 TEGRA_PIN_DMIC2_DAT_PM2,
109 TEGRA_PIN_DMIC2_CLK_PM3,
110 TEGRA_PIN_DMIC4_DAT_PM4,
111 TEGRA_PIN_DMIC4_CLK_PM5,
112 TEGRA_PIN_GPIO_CAM1_PN0,
113 TEGRA_PIN_GPIO_CAM2_PN1,
114 TEGRA_PIN_GPIO_CAM3_PN2,
115 TEGRA_PIN_GPIO_CAM4_PN3,
116 TEGRA_PIN_GPIO_CAM5_PN4,
117 TEGRA_PIN_GPIO_CAM6_PN5,
118 TEGRA_PIN_GPIO_CAM7_PN6,
119 TEGRA_PIN_EXTPERIPH1_CLK_PO0,
120 TEGRA_PIN_EXTPERIPH2_CLK_PO1,
121 TEGRA_PIN_CAM_I2C_SCL_PO2,
122 TEGRA_PIN_CAM_I2C_SDA_PO3,
123 TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
124 TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
125 TEGRA_PIN_HDMI_CEC_PP2,
126 TEGRA_PIN_GPIO_EDP0_PP3,
127 TEGRA_PIN_GPIO_EDP1_PP4,
128 TEGRA_PIN_GPIO_EDP2_PP5,
129 TEGRA_PIN_GPIO_EDP3_PP6,
130 TEGRA_PIN_DIRECTDC1_CLK_PQ0,
131 TEGRA_PIN_DIRECTDC1_IN_PQ1,
132 TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
133 TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
134 TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
135 TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
136 TEGRA_PIN_QSPI_SCK_PR0,
137 TEGRA_PIN_QSPI_IO0_PR1,
138 TEGRA_PIN_QSPI_IO1_PR2,
139 TEGRA_PIN_QSPI_IO2_PR3,
140 TEGRA_PIN_QSPI_IO3_PR4,
141 TEGRA_PIN_QSPI_CS_N_PR5,
142 TEGRA_PIN_UART1_TX_PT0,
143 TEGRA_PIN_UART1_RX_PT1,
144 TEGRA_PIN_UART1_RTS_PT2,
145 TEGRA_PIN_UART1_CTS_PT3,
146 TEGRA_PIN_UART2_TX_PX0,
147 TEGRA_PIN_UART2_RX_PX1,
148 TEGRA_PIN_UART2_RTS_PX2,
149 TEGRA_PIN_UART2_CTS_PX3,
150 TEGRA_PIN_UART5_TX_PX4,
151 TEGRA_PIN_UART5_RX_PX5,
152 TEGRA_PIN_UART5_RTS_PX6,
153 TEGRA_PIN_UART5_CTS_PX7,
154 TEGRA_PIN_GPIO_MDM1_PY0,
155 TEGRA_PIN_GPIO_MDM2_PY1,
156 TEGRA_PIN_GPIO_MDM3_PY2,
157 TEGRA_PIN_GPIO_MDM4_PY3,
158 TEGRA_PIN_GPIO_MDM5_PY4,
159 TEGRA_PIN_GPIO_MDM6_PY5,
160 TEGRA_PIN_GPIO_MDM7_PY6,
161 TEGRA_PIN_UFS0_REF_CLK_PBB0,
162 TEGRA_PIN_UFS0_RST_PBB1,
163 TEGRA_PIN_DAP4_SCLK_PCC0,
164 TEGRA_PIN_DAP4_DOUT_PCC1,
165 TEGRA_PIN_DAP4_DIN_PCC2,
166 TEGRA_PIN_DAP4_FS_PCC3,
167 TEGRA_PIN_DIRECTDC_COMP,
168 TEGRA_PIN_SDMMC1_COMP,
169 TEGRA_PIN_EQOS_COMP,
170 TEGRA_PIN_SDMMC3_COMP,
171 TEGRA_PIN_QSPI_COMP,
172};
173
174enum {
175 TEGRA_PIN_PWR_I2C_SCL_PS0,
176 TEGRA_PIN_PWR_I2C_SDA_PS1,
177 TEGRA_PIN_BATT_OC_PS2,
178 TEGRA_PIN_SAFE_STATE_PS3,
179 TEGRA_PIN_VCOMP_ALERT_PS4,
180 TEGRA_PIN_GPIO_DIS0_PU0,
181 TEGRA_PIN_GPIO_DIS1_PU1,
182 TEGRA_PIN_GPIO_DIS2_PU2,
183 TEGRA_PIN_GPIO_DIS3_PU3,
184 TEGRA_PIN_GPIO_DIS4_PU4,
185 TEGRA_PIN_GPIO_DIS5_PU5,
186 TEGRA_PIN_GPIO_SEN0_PV0,
187 TEGRA_PIN_GPIO_SEN1_PV1,
188 TEGRA_PIN_GPIO_SEN2_PV2,
189 TEGRA_PIN_GPIO_SEN3_PV3,
190 TEGRA_PIN_GPIO_SEN4_PV4,
191 TEGRA_PIN_GPIO_SEN5_PV5,
192 TEGRA_PIN_GPIO_SEN6_PV6,
193 TEGRA_PIN_GPIO_SEN7_PV7,
194 TEGRA_PIN_GEN8_I2C_SCL_PW0,
195 TEGRA_PIN_GEN8_I2C_SDA_PW1,
196 TEGRA_PIN_UART3_TX_PW2,
197 TEGRA_PIN_UART3_RX_PW3,
198 TEGRA_PIN_UART3_RTS_PW4,
199 TEGRA_PIN_UART3_CTS_PW5,
200 TEGRA_PIN_UART7_TX_PW6,
201 TEGRA_PIN_UART7_RX_PW7,
202 TEGRA_PIN_CAN1_DOUT_PZ0,
203 TEGRA_PIN_CAN1_DIN_PZ1,
204 TEGRA_PIN_CAN0_DOUT_PZ2,
205 TEGRA_PIN_CAN0_DIN_PZ3,
206 TEGRA_PIN_CAN_GPIO0_PAA0,
207 TEGRA_PIN_CAN_GPIO1_PAA1,
208 TEGRA_PIN_CAN_GPIO2_PAA2,
209 TEGRA_PIN_CAN_GPIO3_PAA3,
210 TEGRA_PIN_CAN_GPIO4_PAA4,
211 TEGRA_PIN_CAN_GPIO5_PAA5,
212 TEGRA_PIN_CAN_GPIO6_PAA6,
213 TEGRA_PIN_CAN_GPIO7_PAA7,
214 TEGRA_PIN_GPIO_SEN8_PEE0,
215 TEGRA_PIN_GPIO_SEN9_PEE1,
216 TEGRA_PIN_TOUCH_CLK_PEE2,
217 TEGRA_PIN_POWER_ON_PFF0,
218 TEGRA_PIN_GPIO_SW1_PFF1,
219 TEGRA_PIN_GPIO_SW2_PFF2,
220 TEGRA_PIN_GPIO_SW3_PFF3,
221 TEGRA_PIN_GPIO_SW4_PFF4,
222 TEGRA_PIN_SHUTDOWN,
223 TEGRA_PIN_PMU_INT,
224 TEGRA_PIN_SOC_PWR_REQ,
225 TEGRA_PIN_CLK_32K_IN,
226};
227
228/* Table for pin descriptor */
229static const struct pinctrl_pin_desc tegra186_pins[] = {
230 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N_PA0"),
231 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N_PA1"),
232 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N_PA2"),
233 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N_PA3"),
234 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N_PA4"),
235 PINCTRL_PIN(TEGRA_PIN_PEX_L2_RST_N_PA5, "PEX_L2_RST_N_PA5"),
236 PINCTRL_PIN(TEGRA_PIN_PEX_L2_CLKREQ_N_PA6, "PEX_L2_CLKREQ_N_PA6"),
237 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PB0, "UART4_TX_PB0"),
238 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PB1, "UART4_RX_PB1"),
239 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PB2, "UART4_RTS_PB2"),
240 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PB3, "UART4_CTS_PB3"),
241 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN1_PB4, "GPIO_WAN1_PB4"),
242 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN2_PB5, "GPIO_WAN2_PB5"),
243 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN3_PB6, "GPIO_WAN3_PB6"),
244 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN4_PC0, "GPIO_WAN4_PC0"),
245 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PC1, "DAP2_SCLK_PC1"),
246 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PC2, "DAP2_DOUT_PC2"),
247 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PC3, "DAP2_DIN_PC3"),
248 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PC4, "DAP2_FS_PC4"),
249 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC5, "GEN1_I2C_SCL_PC5"),
250 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC6, "GEN1_I2C_SDA_PC6"),
251 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PD0, "SDMMC1_CLK_PD0"),
252 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PD1, "SDMMC1_CMD_PD1"),
253 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PD2, "SDMMC1_DAT0_PD2"),
254 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PD3, "SDMMC1_DAT1_PD3"),
255 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PD4, "SDMMC1_DAT2_PD4"),
256 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PD5, "SDMMC1_DAT3_PD5"),
257 PINCTRL_PIN(TEGRA_PIN_EQOS_TXC_PE0, "EQOS_TXC_PE0"),
258 PINCTRL_PIN(TEGRA_PIN_EQOS_TD0_PE1, "EQOS_TD0_PE1"),
259 PINCTRL_PIN(TEGRA_PIN_EQOS_TD1_PE2, "EQOS_TD1_PE2"),
260 PINCTRL_PIN(TEGRA_PIN_EQOS_TD2_PE3, "EQOS_TD2_PE3"),
261 PINCTRL_PIN(TEGRA_PIN_EQOS_TD3_PE4, "EQOS_TD3_PE4"),
262 PINCTRL_PIN(TEGRA_PIN_EQOS_TX_CTL_PE5, "EQOS_TX_CTL_PE5"),
263 PINCTRL_PIN(TEGRA_PIN_EQOS_RD0_PE6, "EQOS_RD0_PE6"),
264 PINCTRL_PIN(TEGRA_PIN_EQOS_RD1_PE7, "EQOS_RD1_PE7"),
265 PINCTRL_PIN(TEGRA_PIN_EQOS_RD2_PF0, "EQOS_RD2_PF0"),
266 PINCTRL_PIN(TEGRA_PIN_EQOS_RD3_PF1, "EQOS_RD3_PF1"),
267 PINCTRL_PIN(TEGRA_PIN_EQOS_RX_CTL_PF2, "EQOS_RX_CTL_PF2"),
268 PINCTRL_PIN(TEGRA_PIN_EQOS_RXC_PF3, "EQOS_RXC_PF3"),
269 PINCTRL_PIN(TEGRA_PIN_EQOS_MDIO_PF4, "EQOS_MDIO_PF4"),
270 PINCTRL_PIN(TEGRA_PIN_EQOS_MDC_PF5, "EQOS_MDC_PF5"),
271 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PG0, "SDMMC3_CLK_PG0"),
272 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PG1, "SDMMC3_CMD_PG1"),
273 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PG2, "SDMMC3_DAT0_PG2"),
274 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PG3, "SDMMC3_DAT1_PG3"),
275 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PG4, "SDMMC3_DAT2_PG4"),
276 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PG5, "SDMMC3_DAT3_PG5"),
277 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN5_PH0, "GPIO_WAN5_PH0"),
278 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN6_PH1, "GPIO_WAN6_PH1"),
279 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN7_PH2, "GPIO_WAN7_PH2"),
280 PINCTRL_PIN(TEGRA_PIN_GPIO_WAN8_PH3, "GPIO_WAN8_PH3"),
281 PINCTRL_PIN(TEGRA_PIN_BCPU_PWR_REQ_PH4, "BCPU_PWR_REQ_PH4"),
282 PINCTRL_PIN(TEGRA_PIN_MCPU_PWR_REQ_PH5, "MCPU_PWR_REQ_PH5"),
283 PINCTRL_PIN(TEGRA_PIN_GPU_PWR_REQ_PH6, "GPU_PWR_REQ_PH6"),
284 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ0_PI0, "GPIO_PQ0_PI0"),
285 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ1_PI1, "GPIO_PQ1_PI1"),
286 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ2_PI2, "GPIO_PQ2_PI2"),
287 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ3_PI3, "GPIO_PQ3_PI3"),
288 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ4_PI4, "GPIO_PQ4_PI4"),
289 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ5_PI5, "GPIO_PQ5_PI5"),
290 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ6_PI6, "GPIO_PQ6_PI6"),
291 PINCTRL_PIN(TEGRA_PIN_GPIO_PQ7_PI7, "GPIO_PQ7_PI7"),
292 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PJ0, "DAP1_SCLK_PJ0"),
293 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PJ1, "DAP1_DOUT_PJ1"),
294 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PJ2, "DAP1_DIN_PJ2"),
295 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PJ3, "DAP1_FS_PJ3"),
296 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PJ4, "AUD_MCLK_PJ4"),
297 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD0_PJ5, "GPIO_AUD0_PJ5"),
298 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD1_PJ6, "GPIO_AUD1_PJ6"),
299 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD2_PJ7, "GPIO_AUD2_PJ7"),
300 PINCTRL_PIN(TEGRA_PIN_GPIO_AUD3_PK0, "GPIO_AUD3_PK0"),
301 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SCL_PL0, "GEN7_I2C_SCL_PL0"),
302 PINCTRL_PIN(TEGRA_PIN_GEN7_I2C_SDA_PL1, "GEN7_I2C_SDA_PL1"),
303 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SCL_PL2, "GEN9_I2C_SCL_PL2"),
304 PINCTRL_PIN(TEGRA_PIN_GEN9_I2C_SDA_PL3, "GEN9_I2C_SDA_PL3"),
305 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PL4, "USB_VBUS_EN0_PL4"),
306 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PL5, "USB_VBUS_EN1_PL5"),
307 PINCTRL_PIN(TEGRA_PIN_GP_PWM6_PL6, "GP_PWM6_PL6"),
308 PINCTRL_PIN(TEGRA_PIN_GP_PWM7_PL7, "GP_PWM7_PL7"),
309 PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PM0, "DMIC1_DAT_PM0"),
310 PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PM1, "DMIC1_CLK_PM1"),
311 PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PM2, "DMIC2_DAT_PM2"),
312 PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PM3, "DMIC2_CLK_PM3"),
313 PINCTRL_PIN(TEGRA_PIN_DMIC4_DAT_PM4, "DMIC4_DAT_PM4"),
314 PINCTRL_PIN(TEGRA_PIN_DMIC4_CLK_PM5, "DMIC4_CLK_PM5"),
315 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM1_PN0, "GPIO_CAM1_PN0"),
316 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM2_PN1, "GPIO_CAM2_PN1"),
317 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM3_PN2, "GPIO_CAM3_PN2"),
318 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM4_PN3, "GPIO_CAM4_PN3"),
319 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM5_PN4, "GPIO_CAM6_PN5"),
320 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM6_PN5, "GPIO_CAM6_PN5"),
321 PINCTRL_PIN(TEGRA_PIN_GPIO_CAM7_PN6, "GPIO_CAM7_PN6"),
322 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH1_CLK_PO0, "EXTPERIPH1_CLK_PO0"),
323 PINCTRL_PIN(TEGRA_PIN_EXTPERIPH2_CLK_PO1, "EXTPERIPH2_CLK_PO1"),
324 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PO2, "CAM_I2C_SCL_PO2"),
325 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PO3, "CAM_I2C_SDA_PO3"),
326 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH0_HPD_PP0, "DP_AUX_CH0_HPD_PP0"),
327 PINCTRL_PIN(TEGRA_PIN_DP_AUX_CH1_HPD_PP1, "DP_AUX_CH1_HPD_PP1"),
328 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PP2, "HDMI_CEC_PP2"),
329 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP0_PP3, "GPIO_EDP0_PP3"),
330 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP1_PP4, "GPIO_EDP1_PP4"),
331 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP2_PP5, "GPIO_EDP2_PP5"),
332 PINCTRL_PIN(TEGRA_PIN_GPIO_EDP3_PP6, "GPIO_EDP3_PP6"),
333 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_CLK_PQ0, "DIRECTDC1_CLK_PQ0"),
334 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_IN_PQ1, "DIRECTDC1_IN_PQ1"),
335 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT0_PQ2, "DIRECTDC1_OUT0_PQ2"),
336 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT1_PQ3, "DIRECTDC1_OUT1_PQ3"),
337 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT2_PQ4, "DIRECTDC1_OUT2_PQ4"),
338 PINCTRL_PIN(TEGRA_PIN_DIRECTDC1_OUT3_PQ5, "DIRECTDC1_OUT3_PQ5"),
339 PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PR0, "QSPI_SCK_PR0"),
340 PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PR1, "QSPI_IO0_PR1"),
341 PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PR2, "QSPI_IO1_PR2"),
342 PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PR3, "QSPI_IO2_PR3"),
343 PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PR4, "QSPI_IO3_PR4"),
344 PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PR5, "QSPI_CS_N_PR5"),
345 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PT0, "UART1_TX_PT0"),
346 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PT1, "UART1_RX_PT1"),
347 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PT2, "UART1_RTS_PT2"),
348 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PT3, "UART1_CTS_PT3"),
349 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PX0, "UART2_TX_PX0"),
350 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PX1, "UART2_RX_PX1"),
351 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PX2, "UART2_RTS_PX2"),
352 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PX3, "UART2_CTS_PX3"),
353 PINCTRL_PIN(TEGRA_PIN_UART5_TX_PX4, "UART5_TX_PX4"),
354 PINCTRL_PIN(TEGRA_PIN_UART5_RX_PX5, "UART5_RX_PX5"),
355 PINCTRL_PIN(TEGRA_PIN_UART5_RTS_PX6, "UART5_RTS_PX6"),
356 PINCTRL_PIN(TEGRA_PIN_UART5_CTS_PX7, "UART5_CTS_PX7"),
357 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM1_PY0, "GPIO_MDM1_PY0"),
358 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM2_PY1, "GPIO_MDM2_PY1"),
359 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM3_PY2, "GPIO_MDM3_PY2"),
360 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM4_PY3, "GPIO_MDM4_PY3"),
361 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM5_PY4, "GPIO_MDM5_PY4"),
362 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM6_PY5, "GPIO_MDM6_PY5"),
363 PINCTRL_PIN(TEGRA_PIN_GPIO_MDM7_PY6, "GPIO_MDM7_PY6"),
364 PINCTRL_PIN(TEGRA_PIN_UFS0_REF_CLK_PBB0, "UFS0_REF_CLK_PBB0"),
365 PINCTRL_PIN(TEGRA_PIN_UFS0_RST_PBB1, "UFS0_RST_PBB1"),
366 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PCC0, "DAP4_SCLK_PCC0"),
367 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PCC1, "DAP4_DOUT_PCC1"),
368 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PCC2, "DAP4_DIN_PCC2"),
369 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PCC3, "DAP4_FS_PCC3"),
370 PINCTRL_PIN(TEGRA_PIN_DIRECTDC_COMP, "DIRECTDC_COMP"),
371 PINCTRL_PIN(TEGRA_PIN_SDMMC1_COMP, "SDMMC1_COMP"),
372 PINCTRL_PIN(TEGRA_PIN_EQOS_COMP, "EQOS_COMP"),
373 PINCTRL_PIN(TEGRA_PIN_SDMMC3_COMP, "SDMMC3_COMP"),
374 PINCTRL_PIN(TEGRA_PIN_QSPI_COMP, "QSPI_COMP"),
375};
376
377static const unsigned int pex_l0_rst_n_pa0_pins[] = {
378 TEGRA_PIN_PEX_L0_RST_N_PA0,
379};
380
381static const unsigned int pex_l0_clkreq_n_pa1_pins[] = {
382 TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
383};
384
385static const unsigned int pex_wake_n_pa2_pins[] = {
386 TEGRA_PIN_PEX_WAKE_N_PA2,
387};
388
389static const unsigned int pex_l1_rst_n_pa3_pins[] = {
390 TEGRA_PIN_PEX_L1_RST_N_PA3,
391};
392
393static const unsigned int pex_l1_clkreq_n_pa4_pins[] = {
394 TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
395};
396
397static const unsigned int pex_l2_rst_n_pa5_pins[] = {
398 TEGRA_PIN_PEX_L2_RST_N_PA5,
399};
400
401static const unsigned int pex_l2_clkreq_n_pa6_pins[] = {
402 TEGRA_PIN_PEX_L2_CLKREQ_N_PA6,
403};
404
405static const unsigned int uart4_tx_pb0_pins[] = {
406 TEGRA_PIN_UART4_TX_PB0,
407};
408
409static const unsigned int uart4_rx_pb1_pins[] = {
410 TEGRA_PIN_UART4_RX_PB1,
411};
412
413static const unsigned int uart4_rts_pb2_pins[] = {
414 TEGRA_PIN_UART4_RTS_PB2,
415};
416
417static const unsigned int uart4_cts_pb3_pins[] = {
418 TEGRA_PIN_UART4_CTS_PB3,
419};
420
421static const unsigned int gpio_wan1_pb4_pins[] = {
422 TEGRA_PIN_GPIO_WAN1_PB4,
423};
424
425static const unsigned int gpio_wan2_pb5_pins[] = {
426 TEGRA_PIN_GPIO_WAN2_PB5,
427};
428
429static const unsigned int gpio_wan3_pb6_pins[] = {
430 TEGRA_PIN_GPIO_WAN3_PB6,
431};
432
433static const unsigned int gpio_wan4_pc0_pins[] = {
434 TEGRA_PIN_GPIO_WAN4_PC0,
435};
436
437static const unsigned int dap2_sclk_pc1_pins[] = {
438 TEGRA_PIN_DAP2_SCLK_PC1,
439};
440
441static const unsigned int dap2_dout_pc2_pins[] = {
442 TEGRA_PIN_DAP2_DOUT_PC2,
443};
444
445static const unsigned int dap2_din_pc3_pins[] = {
446 TEGRA_PIN_DAP2_DIN_PC3,
447};
448
449static const unsigned int dap2_fs_pc4_pins[] = {
450 TEGRA_PIN_DAP2_FS_PC4,
451};
452
453static const unsigned int gen1_i2c_scl_pc5_pins[] = {
454 TEGRA_PIN_GEN1_I2C_SCL_PC5,
455};
456
457static const unsigned int gen1_i2c_sda_pc6_pins[] = {
458 TEGRA_PIN_GEN1_I2C_SDA_PC6,
459};
460
461static const unsigned int sdmmc1_clk_pd0_pins[] = {
462 TEGRA_PIN_SDMMC1_CLK_PD0,
463};
464
465static const unsigned int sdmmc1_cmd_pd1_pins[] = {
466 TEGRA_PIN_SDMMC1_CMD_PD1,
467};
468
469static const unsigned int sdmmc1_dat0_pd2_pins[] = {
470 TEGRA_PIN_SDMMC1_DAT0_PD2,
471};
472
473static const unsigned int sdmmc1_dat1_pd3_pins[] = {
474 TEGRA_PIN_SDMMC1_DAT1_PD3,
475};
476
477static const unsigned int sdmmc1_dat2_pd4_pins[] = {
478 TEGRA_PIN_SDMMC1_DAT2_PD4,
479};
480
481static const unsigned int sdmmc1_dat3_pd5_pins[] = {
482 TEGRA_PIN_SDMMC1_DAT3_PD5,
483};
484
485static const unsigned int eqos_txc_pe0_pins[] = {
486 TEGRA_PIN_EQOS_TXC_PE0,
487};
488
489static const unsigned int eqos_td0_pe1_pins[] = {
490 TEGRA_PIN_EQOS_TD0_PE1,
491};
492
493static const unsigned int eqos_td1_pe2_pins[] = {
494 TEGRA_PIN_EQOS_TD1_PE2,
495};
496
497static const unsigned int eqos_td2_pe3_pins[] = {
498 TEGRA_PIN_EQOS_TD2_PE3,
499};
500
501static const unsigned int eqos_td3_pe4_pins[] = {
502 TEGRA_PIN_EQOS_TD3_PE4,
503};
504
505static const unsigned int eqos_tx_ctl_pe5_pins[] = {
506 TEGRA_PIN_EQOS_TX_CTL_PE5,
507};
508
509static const unsigned int eqos_rd0_pe6_pins[] = {
510 TEGRA_PIN_EQOS_RD0_PE6,
511};
512
513static const unsigned int eqos_rd1_pe7_pins[] = {
514 TEGRA_PIN_EQOS_RD1_PE7,
515};
516
517static const unsigned int eqos_rd2_pf0_pins[] = {
518 TEGRA_PIN_EQOS_RD2_PF0,
519};
520
521static const unsigned int eqos_rd3_pf1_pins[] = {
522 TEGRA_PIN_EQOS_RD3_PF1,
523};
524
525static const unsigned int eqos_rx_ctl_pf2_pins[] = {
526 TEGRA_PIN_EQOS_RX_CTL_PF2,
527};
528
529static const unsigned int eqos_rxc_pf3_pins[] = {
530 TEGRA_PIN_EQOS_RXC_PF3,
531};
532
533static const unsigned int eqos_mdio_pf4_pins[] = {
534 TEGRA_PIN_EQOS_MDIO_PF4,
535};
536
537static const unsigned int eqos_mdc_pf5_pins[] = {
538 TEGRA_PIN_EQOS_MDC_PF5,
539};
540
541static const unsigned int sdmmc3_clk_pg0_pins[] = {
542 TEGRA_PIN_SDMMC3_CLK_PG0,
543};
544
545static const unsigned int sdmmc3_cmd_pg1_pins[] = {
546 TEGRA_PIN_SDMMC3_CMD_PG1,
547};
548
549static const unsigned int sdmmc3_dat0_pg2_pins[] = {
550 TEGRA_PIN_SDMMC3_DAT0_PG2,
551};
552
553static const unsigned int sdmmc3_dat1_pg3_pins[] = {
554 TEGRA_PIN_SDMMC3_DAT1_PG3,
555};
556
557static const unsigned int sdmmc3_dat2_pg4_pins[] = {
558 TEGRA_PIN_SDMMC3_DAT2_PG4,
559};
560
561static const unsigned int sdmmc3_dat3_pg5_pins[] = {
562 TEGRA_PIN_SDMMC3_DAT3_PG5,
563};
564
565static const unsigned int gpio_wan5_ph0_pins[] = {
566 TEGRA_PIN_GPIO_WAN5_PH0,
567};
568
569static const unsigned int gpio_wan6_ph1_pins[] = {
570 TEGRA_PIN_GPIO_WAN6_PH1,
571};
572
573static const unsigned int gpio_wan7_ph2_pins[] = {
574 TEGRA_PIN_GPIO_WAN7_PH2,
575};
576
577static const unsigned int gpio_wan8_ph3_pins[] = {
578 TEGRA_PIN_GPIO_WAN8_PH3,
579};
580
581static const unsigned int bcpu_pwr_req_ph4_pins[] = {
582 TEGRA_PIN_BCPU_PWR_REQ_PH4,
583};
584
585static const unsigned int mcpu_pwr_req_ph5_pins[] = {
586 TEGRA_PIN_MCPU_PWR_REQ_PH5,
587};
588
589static const unsigned int gpu_pwr_req_ph6_pins[] = {
590 TEGRA_PIN_GPU_PWR_REQ_PH6,
591};
592
593static const unsigned int gpio_pq0_pi0_pins[] = {
594 TEGRA_PIN_GPIO_PQ0_PI0,
595};
596
597static const unsigned int gpio_pq1_pi1_pins[] = {
598 TEGRA_PIN_GPIO_PQ1_PI1,
599};
600
601static const unsigned int gpio_pq2_pi2_pins[] = {
602 TEGRA_PIN_GPIO_PQ2_PI2,
603};
604
605static const unsigned int gpio_pq3_pi3_pins[] = {
606 TEGRA_PIN_GPIO_PQ3_PI3,
607};
608
609static const unsigned int gpio_pq4_pi4_pins[] = {
610 TEGRA_PIN_GPIO_PQ4_PI4,
611};
612
613static const unsigned int gpio_pq5_pi5_pins[] = {
614 TEGRA_PIN_GPIO_PQ5_PI5,
615};
616
617static const unsigned int gpio_pq6_pi6_pins[] = {
618 TEGRA_PIN_GPIO_PQ6_PI6,
619};
620
621static const unsigned int gpio_pq7_pi7_pins[] = {
622 TEGRA_PIN_GPIO_PQ7_PI7,
623};
624
625static const unsigned int dap1_sclk_pj0_pins[] = {
626 TEGRA_PIN_DAP1_SCLK_PJ0,
627};
628
629static const unsigned int dap1_dout_pj1_pins[] = {
630 TEGRA_PIN_DAP1_DOUT_PJ1,
631};
632
633static const unsigned int dap1_din_pj2_pins[] = {
634 TEGRA_PIN_DAP1_DIN_PJ2,
635};
636
637static const unsigned int dap1_fs_pj3_pins[] = {
638 TEGRA_PIN_DAP1_FS_PJ3,
639};
640
641static const unsigned int aud_mclk_pj4_pins[] = {
642 TEGRA_PIN_AUD_MCLK_PJ4,
643};
644
645static const unsigned int gpio_aud0_pj5_pins[] = {
646 TEGRA_PIN_GPIO_AUD0_PJ5,
647};
648
649static const unsigned int gpio_aud1_pj6_pins[] = {
650 TEGRA_PIN_GPIO_AUD1_PJ6,
651};
652
653static const unsigned int gpio_aud2_pj7_pins[] = {
654 TEGRA_PIN_GPIO_AUD2_PJ7,
655};
656
657static const unsigned int gpio_aud3_pk0_pins[] = {
658 TEGRA_PIN_GPIO_AUD3_PK0,
659};
660
661static const unsigned int gen7_i2c_scl_pl0_pins[] = {
662 TEGRA_PIN_GEN7_I2C_SCL_PL0,
663};
664
665static const unsigned int gen7_i2c_sda_pl1_pins[] = {
666 TEGRA_PIN_GEN7_I2C_SDA_PL1,
667};
668
669static const unsigned int gen9_i2c_scl_pl2_pins[] = {
670 TEGRA_PIN_GEN9_I2C_SCL_PL2,
671};
672
673static const unsigned int gen9_i2c_sda_pl3_pins[] = {
674 TEGRA_PIN_GEN9_I2C_SDA_PL3,
675};
676
677static const unsigned int usb_vbus_en0_pl4_pins[] = {
678 TEGRA_PIN_USB_VBUS_EN0_PL4,
679};
680
681static const unsigned int usb_vbus_en1_pl5_pins[] = {
682 TEGRA_PIN_USB_VBUS_EN1_PL5,
683};
684
685static const unsigned int gp_pwm6_pl6_pins[] = {
686 TEGRA_PIN_GP_PWM6_PL6,
687};
688
689static const unsigned int gp_pwm7_pl7_pins[] = {
690 TEGRA_PIN_GP_PWM7_PL7,
691};
692
693static const unsigned int dmic1_dat_pm0_pins[] = {
694 TEGRA_PIN_DMIC1_DAT_PM0,
695};
696
697static const unsigned int dmic1_clk_pm1_pins[] = {
698 TEGRA_PIN_DMIC1_CLK_PM1,
699};
700
701static const unsigned int dmic2_dat_pm2_pins[] = {
702 TEGRA_PIN_DMIC2_DAT_PM2,
703};
704
705static const unsigned int dmic2_clk_pm3_pins[] = {
706 TEGRA_PIN_DMIC2_CLK_PM3,
707};
708
709static const unsigned int dmic4_dat_pm4_pins[] = {
710 TEGRA_PIN_DMIC4_DAT_PM4,
711};
712
713static const unsigned int dmic4_clk_pm5_pins[] = {
714 TEGRA_PIN_DMIC4_CLK_PM5,
715};
716
717static const unsigned int gpio_cam1_pn0_pins[] = {
718 TEGRA_PIN_GPIO_CAM1_PN0,
719};
720
721static const unsigned int gpio_cam2_pn1_pins[] = {
722 TEGRA_PIN_GPIO_CAM2_PN1,
723};
724
725static const unsigned int gpio_cam3_pn2_pins[] = {
726 TEGRA_PIN_GPIO_CAM3_PN2,
727};
728
729static const unsigned int gpio_cam4_pn3_pins[] = {
730 TEGRA_PIN_GPIO_CAM4_PN3,
731};
732
733static const unsigned int gpio_cam5_pn4_pins[] = {
734 TEGRA_PIN_GPIO_CAM5_PN4,
735};
736
737static const unsigned int gpio_cam6_pn5_pins[] = {
738 TEGRA_PIN_GPIO_CAM6_PN5,
739};
740
741static const unsigned int gpio_cam7_pn6_pins[] = {
742 TEGRA_PIN_GPIO_CAM7_PN6,
743};
744
745static const unsigned int extperiph1_clk_po0_pins[] = {
746 TEGRA_PIN_EXTPERIPH1_CLK_PO0,
747};
748
749static const unsigned int extperiph2_clk_po1_pins[] = {
750 TEGRA_PIN_EXTPERIPH2_CLK_PO1,
751};
752
753static const unsigned int cam_i2c_scl_po2_pins[] = {
754 TEGRA_PIN_CAM_I2C_SCL_PO2,
755};
756
757static const unsigned int cam_i2c_sda_po3_pins[] = {
758 TEGRA_PIN_CAM_I2C_SDA_PO3,
759};
760
761static const unsigned int dp_aux_ch0_hpd_pp0_pins[] = {
762 TEGRA_PIN_DP_AUX_CH0_HPD_PP0,
763};
764
765static const unsigned int dp_aux_ch1_hpd_pp1_pins[] = {
766 TEGRA_PIN_DP_AUX_CH1_HPD_PP1,
767};
768
769static const unsigned int hdmi_cec_pp2_pins[] = {
770 TEGRA_PIN_HDMI_CEC_PP2,
771};
772
773static const unsigned int gpio_edp0_pp3_pins[] = {
774 TEGRA_PIN_GPIO_EDP0_PP3,
775};
776
777static const unsigned int gpio_edp1_pp4_pins[] = {
778 TEGRA_PIN_GPIO_EDP1_PP4,
779};
780
781static const unsigned int gpio_edp2_pp5_pins[] = {
782 TEGRA_PIN_GPIO_EDP2_PP5,
783};
784
785static const unsigned int gpio_edp3_pp6_pins[] = {
786 TEGRA_PIN_GPIO_EDP3_PP6,
787};
788
789static const unsigned int directdc1_clk_pq0_pins[] = {
790 TEGRA_PIN_DIRECTDC1_CLK_PQ0,
791};
792
793static const unsigned int directdc1_in_pq1_pins[] = {
794 TEGRA_PIN_DIRECTDC1_IN_PQ1,
795};
796
797static const unsigned int directdc1_out0_pq2_pins[] = {
798 TEGRA_PIN_DIRECTDC1_OUT0_PQ2,
799};
800
801static const unsigned int directdc1_out1_pq3_pins[] = {
802 TEGRA_PIN_DIRECTDC1_OUT1_PQ3,
803};
804
805static const unsigned int directdc1_out2_pq4_pins[] = {
806 TEGRA_PIN_DIRECTDC1_OUT2_PQ4,
807};
808
809static const unsigned int directdc1_out3_pq5_pins[] = {
810 TEGRA_PIN_DIRECTDC1_OUT3_PQ5,
811};
812
813static const unsigned int qspi_sck_pr0_pins[] = {
814 TEGRA_PIN_QSPI_SCK_PR0,
815};
816
817static const unsigned int qspi_io0_pr1_pins[] = {
818 TEGRA_PIN_QSPI_IO0_PR1,
819};
820
821static const unsigned int qspi_io1_pr2_pins[] = {
822 TEGRA_PIN_QSPI_IO1_PR2,
823};
824
825static const unsigned int qspi_io2_pr3_pins[] = {
826 TEGRA_PIN_QSPI_IO2_PR3,
827};
828
829static const unsigned int qspi_io3_pr4_pins[] = {
830 TEGRA_PIN_QSPI_IO3_PR4,
831};
832
833static const unsigned int qspi_cs_n_pr5_pins[] = {
834 TEGRA_PIN_QSPI_CS_N_PR5,
835};
836
837static const unsigned int pwr_i2c_scl_ps0_pins[] = {
838 TEGRA_PIN_PWR_I2C_SCL_PS0,
839};
840
841static const unsigned int pwr_i2c_sda_ps1_pins[] = {
842 TEGRA_PIN_PWR_I2C_SDA_PS1,
843};
844
845static const unsigned int batt_oc_ps2_pins[] = {
846 TEGRA_PIN_BATT_OC_PS2,
847};
848
849static const unsigned int safe_state_ps3_pins[] = {
850 TEGRA_PIN_SAFE_STATE_PS3,
851};
852
853static const unsigned int vcomp_alert_ps4_pins[] = {
854 TEGRA_PIN_VCOMP_ALERT_PS4,
855};
856
857static const unsigned int uart1_tx_pt0_pins[] = {
858 TEGRA_PIN_UART1_TX_PT0,
859};
860
861static const unsigned int uart1_rx_pt1_pins[] = {
862 TEGRA_PIN_UART1_RX_PT1,
863};
864
865static const unsigned int uart1_rts_pt2_pins[] = {
866 TEGRA_PIN_UART1_RTS_PT2,
867};
868
869static const unsigned int uart1_cts_pt3_pins[] = {
870 TEGRA_PIN_UART1_CTS_PT3,
871};
872
873static const unsigned int gpio_dis0_pu0_pins[] = {
874 TEGRA_PIN_GPIO_DIS0_PU0,
875};
876
877static const unsigned int gpio_dis1_pu1_pins[] = {
878 TEGRA_PIN_GPIO_DIS1_PU1,
879};
880
881static const unsigned int gpio_dis2_pu2_pins[] = {
882 TEGRA_PIN_GPIO_DIS2_PU2,
883};
884
885static const unsigned int gpio_dis3_pu3_pins[] = {
886 TEGRA_PIN_GPIO_DIS3_PU3,
887};
888
889static const unsigned int gpio_dis4_pu4_pins[] = {
890 TEGRA_PIN_GPIO_DIS4_PU4,
891};
892
893static const unsigned int gpio_dis5_pu5_pins[] = {
894 TEGRA_PIN_GPIO_DIS5_PU5,
895};
896
897static const unsigned int gpio_sen0_pv0_pins[] = {
898 TEGRA_PIN_GPIO_SEN0_PV0,
899};
900
901static const unsigned int gpio_sen1_pv1_pins[] = {
902 TEGRA_PIN_GPIO_SEN1_PV1,
903};
904
905static const unsigned int gpio_sen2_pv2_pins[] = {
906 TEGRA_PIN_GPIO_SEN2_PV2,
907};
908
909static const unsigned int gpio_sen3_pv3_pins[] = {
910 TEGRA_PIN_GPIO_SEN3_PV3,
911};
912
913static const unsigned int gpio_sen4_pv4_pins[] = {
914 TEGRA_PIN_GPIO_SEN4_PV4,
915};
916
917static const unsigned int gpio_sen5_pv5_pins[] = {
918 TEGRA_PIN_GPIO_SEN5_PV5,
919};
920
921static const unsigned int gpio_sen6_pv6_pins[] = {
922 TEGRA_PIN_GPIO_SEN6_PV6,
923};
924
925static const unsigned int gpio_sen7_pv7_pins[] = {
926 TEGRA_PIN_GPIO_SEN7_PV7,
927};
928
929static const unsigned int gen8_i2c_scl_pw0_pins[] = {
930 TEGRA_PIN_GEN8_I2C_SCL_PW0,
931};
932
933static const unsigned int gen8_i2c_sda_pw1_pins[] = {
934 TEGRA_PIN_GEN8_I2C_SDA_PW1,
935};
936
937static const unsigned int uart3_tx_pw2_pins[] = {
938 TEGRA_PIN_UART3_TX_PW2,
939};
940
941static const unsigned int uart3_rx_pw3_pins[] = {
942 TEGRA_PIN_UART3_RX_PW3,
943};
944
945static const unsigned int uart3_rts_pw4_pins[] = {
946 TEGRA_PIN_UART3_RTS_PW4,
947};
948
949static const unsigned int uart3_cts_pw5_pins[] = {
950 TEGRA_PIN_UART3_CTS_PW5,
951};
952
953static const unsigned int uart7_tx_pw6_pins[] = {
954 TEGRA_PIN_UART7_TX_PW6,
955};
956
957static const unsigned int uart7_rx_pw7_pins[] = {
958 TEGRA_PIN_UART7_RX_PW7,
959};
960
961static const unsigned int uart2_tx_px0_pins[] = {
962 TEGRA_PIN_UART2_TX_PX0,
963};
964
965static const unsigned int uart2_rx_px1_pins[] = {
966 TEGRA_PIN_UART2_RX_PX1,
967};
968
969static const unsigned int uart2_rts_px2_pins[] = {
970 TEGRA_PIN_UART2_RTS_PX2,
971};
972
973static const unsigned int uart2_cts_px3_pins[] = {
974 TEGRA_PIN_UART2_CTS_PX3,
975};
976
977static const unsigned int uart5_tx_px4_pins[] = {
978 TEGRA_PIN_UART5_TX_PX4,
979};
980
981static const unsigned int uart5_rx_px5_pins[] = {
982 TEGRA_PIN_UART5_RX_PX5,
983};
984
985static const unsigned int uart5_rts_px6_pins[] = {
986 TEGRA_PIN_UART5_RTS_PX6,
987};
988
989static const unsigned int uart5_cts_px7_pins[] = {
990 TEGRA_PIN_UART5_CTS_PX7,
991};
992
993static const unsigned int gpio_mdm1_py0_pins[] = {
994 TEGRA_PIN_GPIO_MDM1_PY0,
995};
996
997static const unsigned int gpio_mdm2_py1_pins[] = {
998 TEGRA_PIN_GPIO_MDM2_PY1,
999};
1000
1001static const unsigned int gpio_mdm3_py2_pins[] = {
1002 TEGRA_PIN_GPIO_MDM3_PY2,
1003};
1004
1005static const unsigned int gpio_mdm4_py3_pins[] = {
1006 TEGRA_PIN_GPIO_MDM4_PY3,
1007};
1008
1009static const unsigned int gpio_mdm5_py4_pins[] = {
1010 TEGRA_PIN_GPIO_MDM5_PY4,
1011};
1012
1013static const unsigned int gpio_mdm6_py5_pins[] = {
1014 TEGRA_PIN_GPIO_MDM6_PY5,
1015};
1016
1017static const unsigned int gpio_mdm7_py6_pins[] = {
1018 TEGRA_PIN_GPIO_MDM7_PY6,
1019};
1020
1021static const unsigned int can1_dout_pz0_pins[] = {
1022 TEGRA_PIN_CAN1_DOUT_PZ0,
1023};
1024
1025static const unsigned int can1_din_pz1_pins[] = {
1026 TEGRA_PIN_CAN1_DIN_PZ1,
1027};
1028
1029static const unsigned int can0_dout_pz2_pins[] = {
1030 TEGRA_PIN_CAN0_DOUT_PZ2,
1031};
1032
1033static const unsigned int can0_din_pz3_pins[] = {
1034 TEGRA_PIN_CAN0_DIN_PZ3,
1035};
1036
1037static const unsigned int can_gpio0_paa0_pins[] = {
1038 TEGRA_PIN_CAN_GPIO0_PAA0,
1039};
1040
1041static const unsigned int can_gpio1_paa1_pins[] = {
1042 TEGRA_PIN_CAN_GPIO1_PAA1,
1043};
1044
1045static const unsigned int can_gpio2_paa2_pins[] = {
1046 TEGRA_PIN_CAN_GPIO2_PAA2,
1047};
1048
1049static const unsigned int can_gpio3_paa3_pins[] = {
1050 TEGRA_PIN_CAN_GPIO3_PAA3,
1051};
1052
1053static const unsigned int can_gpio4_paa4_pins[] = {
1054 TEGRA_PIN_CAN_GPIO4_PAA4,
1055};
1056
1057static const unsigned int can_gpio5_paa5_pins[] = {
1058 TEGRA_PIN_CAN_GPIO5_PAA5,
1059};
1060
1061static const unsigned int can_gpio6_paa6_pins[] = {
1062 TEGRA_PIN_CAN_GPIO6_PAA6,
1063};
1064
1065static const unsigned int can_gpio7_paa7_pins[] = {
1066 TEGRA_PIN_CAN_GPIO7_PAA7,
1067};
1068
1069static const unsigned int ufs0_ref_clk_pbb0_pins[] = {
1070 TEGRA_PIN_UFS0_REF_CLK_PBB0,
1071};
1072
1073static const unsigned int ufs0_rst_pbb1_pins[] = {
1074 TEGRA_PIN_UFS0_RST_PBB1,
1075};
1076
1077static const unsigned int dap4_sclk_pcc0_pins[] = {
1078 TEGRA_PIN_DAP4_SCLK_PCC0,
1079};
1080
1081static const unsigned int dap4_dout_pcc1_pins[] = {
1082 TEGRA_PIN_DAP4_DOUT_PCC1,
1083};
1084
1085static const unsigned int dap4_din_pcc2_pins[] = {
1086 TEGRA_PIN_DAP4_DIN_PCC2,
1087};
1088
1089static const unsigned int dap4_fs_pcc3_pins[] = {
1090 TEGRA_PIN_DAP4_FS_PCC3,
1091};
1092
1093static const unsigned int gpio_sen8_pee0_pins[] = {
1094 TEGRA_PIN_GPIO_SEN8_PEE0,
1095};
1096
1097static const unsigned int gpio_sen9_pee1_pins[] = {
1098 TEGRA_PIN_GPIO_SEN9_PEE1,
1099};
1100
1101static const unsigned int touch_clk_pee2_pins[] = {
1102 TEGRA_PIN_TOUCH_CLK_PEE2,
1103};
1104
1105static const unsigned int power_on_pff0_pins[] = {
1106 TEGRA_PIN_POWER_ON_PFF0,
1107};
1108
1109static const unsigned int gpio_sw1_pff1_pins[] = {
1110 TEGRA_PIN_GPIO_SW1_PFF1,
1111};
1112
1113static const unsigned int gpio_sw2_pff2_pins[] = {
1114 TEGRA_PIN_GPIO_SW2_PFF2,
1115};
1116
1117static const unsigned int gpio_sw3_pff3_pins[] = {
1118 TEGRA_PIN_GPIO_SW3_PFF3,
1119};
1120
1121static const unsigned int gpio_sw4_pff4_pins[] = {
1122 TEGRA_PIN_GPIO_SW4_PFF4,
1123};
1124
1125static const unsigned int directdc_comp_pins[] = {
1126 TEGRA_PIN_DIRECTDC_COMP,
1127};
1128
1129static const unsigned int sdmmc1_comp_pins[] = {
1130 TEGRA_PIN_SDMMC1_COMP,
1131};
1132
1133static const unsigned int eqos_comp_pins[] = {
1134 TEGRA_PIN_EQOS_COMP,
1135};
1136
1137static const unsigned int sdmmc3_comp_pins[] = {
1138 TEGRA_PIN_SDMMC3_COMP,
1139};
1140
1141static const unsigned int qspi_comp_pins[] = {
1142 TEGRA_PIN_QSPI_COMP,
1143};
1144
1145static const unsigned int shutdown_pins[] = {
1146 TEGRA_PIN_SHUTDOWN,
1147};
1148
1149static const unsigned int pmu_int_pins[] = {
1150 TEGRA_PIN_PMU_INT,
1151};
1152
1153static const unsigned int soc_pwr_req_pins[] = {
1154 TEGRA_PIN_SOC_PWR_REQ,
1155};
1156
1157static const unsigned int clk_32k_in_pins[] = {
1158 TEGRA_PIN_CLK_32K_IN,
1159};
1160
1161static const unsigned int sdmmc4_clk_pins[] = {};
1162
1163static const unsigned int sdmmc4_cmd_pins[] = {};
1164
1165static const unsigned int sdmmc4_dqs_pins[] = {};
1166
1167static const unsigned int sdmmc4_dat7_pins[] = {};
1168
1169static const unsigned int sdmmc4_dat6_pins[] = {};
1170
1171static const unsigned int sdmmc4_dat5_pins[] = {};
1172
1173static const unsigned int sdmmc4_dat4_pins[] = {};
1174
1175static const unsigned int sdmmc4_dat3_pins[] = {};
1176
1177static const unsigned int sdmmc4_dat2_pins[] = {};
1178
1179static const unsigned int sdmmc4_dat1_pins[] = {};
1180
1181static const unsigned int sdmmc4_dat0_pins[] = {};
1182
1183/* Define unique ID for each function */
1184enum tegra_mux_dt {
1185 TEGRA_MUX_RSVD0,
1186 TEGRA_MUX_RSVD1,
1187 TEGRA_MUX_RSVD2,
1188 TEGRA_MUX_RSVD3,
1189 TEGRA_MUX_TOUCH,
1190 TEGRA_MUX_UARTC,
1191 TEGRA_MUX_I2C8,
1192 TEGRA_MUX_UARTG,
1193 TEGRA_MUX_SPI2,
1194 TEGRA_MUX_GP,
1195 TEGRA_MUX_DCA,
1196 TEGRA_MUX_WDT,
1197 TEGRA_MUX_I2C2,
1198 TEGRA_MUX_CAN1,
1199 TEGRA_MUX_CAN0,
1200 TEGRA_MUX_DMIC3,
1201 TEGRA_MUX_DMIC5,
1202 TEGRA_MUX_GPIO,
1203 TEGRA_MUX_DSPK1,
1204 TEGRA_MUX_DSPK0,
1205 TEGRA_MUX_SPDIF,
1206 TEGRA_MUX_AUD,
1207 TEGRA_MUX_I2S1,
1208 TEGRA_MUX_DMIC1,
1209 TEGRA_MUX_DMIC2,
1210 TEGRA_MUX_I2S3,
1211 TEGRA_MUX_DMIC4,
1212 TEGRA_MUX_I2S4,
1213 TEGRA_MUX_EXTPERIPH2,
1214 TEGRA_MUX_EXTPERIPH1,
1215 TEGRA_MUX_I2C3,
1216 TEGRA_MUX_VGP1,
1217 TEGRA_MUX_VGP2,
1218 TEGRA_MUX_VGP3,
1219 TEGRA_MUX_VGP4,
1220 TEGRA_MUX_VGP5,
1221 TEGRA_MUX_VGP6,
1222 TEGRA_MUX_EXTPERIPH3,
1223 TEGRA_MUX_EXTPERIPH4,
1224 TEGRA_MUX_SPI4,
1225 TEGRA_MUX_I2S2,
1226 TEGRA_MUX_UARTD,
1227 TEGRA_MUX_I2C1,
1228 TEGRA_MUX_UARTA,
1229 TEGRA_MUX_DIRECTDC1,
1230 TEGRA_MUX_DIRECTDC,
1231 TEGRA_MUX_IQC0,
1232 TEGRA_MUX_IQC1,
1233 TEGRA_MUX_I2S6,
1234 TEGRA_MUX_DTV,
1235 TEGRA_MUX_UARTF,
1236 TEGRA_MUX_SDMMC3,
1237 TEGRA_MUX_SDMMC4,
1238 TEGRA_MUX_SDMMC1,
1239 TEGRA_MUX_DP,
1240 TEGRA_MUX_HDMI,
1241 TEGRA_MUX_PE2,
1242 TEGRA_MUX_SATA,
1243 TEGRA_MUX_PE,
1244 TEGRA_MUX_PE1,
1245 TEGRA_MUX_PE0,
1246 TEGRA_MUX_SOC,
1247 TEGRA_MUX_EQOS,
1248 TEGRA_MUX_SDMMC2,
1249 TEGRA_MUX_QSPI,
1250 TEGRA_MUX_SCE,
1251 TEGRA_MUX_I2C5,
1252 TEGRA_MUX_DISPLAYA,
1253 TEGRA_MUX_DISPLAYB,
1254 TEGRA_MUX_DCC,
1255 TEGRA_MUX_DCB,
1256 TEGRA_MUX_SPI1,
1257 TEGRA_MUX_UARTB,
1258 TEGRA_MUX_UARTE,
1259 TEGRA_MUX_SPI3,
1260 TEGRA_MUX_NV,
1261 TEGRA_MUX_CCLA,
1262 TEGRA_MUX_I2C7,
1263 TEGRA_MUX_I2C9,
1264 TEGRA_MUX_I2S5,
1265 TEGRA_MUX_USB,
1266 TEGRA_MUX_UFS0,
1267};
1268
1269/* Make list of each function name */
1270#define TEGRA_PIN_FUNCTION(lid) #lid
1271
1272static const char * const tegra186_functions[] = {
1273 TEGRA_PIN_FUNCTION(rsvd0),
1274 TEGRA_PIN_FUNCTION(rsvd1),
1275 TEGRA_PIN_FUNCTION(rsvd2),
1276 TEGRA_PIN_FUNCTION(rsvd3),
1277 TEGRA_PIN_FUNCTION(touch),
1278 TEGRA_PIN_FUNCTION(uartc),
1279 TEGRA_PIN_FUNCTION(i2c8),
1280 TEGRA_PIN_FUNCTION(uartg),
1281 TEGRA_PIN_FUNCTION(spi2),
1282 TEGRA_PIN_FUNCTION(gp),
1283 TEGRA_PIN_FUNCTION(dca),
1284 TEGRA_PIN_FUNCTION(wdt),
1285 TEGRA_PIN_FUNCTION(i2c2),
1286 TEGRA_PIN_FUNCTION(can1),
1287 TEGRA_PIN_FUNCTION(can0),
1288 TEGRA_PIN_FUNCTION(dmic3),
1289 TEGRA_PIN_FUNCTION(dmic5),
1290 TEGRA_PIN_FUNCTION(gpio),
1291 TEGRA_PIN_FUNCTION(dspk1),
1292 TEGRA_PIN_FUNCTION(dspk0),
1293 TEGRA_PIN_FUNCTION(spdif),
1294 TEGRA_PIN_FUNCTION(aud),
1295 TEGRA_PIN_FUNCTION(i2s1),
1296 TEGRA_PIN_FUNCTION(dmic1),
1297 TEGRA_PIN_FUNCTION(dmic2),
1298 TEGRA_PIN_FUNCTION(i2s3),
1299 TEGRA_PIN_FUNCTION(dmic4),
1300 TEGRA_PIN_FUNCTION(i2s4),
1301 TEGRA_PIN_FUNCTION(extperiph2),
1302 TEGRA_PIN_FUNCTION(extperiph1),
1303 TEGRA_PIN_FUNCTION(i2c3),
1304 TEGRA_PIN_FUNCTION(vgp1),
1305 TEGRA_PIN_FUNCTION(vgp2),
1306 TEGRA_PIN_FUNCTION(vgp3),
1307 TEGRA_PIN_FUNCTION(vgp4),
1308 TEGRA_PIN_FUNCTION(vgp5),
1309 TEGRA_PIN_FUNCTION(vgp6),
1310 TEGRA_PIN_FUNCTION(extperiph3),
1311 TEGRA_PIN_FUNCTION(extperiph4),
1312 TEGRA_PIN_FUNCTION(spi4),
1313 TEGRA_PIN_FUNCTION(i2s2),
1314 TEGRA_PIN_FUNCTION(uartd),
1315 TEGRA_PIN_FUNCTION(i2c1),
1316 TEGRA_PIN_FUNCTION(uarta),
1317 TEGRA_PIN_FUNCTION(directdc1),
1318 TEGRA_PIN_FUNCTION(directdc),
1319 TEGRA_PIN_FUNCTION(iqc0),
1320 TEGRA_PIN_FUNCTION(iqc1),
1321 TEGRA_PIN_FUNCTION(i2s6),
1322 TEGRA_PIN_FUNCTION(dtv),
1323 TEGRA_PIN_FUNCTION(uartf),
1324 TEGRA_PIN_FUNCTION(sdmmc3),
1325 TEGRA_PIN_FUNCTION(sdmmc4),
1326 TEGRA_PIN_FUNCTION(sdmmc1),
1327 TEGRA_PIN_FUNCTION(dp),
1328 TEGRA_PIN_FUNCTION(hdmi),
1329 TEGRA_PIN_FUNCTION(pe2),
1330 TEGRA_PIN_FUNCTION(sata),
1331 TEGRA_PIN_FUNCTION(pe),
1332 TEGRA_PIN_FUNCTION(pe1),
1333 TEGRA_PIN_FUNCTION(pe0),
1334 TEGRA_PIN_FUNCTION(soc),
1335 TEGRA_PIN_FUNCTION(eqos),
1336 TEGRA_PIN_FUNCTION(sdmmc2),
1337 TEGRA_PIN_FUNCTION(qspi),
1338 TEGRA_PIN_FUNCTION(sce),
1339 TEGRA_PIN_FUNCTION(i2c5),
1340 TEGRA_PIN_FUNCTION(displaya),
1341 TEGRA_PIN_FUNCTION(displayb),
1342 TEGRA_PIN_FUNCTION(dcc),
1343 TEGRA_PIN_FUNCTION(dcb),
1344 TEGRA_PIN_FUNCTION(spi1),
1345 TEGRA_PIN_FUNCTION(uartb),
1346 TEGRA_PIN_FUNCTION(uarte),
1347 TEGRA_PIN_FUNCTION(spi3),
1348 TEGRA_PIN_FUNCTION(nv),
1349 TEGRA_PIN_FUNCTION(ccla),
1350 TEGRA_PIN_FUNCTION(i2c7),
1351 TEGRA_PIN_FUNCTION(i2c9),
1352 TEGRA_PIN_FUNCTION(i2s5),
1353 TEGRA_PIN_FUNCTION(usb),
1354 TEGRA_PIN_FUNCTION(ufs0),
1355};
1356
1357#define PINGROUP_REG_Y(r) ((r))
1358#define PINGROUP_REG_N(r) -1
1359
1360#define DRV_PINGROUP_Y(r) ((r))
1361#define DRV_PINGROUP_N(r) -1
1362
1363#define DRV_PINGROUP_ENTRY_N(pg_name) \
1364 .drv_reg = -1, \
1365 .drv_bank = -1, \
1366 .drvdn_bit = -1, \
1367 .drvdn_width = -1, \
1368 .drvup_bit = -1, \
1369 .drvup_width = -1, \
1370 .slwr_bit = -1, \
1371 .slwr_width = -1, \
1372 .slwf_bit = -1, \
1373 .slwf_width = -1
1374
1375#define DRV_PINGROUP_ENTRY_Y(r, drvdn_b, drvdn_w, drvup_b, \
1376 drvup_w, slwr_b, slwr_w, slwf_b, \
1377 slwf_w, bank) \
1378 .drv_reg = ((r)), \
1379 .drv_bank = bank, \
1380 .drvdn_bit = drvdn_b, \
1381 .drvdn_width = drvdn_w, \
1382 .drvup_bit = drvup_b, \
1383 .drvup_width = drvup_w, \
1384 .slwr_bit = slwr_b, \
1385 .slwr_width = slwr_w, \
1386 .slwf_bit = slwf_b, \
1387 .slwf_width = slwf_w
1388
1389#define PIN_PINGROUP_ENTRY_N(pg_name) \
1390 .mux_reg = -1, \
1391 .pupd_reg = -1, \
1392 .tri_reg = -1, \
1393 .einput_bit = -1, \
1394 .e_io_hv_bit = -1, \
1395 .odrain_bit = -1, \
1396 .lock_bit = -1, \
1397 .parked_bit = -1, \
1398 .lpmd_bit = -1, \
1399 .drvtype_bit = -1, \
1400 .lpdr_bit = -1, \
1401 .pbias_buf_bit = -1, \
1402 .preemp_bit = -1, \
1403 .rfu_in_bit = -1
1404
1405#define PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, e_input, \
1406 e_lpdr, e_pbias_buf, gpio_sfio_sel, \
1407 e_od, schmitt_b, drvtype, epreemp, \
1408 io_reset, rfu_in) \
1409 .mux_reg = PINGROUP_REG_Y(r), \
1410 .lpmd_bit = -1, \
1411 .lock_bit = -1, \
1412 .hsm_bit = -1, \
1413 .mux_bank = bank, \
1414 .mux_bit = 0, \
1415 .pupd_reg = PINGROUP_REG_##pupd(r), \
1416 .pupd_bank = bank, \
1417 .pupd_bit = 2, \
1418 .tri_reg = PINGROUP_REG_Y(r), \
1419 .tri_bank = bank, \
1420 .tri_bit = 4, \
1421 .einput_bit = e_input, \
1422 .sfsel_bit = gpio_sfio_sel, \
1423 .odrain_bit = e_od, \
1424 .schmitt_bit = schmitt_b, \
1425 .drvtype_bit = 13, \
1426 .lpdr_bit = e_lpdr, \
1427
1428/* main drive pin groups */
1429#define drive_gpio_aud3_pk0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1430#define drive_gpio_aud2_pj7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1431#define drive_gpio_aud1_pj6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1432#define drive_gpio_aud0_pj5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1433#define drive_aud_mclk_pj4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1434#define drive_dap1_fs_pj3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1435#define drive_dap1_din_pj2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1436#define drive_dap1_dout_pj1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1437#define drive_dap1_sclk_pj0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1438#define drive_dmic1_clk_pm1 DRV_PINGROUP_ENTRY_Y(0x2004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1439#define drive_dmic1_dat_pm0 DRV_PINGROUP_ENTRY_Y(0x200c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1440#define drive_dmic2_dat_pm2 DRV_PINGROUP_ENTRY_Y(0x2014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1441#define drive_dmic2_clk_pm3 DRV_PINGROUP_ENTRY_Y(0x201c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1442#define drive_dmic4_dat_pm4 DRV_PINGROUP_ENTRY_Y(0x2024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1443#define drive_dmic4_clk_pm5 DRV_PINGROUP_ENTRY_Y(0x202c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1444#define drive_dap4_fs_pcc3 DRV_PINGROUP_ENTRY_Y(0x2034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1445#define drive_dap4_din_pcc2 DRV_PINGROUP_ENTRY_Y(0x203c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1446#define drive_dap4_dout_pcc1 DRV_PINGROUP_ENTRY_Y(0x2044, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1447#define drive_dap4_sclk_pcc0 DRV_PINGROUP_ENTRY_Y(0x204c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1448#define drive_extperiph2_clk_po1 DRV_PINGROUP_ENTRY_Y(0x0004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449#define drive_extperiph1_clk_po0 DRV_PINGROUP_ENTRY_Y(0x000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450#define drive_cam_i2c_sda_po3 DRV_PINGROUP_ENTRY_Y(0x0014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451#define drive_cam_i2c_scl_po2 DRV_PINGROUP_ENTRY_Y(0x001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452#define drive_gpio_cam1_pn0 DRV_PINGROUP_ENTRY_Y(0x0024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453#define drive_gpio_cam2_pn1 DRV_PINGROUP_ENTRY_Y(0x002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454#define drive_gpio_cam3_pn2 DRV_PINGROUP_ENTRY_Y(0x0034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1455#define drive_gpio_cam4_pn3 DRV_PINGROUP_ENTRY_Y(0x003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1456#define drive_gpio_cam5_pn4 DRV_PINGROUP_ENTRY_Y(0x0044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1457#define drive_gpio_cam6_pn5 DRV_PINGROUP_ENTRY_Y(0x004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1458#define drive_gpio_cam7_pn6 DRV_PINGROUP_ENTRY_Y(0x0054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1459#define drive_dap2_din_pc3 DRV_PINGROUP_ENTRY_Y(0x4004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1460#define drive_dap2_dout_pc2 DRV_PINGROUP_ENTRY_Y(0x400c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1461#define drive_dap2_fs_pc4 DRV_PINGROUP_ENTRY_Y(0x4014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1462#define drive_dap2_sclk_pc1 DRV_PINGROUP_ENTRY_Y(0x401c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1463#define drive_uart4_cts_pb3 DRV_PINGROUP_ENTRY_Y(0x4024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1464#define drive_uart4_rts_pb2 DRV_PINGROUP_ENTRY_Y(0x402c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1465#define drive_uart4_rx_pb1 DRV_PINGROUP_ENTRY_Y(0x4034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1466#define drive_uart4_tx_pb0 DRV_PINGROUP_ENTRY_Y(0x403c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1467#define drive_gpio_wan4_pc0 DRV_PINGROUP_ENTRY_Y(0x4044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1468#define drive_gpio_wan3_pb6 DRV_PINGROUP_ENTRY_Y(0x404c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1469#define drive_gpio_wan2_pb5 DRV_PINGROUP_ENTRY_Y(0x4054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1470#define drive_gpio_wan1_pb4 DRV_PINGROUP_ENTRY_Y(0x405c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1471#define drive_gen1_i2c_scl_pc5 DRV_PINGROUP_ENTRY_Y(0x4064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1472#define drive_gen1_i2c_sda_pc6 DRV_PINGROUP_ENTRY_Y(0x406c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1473#define drive_uart1_cts_pt3 DRV_PINGROUP_ENTRY_Y(0x5004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1474#define drive_uart1_rts_pt2 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1475#define drive_uart1_rx_pt1 DRV_PINGROUP_ENTRY_Y(0x5014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1476#define drive_uart1_tx_pt0 DRV_PINGROUP_ENTRY_Y(0x501c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1477#define drive_directdc1_out3_pq5 DRV_PINGROUP_ENTRY_Y(0x502c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1478#define drive_directdc1_out2_pq4 DRV_PINGROUP_ENTRY_Y(0x5034, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1479#define drive_directdc1_out1_pq3 DRV_PINGROUP_ENTRY_Y(0x503c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1480#define drive_directdc1_out0_pq2 DRV_PINGROUP_ENTRY_Y(0x5044, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1481#define drive_directdc1_in_pq1 DRV_PINGROUP_ENTRY_Y(0x504c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1482#define drive_directdc1_clk_pq0 DRV_PINGROUP_ENTRY_Y(0x5054, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1483#define drive_gpio_pq0_pi0 DRV_PINGROUP_ENTRY_Y(0x3004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1484#define drive_gpio_pq1_pi1 DRV_PINGROUP_ENTRY_Y(0x300c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1485#define drive_gpio_pq2_pi2 DRV_PINGROUP_ENTRY_Y(0x3014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1486#define drive_gpio_pq3_pi3 DRV_PINGROUP_ENTRY_Y(0x301c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1487#define drive_gpio_pq4_pi4 DRV_PINGROUP_ENTRY_Y(0x3024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1488#define drive_gpio_pq5_pi5 DRV_PINGROUP_ENTRY_Y(0x302c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1489#define drive_gpio_pq6_pi6 DRV_PINGROUP_ENTRY_Y(0x3034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1490#define drive_gpio_pq7_pi7 DRV_PINGROUP_ENTRY_Y(0x303c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1491#define drive_gpio_edp2_pp5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1492#define drive_gpio_edp3_pp6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1493#define drive_gpio_edp0_pp3 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1494#define drive_gpio_edp1_pp4 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1495#define drive_dp_aux_ch0_hpd_pp0 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1496#define drive_dp_aux_ch1_hpd_pp1 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1497#define drive_hdmi_cec_pp2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1498#define drive_pex_l2_clkreq_n_pa6 DRV_PINGROUP_ENTRY_Y(0x7004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1499#define drive_pex_wake_n_pa2 DRV_PINGROUP_ENTRY_Y(0x700c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1500#define drive_pex_l1_clkreq_n_pa4 DRV_PINGROUP_ENTRY_Y(0x7014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1501#define drive_pex_l1_rst_n_pa3 DRV_PINGROUP_ENTRY_Y(0x701c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1502#define drive_pex_l0_clkreq_n_pa1 DRV_PINGROUP_ENTRY_Y(0x7024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1503#define drive_pex_l0_rst_n_pa0 DRV_PINGROUP_ENTRY_Y(0x702c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1504#define drive_pex_l2_rst_n_pa5 DRV_PINGROUP_ENTRY_Y(0x7034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1505#define drive_sdmmc1_clk_pd0 DRV_PINGROUP_ENTRY_Y(0x8004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1506#define drive_sdmmc1_cmd_pd1 DRV_PINGROUP_ENTRY_Y(0x800c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1507#define drive_sdmmc1_dat3_pd5 DRV_PINGROUP_ENTRY_Y(0x8018, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1508#define drive_sdmmc1_dat2_pd4 DRV_PINGROUP_ENTRY_Y(0x8020, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1509#define drive_sdmmc1_dat1_pd3 DRV_PINGROUP_ENTRY_Y(0x8028, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1510#define drive_sdmmc1_dat0_pd2 DRV_PINGROUP_ENTRY_Y(0x8030, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1511#define drive_eqos_td3_pe4 DRV_PINGROUP_ENTRY_Y(0x9004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1512#define drive_eqos_td2_pe3 DRV_PINGROUP_ENTRY_Y(0x900c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1513#define drive_eqos_td1_pe2 DRV_PINGROUP_ENTRY_Y(0x9014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1514#define drive_eqos_td0_pe1 DRV_PINGROUP_ENTRY_Y(0x901c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1515#define drive_eqos_rd3_pf1 DRV_PINGROUP_ENTRY_Y(0x9024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1516#define drive_eqos_rd2_pf0 DRV_PINGROUP_ENTRY_Y(0x902c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1517#define drive_eqos_rd1_pe7 DRV_PINGROUP_ENTRY_Y(0x9034, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1518#define drive_eqos_mdio_pf4 DRV_PINGROUP_ENTRY_Y(0x903c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1519#define drive_eqos_rd0_pe6 DRV_PINGROUP_ENTRY_Y(0x9044, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1520#define drive_eqos_mdc_pf5 DRV_PINGROUP_ENTRY_Y(0x904c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1521#define drive_eqos_txc_pe0 DRV_PINGROUP_ENTRY_Y(0x9058, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1522#define drive_eqos_rxc_pf3 DRV_PINGROUP_ENTRY_Y(0x9060, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1523#define drive_eqos_tx_ctl_pe5 DRV_PINGROUP_ENTRY_Y(0x9068, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1524#define drive_eqos_rx_ctl_pf2 DRV_PINGROUP_ENTRY_Y(0x9070, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1525#define drive_sdmmc3_dat3_pg5 DRV_PINGROUP_ENTRY_Y(0xa004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1526#define drive_sdmmc3_dat2_pg4 DRV_PINGROUP_ENTRY_Y(0xa00c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1527#define drive_sdmmc3_dat1_pg3 DRV_PINGROUP_ENTRY_Y(0xa014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1528#define drive_sdmmc3_dat0_pg2 DRV_PINGROUP_ENTRY_Y(0xa01c, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1529#define drive_sdmmc3_cmd_pg1 DRV_PINGROUP_ENTRY_Y(0xa028, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1530#define drive_sdmmc3_clk_pg0 DRV_PINGROUP_ENTRY_Y(0xa030, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1531#define drive_qspi_io3_pr4 DRV_PINGROUP_ENTRY_Y(0xB004, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1532#define drive_qspi_io2_pr3 DRV_PINGROUP_ENTRY_Y(0xB00C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1533#define drive_qspi_io1_pr2 DRV_PINGROUP_ENTRY_Y(0xB014, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1534#define drive_qspi_io0_pr1 DRV_PINGROUP_ENTRY_Y(0xB01C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1535#define drive_qspi_sck_pr0 DRV_PINGROUP_ENTRY_Y(0xB024, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1536#define drive_qspi_cs_n_pr5 DRV_PINGROUP_ENTRY_Y(0xB02C, -1, -1, -1, -1, 28, 2, 30, 2, 0)
1537#define drive_gpio_wan8_ph3 DRV_PINGROUP_ENTRY_Y(0xd004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1538#define drive_gpio_wan7_ph2 DRV_PINGROUP_ENTRY_Y(0xd00c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1539#define drive_gpio_wan6_ph1 DRV_PINGROUP_ENTRY_Y(0xd014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1540#define drive_gpio_wan5_ph0 DRV_PINGROUP_ENTRY_Y(0xd01c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1541#define drive_uart2_tx_px0 DRV_PINGROUP_ENTRY_Y(0xd024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1542#define drive_uart2_rx_px1 DRV_PINGROUP_ENTRY_Y(0xd02c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1543#define drive_uart2_rts_px2 DRV_PINGROUP_ENTRY_Y(0xd034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1544#define drive_uart2_cts_px3 DRV_PINGROUP_ENTRY_Y(0xd03c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1545#define drive_uart5_rx_px5 DRV_PINGROUP_ENTRY_Y(0xd044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1546#define drive_uart5_tx_px4 DRV_PINGROUP_ENTRY_Y(0xd04c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1547#define drive_uart5_rts_px6 DRV_PINGROUP_ENTRY_Y(0xd054, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1548#define drive_uart5_cts_px7 DRV_PINGROUP_ENTRY_Y(0xd05c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1549#define drive_gpio_mdm1_py0 DRV_PINGROUP_ENTRY_Y(0xd064, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1550#define drive_gpio_mdm2_py1 DRV_PINGROUP_ENTRY_Y(0xd06c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1551#define drive_gpio_mdm3_py2 DRV_PINGROUP_ENTRY_Y(0xd074, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1552#define drive_gpio_mdm4_py3 DRV_PINGROUP_ENTRY_Y(0xd07c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1553#define drive_gpio_mdm5_py4 DRV_PINGROUP_ENTRY_Y(0xd084, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1554#define drive_gpio_mdm6_py5 DRV_PINGROUP_ENTRY_Y(0xd08c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1555#define drive_gpio_mdm7_py6 DRV_PINGROUP_ENTRY_Y(0xd094, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1556#define drive_bcpu_pwr_req_ph4 DRV_PINGROUP_ENTRY_Y(0xd09c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1557#define drive_mcpu_pwr_req_ph5 DRV_PINGROUP_ENTRY_Y(0xd0a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1558#define drive_gpu_pwr_req_ph6 DRV_PINGROUP_ENTRY_Y(0xd0ac, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1559#define drive_gen7_i2c_scl_pl0 DRV_PINGROUP_ENTRY_Y(0xd0b4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1560#define drive_gen7_i2c_sda_pl1 DRV_PINGROUP_ENTRY_Y(0xd0bc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1561#define drive_gen9_i2c_sda_pl3 DRV_PINGROUP_ENTRY_Y(0xd0c4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1562#define drive_gen9_i2c_scl_pl2 DRV_PINGROUP_ENTRY_Y(0xd0cc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1563#define drive_usb_vbus_en0_pl4 DRV_PINGROUP_ENTRY_Y(0xd0d4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1564#define drive_usb_vbus_en1_pl5 DRV_PINGROUP_ENTRY_Y(0xd0dc, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1565#define drive_gp_pwm7_pl7 DRV_PINGROUP_ENTRY_Y(0xd0e4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1566#define drive_gp_pwm6_pl6 DRV_PINGROUP_ENTRY_Y(0xd0ec, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1567#define drive_ufs0_rst_pbb1 DRV_PINGROUP_ENTRY_Y(0x11004, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1568#define drive_ufs0_ref_clk_pbb0 DRV_PINGROUP_ENTRY_Y(0x1100c, 12, 9, 24, 8, -1, -1, -1, -1, 0)
1569
1570#define drive_directdc_comp DRV_PINGROUP_ENTRY_N(no_entry)
1571#define drive_sdmmc1_comp DRV_PINGROUP_ENTRY_N(no_entry)
1572#define drive_eqos_comp DRV_PINGROUP_ENTRY_N(no_entry)
1573#define drive_sdmmc3_comp DRV_PINGROUP_ENTRY_N(no_entry)
1574#define drive_sdmmc4_clk DRV_PINGROUP_ENTRY_N(no_entry)
1575#define drive_sdmmc4_cmd DRV_PINGROUP_ENTRY_N(no_entry)
1576#define drive_sdmmc4_dqs DRV_PINGROUP_ENTRY_N(no_entry)
1577#define drive_sdmmc4_dat7 DRV_PINGROUP_ENTRY_N(no_entry)
1578#define drive_sdmmc4_dat6 DRV_PINGROUP_ENTRY_N(no_entry)
1579#define drive_sdmmc4_dat5 DRV_PINGROUP_ENTRY_N(no_entry)
1580#define drive_sdmmc4_dat4 DRV_PINGROUP_ENTRY_N(no_entry)
1581#define drive_sdmmc4_dat3 DRV_PINGROUP_ENTRY_N(no_entry)
1582#define drive_sdmmc4_dat2 DRV_PINGROUP_ENTRY_N(no_entry)
1583#define drive_sdmmc4_dat1 DRV_PINGROUP_ENTRY_N(no_entry)
1584#define drive_sdmmc4_dat0 DRV_PINGROUP_ENTRY_N(no_entry)
1585#define drive_qspi_comp DRV_PINGROUP_ENTRY_N(no_entry)
1586
1587/* AON drive pin groups */
1588#define drive_touch_clk_pee2 DRV_PINGROUP_ENTRY_Y(0x2004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1589#define drive_uart3_cts_pw5 DRV_PINGROUP_ENTRY_Y(0x200c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1590#define drive_uart3_rts_pw4 DRV_PINGROUP_ENTRY_Y(0x2014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1591#define drive_uart3_rx_pw3 DRV_PINGROUP_ENTRY_Y(0x201c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1592#define drive_uart3_tx_pw2 DRV_PINGROUP_ENTRY_Y(0x2024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1593#define drive_gen8_i2c_sda_pw1 DRV_PINGROUP_ENTRY_Y(0x202c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1594#define drive_gen8_i2c_scl_pw0 DRV_PINGROUP_ENTRY_Y(0x2034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1595#define drive_uart7_rx_pw7 DRV_PINGROUP_ENTRY_Y(0x203c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1596#define drive_uart7_tx_pw6 DRV_PINGROUP_ENTRY_Y(0x2044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1597#define drive_gpio_sen0_pv0 DRV_PINGROUP_ENTRY_Y(0x204c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1598#define drive_gpio_sen1_pv1 DRV_PINGROUP_ENTRY_Y(0x2054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1599#define drive_gpio_sen2_pv2 DRV_PINGROUP_ENTRY_Y(0x205c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1600#define drive_gpio_sen3_pv3 DRV_PINGROUP_ENTRY_Y(0x2064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1601#define drive_gpio_sen4_pv4 DRV_PINGROUP_ENTRY_Y(0x206c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1602#define drive_gpio_sen5_pv5 DRV_PINGROUP_ENTRY_Y(0x2074, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1603#define drive_gpio_sen6_pv6 DRV_PINGROUP_ENTRY_Y(0x207c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1604#define drive_gpio_sen7_pv7 DRV_PINGROUP_ENTRY_Y(0x2084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1605#define drive_gpio_sen8_pee0 DRV_PINGROUP_ENTRY_Y(0x208c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1606#define drive_gpio_sen9_pee1 DRV_PINGROUP_ENTRY_Y(0x2094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1607#define drive_can_gpio7_paa7 DRV_PINGROUP_ENTRY_Y(0x3004, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1608#define drive_can1_dout_pz0 DRV_PINGROUP_ENTRY_Y(0x300C, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1609#define drive_can1_din_pz1 DRV_PINGROUP_ENTRY_Y(0x3014, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1610#define drive_can0_dout_pz2 DRV_PINGROUP_ENTRY_Y(0x301c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1611#define drive_can0_din_pz3 DRV_PINGROUP_ENTRY_Y(0x3024, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1612#define drive_can_gpio0_paa0 DRV_PINGROUP_ENTRY_Y(0x302c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1613#define drive_can_gpio1_paa1 DRV_PINGROUP_ENTRY_Y(0x3034, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1614#define drive_can_gpio2_paa2 DRV_PINGROUP_ENTRY_Y(0x303c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1615#define drive_can_gpio3_paa3 DRV_PINGROUP_ENTRY_Y(0x3044, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1616#define drive_can_gpio4_paa4 DRV_PINGROUP_ENTRY_Y(0x304c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1617#define drive_can_gpio5_paa5 DRV_PINGROUP_ENTRY_Y(0x3054, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1618#define drive_can_gpio6_paa6 DRV_PINGROUP_ENTRY_Y(0x305c, -1, -1, -1, -1, 28, 2, 30, 2, 1)
1619#define drive_gpio_sw1_pff1 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1620#define drive_gpio_sw2_pff2 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1621#define drive_gpio_sw3_pff3 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1622#define drive_gpio_sw4_pff4 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1623#define drive_shutdown DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1624#define drive_pmu_int DRV_PINGROUP_ENTRY_Y(0x102C, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1625#define drive_safe_state_ps3 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1626#define drive_vcomp_alert_ps4 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1627#define drive_soc_pwr_req DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1628#define drive_batt_oc_ps2 DRV_PINGROUP_ENTRY_Y(0x104c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1629#define drive_clk_32k_in DRV_PINGROUP_ENTRY_Y(0x1054, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1630#define drive_power_on_pff0 DRV_PINGROUP_ENTRY_Y(0x105c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1631#define drive_pwr_i2c_scl_ps0 DRV_PINGROUP_ENTRY_Y(0x1064, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1632#define drive_pwr_i2c_sda_ps1 DRV_PINGROUP_ENTRY_Y(0x106c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1633#define drive_gpio_dis0_pu0 DRV_PINGROUP_ENTRY_Y(0x1084, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1634#define drive_gpio_dis1_pu1 DRV_PINGROUP_ENTRY_Y(0x108c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1635#define drive_gpio_dis2_pu2 DRV_PINGROUP_ENTRY_Y(0x1094, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1636#define drive_gpio_dis3_pu3 DRV_PINGROUP_ENTRY_Y(0x109c, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1637#define drive_gpio_dis4_pu4 DRV_PINGROUP_ENTRY_Y(0x10a4, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1638#define drive_gpio_dis5_pu5 DRV_PINGROUP_ENTRY_Y(0x10ac, 12, 5, 20, 5, -1, -1, -1, -1, 1)
1639
1640#define PINGROUP(pg_name, f0, f1, f2, f3, r, bank, pupd, e_io_hv, e_lpbk, e_input, e_lpdr, e_pbias_buf, \
1641 gpio_sfio_sel, e_od, schmitt_b, drvtype, epreemp, io_reset, rfu_in) \
1642 { \
1643 .name = #pg_name, \
1644 .pins = pg_name##_pins, \
1645 .npins = ARRAY_SIZE(pg_name##_pins), \
1646 .funcs = { \
1647 TEGRA_MUX_##f0, \
1648 TEGRA_MUX_##f1, \
1649 TEGRA_MUX_##f2, \
1650 TEGRA_MUX_##f3, \
1651 }, \
1652 PIN_PINGROUP_ENTRY_Y(r, bank, pupd, e_io_hv, e_lpbk, \
1653 e_input, e_lpdr, e_pbias_buf, \
1654 gpio_sfio_sel, e_od, \
1655 schmitt_b, drvtype, \
1656 epreemp, io_reset, \
1657 rfu_in) \
1658 drive_##pg_name, \
1659 }
1660
1661static const struct tegra_pingroup tegra186_groups[] = {
1662 PINGROUP(gpio_aud3_pk0, RSVD0, DSPK1, SPDIF, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1663 PINGROUP(gpio_aud2_pj7, RSVD0, DSPK1, SPDIF, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1664 PINGROUP(gpio_aud1_pj6, RSVD0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1665 PINGROUP(gpio_aud0_pj5, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1666 PINGROUP(aud_mclk_pj4, AUD, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1667 PINGROUP(dap1_fs_pj3, I2S1, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1668 PINGROUP(dap1_din_pj2, I2S1, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1669 PINGROUP(dap1_dout_pj1, I2S1, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1670 PINGROUP(dap1_sclk_pj0, I2S1, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1671 PINGROUP(dmic1_clk_pm1, DMIC1, I2S3, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1672 PINGROUP(dmic1_dat_pm0, DMIC1, I2S3, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1673 PINGROUP(dmic2_dat_pm2, DMIC2, I2S3, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1674 PINGROUP(dmic2_clk_pm3, DMIC2, I2S3, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1675 PINGROUP(dmic4_dat_pm4, DMIC4, DSPK0, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1676 PINGROUP(dmic4_clk_pm5, DMIC4, DSPK0, RSVD2, RSVD3, 0x2028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1677 PINGROUP(dap4_fs_pcc3, I2S4, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1678 PINGROUP(dap4_din_pcc2, I2S4, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1679 PINGROUP(dap4_dout_pcc1, I2S4, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1680 PINGROUP(dap4_sclk_pcc0, I2S4, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1681 PINGROUP(extperiph2_clk_po1, EXTPERIPH2, RSVD1, RSVD2, RSVD3, 0x0000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1682 PINGROUP(extperiph1_clk_po0, EXTPERIPH1, RSVD1, RSVD2, RSVD3, 0x0008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1683 PINGROUP(cam_i2c_sda_po3, I2C3, RSVD1, RSVD2, RSVD3, 0x0010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1684 PINGROUP(cam_i2c_scl_po2, I2C3, RSVD1, RSVD2, RSVD3, 0x0018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1685 PINGROUP(gpio_cam1_pn0, VGP1, RSVD1, RSVD2, RSVD3, 0x0020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1686 PINGROUP(gpio_cam2_pn1, VGP2, EXTPERIPH3, RSVD2, RSVD3, 0x0028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1687 PINGROUP(gpio_cam3_pn2, VGP3, EXTPERIPH4, RSVD2, RSVD3, 0x0030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1688 PINGROUP(gpio_cam4_pn3, VGP4, SPI4, RSVD2, RSVD3, 0x0038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1689 PINGROUP(gpio_cam5_pn4, VGP5, SPI4, RSVD2, RSVD3, 0x0040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1690 PINGROUP(gpio_cam6_pn5, VGP6, SPI4, RSVD2, RSVD3, 0x0048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1691 PINGROUP(gpio_cam7_pn6, RSVD0, SPI4, RSVD2, RSVD3, 0x0050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1692 PINGROUP(dap2_din_pc3, I2S2, RSVD1, RSVD2, RSVD3, 0x4000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1693 PINGROUP(dap2_dout_pc2, I2S2, RSVD1, RSVD2, RSVD3, 0x4008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1694 PINGROUP(dap2_fs_pc4, I2S2, RSVD1, RSVD2, RSVD3, 0x4010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1695 PINGROUP(dap2_sclk_pc1, I2S2, RSVD1, RSVD2, RSVD3, 0x4018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1696 PINGROUP(uart4_cts_pb3, UARTD, RSVD1, RSVD2, RSVD3, 0x4020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1697 PINGROUP(uart4_rts_pb2, UARTD, RSVD1, RSVD2, RSVD3, 0x4028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1698 PINGROUP(uart4_rx_pb1, UARTD, RSVD1, RSVD2, RSVD3, 0x4030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1699 PINGROUP(uart4_tx_pb0, UARTD, RSVD1, RSVD2, RSVD3, 0x4038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1700 PINGROUP(gpio_wan4_pc0, RSVD0, RSVD1, RSVD2, RSVD3, 0x4040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1701 PINGROUP(gpio_wan3_pb6, RSVD0, RSVD1, RSVD2, RSVD3, 0x4048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1702 PINGROUP(gpio_wan2_pb5, RSVD0, RSVD1, RSVD2, RSVD3, 0x4050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1703 PINGROUP(gpio_wan1_pb4, RSVD0, RSVD1, RSVD2, RSVD3, 0x4058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1704 PINGROUP(gen1_i2c_scl_pc5, I2C1, RSVD1, RSVD2, RSVD3, 0x4060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1705 PINGROUP(gen1_i2c_sda_pc6, I2C1, RSVD1, RSVD2, RSVD3, 0x4068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1706 PINGROUP(uart1_cts_pt3, UARTA, RSVD1, RSVD2, RSVD3, 0x5000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1707 PINGROUP(uart1_rts_pt2, UARTA, RSVD1, RSVD2, RSVD3, 0x5008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1708 PINGROUP(uart1_rx_pt1, UARTA, RSVD1, RSVD2, RSVD3, 0x5010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1709 PINGROUP(uart1_tx_pt0, UARTA, RSVD1, RSVD2, RSVD3, 0x5018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1710 PINGROUP(directdc1_out3_pq5, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1711 PINGROUP(directdc1_out2_pq4, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1712 PINGROUP(directdc1_out1_pq3, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1713 PINGROUP(directdc1_out0_pq2, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1714 PINGROUP(directdc1_in_pq1, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1715 PINGROUP(directdc1_clk_pq0, DIRECTDC1, RSVD1, RSVD2, RSVD3, 0x5050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1716 PINGROUP(directdc_comp, DIRECTDC, RSVD1, RSVD2, RSVD3, 0x5058, 0, Y, -1, -1, -1, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1717 PINGROUP(gpio_pq0_pi0, RSVD0, IQC0, I2S6, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1718 PINGROUP(gpio_pq1_pi1, RSVD0, IQC0, I2S6, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1719 PINGROUP(gpio_pq2_pi2, RSVD0, IQC0, I2S6, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1720 PINGROUP(gpio_pq3_pi3, RSVD0, IQC0, I2S6, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1721 PINGROUP(gpio_pq4_pi4, RSVD0, IQC1, DTV, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1722 PINGROUP(gpio_pq5_pi5, RSVD0, IQC1, DTV, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1723 PINGROUP(gpio_pq6_pi6, RSVD0, IQC1, DTV, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1724 PINGROUP(gpio_pq7_pi7, RSVD0, IQC1, DTV, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1725 PINGROUP(gpio_edp2_pp5, RSVD0, UARTF, SDMMC3, RSVD3, 0x10000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1726 PINGROUP(gpio_edp3_pp6, RSVD0, UARTF, SDMMC1, RSVD3, 0x10008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1727 PINGROUP(gpio_edp0_pp3, RSVD0, UARTF, SDMMC3, RSVD3, 0x10010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1728 PINGROUP(gpio_edp1_pp4, RSVD0, UARTF, SDMMC1, RSVD3, 0x10018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1729 PINGROUP(dp_aux_ch0_hpd_pp0, DP, RSVD1, RSVD2, RSVD3, 0x10020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1730 PINGROUP(dp_aux_ch1_hpd_pp1, DP, RSVD1, RSVD2, RSVD3, 0x10028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1731 PINGROUP(hdmi_cec_pp2, HDMI, RSVD1, RSVD2, RSVD3, 0x10030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1732 PINGROUP(pex_l2_clkreq_n_pa6, PE2, GP, SATA, RSVD3, 0x7000, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1733 PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x7008, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1734 PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x7010, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1735 PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x7018, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1736 PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x7020, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1737 PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x7028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1738 PINGROUP(pex_l2_rst_n_pa5, PE2, SOC, SATA, RSVD3, 0x7030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1739 PINGROUP(sdmmc1_clk_pd0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8000, 0, Y, 5, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1740 PINGROUP(sdmmc1_cmd_pd1, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1741 PINGROUP(sdmmc1_comp, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8010, 0, Y, -1, -1, 6, -1, -1, -1, -1, -1, N, -1, -1, N),
1742 PINGROUP(sdmmc1_dat3_pd5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8014, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1743 PINGROUP(sdmmc1_dat2_pd4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x801c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1744 PINGROUP(sdmmc1_dat1_pd3, SDMMC1, RSVD1, RSVD2, RSVD3, 0x8024, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1745 PINGROUP(sdmmc1_dat0_pd2, SDMMC1, RSVD1, RSVD2, RSVD3, 0x802c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1746 PINGROUP(eqos_td3_pe4, EQOS, SDMMC2, RSVD2, RSVD3, 0x9000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1747 PINGROUP(eqos_td2_pe3, EQOS, SDMMC2, RSVD2, RSVD3, 0x9008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1748 PINGROUP(eqos_td1_pe2, EQOS, SDMMC2, RSVD2, RSVD3, 0x9010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1749 PINGROUP(eqos_td0_pe1, EQOS, SDMMC2, RSVD2, RSVD3, 0x9018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1750 PINGROUP(eqos_rd3_pf1, EQOS, SDMMC2, RSVD2, RSVD3, 0x9020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1751 PINGROUP(eqos_rd2_pf0, EQOS, SDMMC2, RSVD2, RSVD3, 0x9028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1752 PINGROUP(eqos_rd1_pe7, EQOS, SDMMC2, RSVD2, RSVD3, 0x9030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1753 PINGROUP(eqos_mdio_pf4, EQOS, SOC, RSVD2, RSVD3, 0x9038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1754 PINGROUP(eqos_rd0_pe6, EQOS, SDMMC2, RSVD2, RSVD3, 0x9040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1755 PINGROUP(eqos_mdc_pf5, EQOS, RSVD1, RSVD2, RSVD3, 0x9048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1756 PINGROUP(eqos_comp, EQOS, SDMMC2, RSVD2, RSVD3, 0x9050, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N),
1757 PINGROUP(eqos_txc_pe0, EQOS, SDMMC2, RSVD2, RSVD3, 0x9054, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1758 PINGROUP(eqos_rxc_pf3, EQOS, SDMMC2, RSVD2, RSVD3, 0x905c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1759 PINGROUP(eqos_tx_ctl_pe5, EQOS, SDMMC2, RSVD2, RSVD3, 0x9064, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1760 PINGROUP(eqos_rx_ctl_pf2, EQOS, SDMMC2, RSVD2, RSVD3, 0x906c, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1761 PINGROUP(sdmmc3_dat3_pg5, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1762 PINGROUP(sdmmc3_dat2_pg4, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1763 PINGROUP(sdmmc3_dat1_pg3, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1764 PINGROUP(sdmmc3_dat0_pg2, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1765 PINGROUP(sdmmc3_comp, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa020, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, N, -1, -1, N),
1766 PINGROUP(sdmmc3_cmd_pg1, SDMMC3, RSVD1, RSVD2, RSVD3, 0xa024, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1767 PINGROUP(sdmmc3_clk_pg0, SDMMC3, RSVD1, RSVD1, RSVD3, 0xa02c, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1768 PINGROUP(sdmmc4_clk, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6004, 0, Y, -1, 5, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1769 PINGROUP(sdmmc4_cmd, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6008, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1770 PINGROUP(sdmmc4_dqs, SDMMC4, RSVD1, RSVD2, RSVD3, 0x600c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1771 PINGROUP(sdmmc4_dat7, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6010, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1772 PINGROUP(sdmmc4_dat6, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6014, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1773 PINGROUP(sdmmc4_dat5, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1774 PINGROUP(sdmmc4_dat4, SDMMC4, RSVD1, RSVD2, RSVD3, 0x601c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1775 PINGROUP(sdmmc4_dat3, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6020, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1776 PINGROUP(sdmmc4_dat2, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6024, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1777 PINGROUP(sdmmc4_dat1, SDMMC4, RSVD1, RSVD2, RSVD3, 0x6028, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1778 PINGROUP(sdmmc4_dat0, SDMMC4, RSVD1, RSVD2, RSVD3, 0x602c, 0, Y, -1, -1, 6, -1, 9, -1, -1, 12, Y, -1, -1, Y),
1779 PINGROUP(qspi_io3_pr4, QSPI, RSVD1, RSVD2, RSVD3, 0xB000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1780 PINGROUP(qspi_io2_pr3, QSPI, RSVD1, RSVD2, RSVD3, 0xB008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1781 PINGROUP(qspi_io1_pr2, QSPI, RSVD1, RSVD2, RSVD3, 0xB010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1782 PINGROUP(qspi_io0_pr1, QSPI, RSVD1, RSVD2, RSVD3, 0xB018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1783 PINGROUP(qspi_sck_pr0, QSPI, RSVD1, RSVD2, RSVD3, 0xB020, 0, Y, -1, 5, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1784 PINGROUP(qspi_cs_n_pr5, QSPI, RSVD1, RSVD2, RSVD3, 0xB028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1785 PINGROUP(qspi_comp, QSPI, RSVD1, RSVD2, RSVD3, 0xB030, 0, Y, -1, -1, -1, -1, -1, -1, -1, -1, Y, -1, -1, Y),
1786 PINGROUP(gpio_wan8_ph3, RSVD0, RSVD1, SPI1, RSVD3, 0xd000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1787 PINGROUP(gpio_wan7_ph2, RSVD0, RSVD1, SPI1, RSVD3, 0xd008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1788 PINGROUP(gpio_wan6_ph1, RSVD0, RSVD1, SPI1, RSVD3, 0xd010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1789 PINGROUP(gpio_wan5_ph0, RSVD0, RSVD1, SPI1, RSVD3, 0xd018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1790 PINGROUP(uart2_tx_px0, UARTB, RSVD1, RSVD2, RSVD3, 0xd020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1791 PINGROUP(uart2_rx_px1, UARTB, RSVD1, RSVD2, RSVD3, 0xd028, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1792 PINGROUP(uart2_rts_px2, UARTB, RSVD1, RSVD2, RSVD3, 0xd030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1793 PINGROUP(uart2_cts_px3, UARTB, RSVD1, RSVD2, RSVD3, 0xd038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1794 PINGROUP(uart5_rx_px5, UARTE, SPI3, GP, RSVD3, 0xd040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1795 PINGROUP(uart5_tx_px4, UARTE, SPI3, NV, RSVD3, 0xd048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1796 PINGROUP(uart5_rts_px6, UARTE, SPI3, RSVD2, RSVD3, 0xd050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1797 PINGROUP(uart5_cts_px7, UARTE, SPI3, RSVD2, RSVD3, 0xd058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1798 PINGROUP(gpio_mdm1_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0xd060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1799 PINGROUP(gpio_mdm2_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0xd068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1800 PINGROUP(gpio_mdm3_py2, RSVD0, RSVD1, RSVD2, RSVD3, 0xd070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1801 PINGROUP(gpio_mdm4_py3, RSVD0, SPI1, CCLA, RSVD3, 0xd078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1802 PINGROUP(gpio_mdm5_py4, RSVD0, SPI1, RSVD2, RSVD3, 0xd080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1803 PINGROUP(gpio_mdm6_py5, SOC, RSVD1, RSVD2, RSVD3, 0xd088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1804 PINGROUP(gpio_mdm7_py6, RSVD0, RSVD1, RSVD2, RSVD3, 0xd090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1805 PINGROUP(bcpu_pwr_req_ph4, RSVD0, RSVD1, RSVD2, RSVD3, 0xd098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1806 PINGROUP(mcpu_pwr_req_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0xd0a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1807 PINGROUP(gpu_pwr_req_ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0xd0a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1808 PINGROUP(gen7_i2c_scl_pl0, I2C7, I2S5, RSVD2, RSVD3, 0xd0b0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1809 PINGROUP(gen7_i2c_sda_pl1, I2C7, I2S5, RSVD2, RSVD3, 0xd0b8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1810 PINGROUP(gen9_i2c_sda_pl3, I2C9, I2S5, RSVD2, RSVD3, 0xd0c0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1811 PINGROUP(gen9_i2c_scl_pl2, I2C9, I2S5, RSVD2, RSVD3, 0xd0c8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1812 PINGROUP(usb_vbus_en0_pl4, USB, RSVD1, RSVD2, RSVD3, 0xd0d0, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1813 PINGROUP(usb_vbus_en1_pl5, USB, RSVD1, RSVD2, RSVD3, 0xd0d8, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1814 PINGROUP(gp_pwm7_pl7, GP, RSVD1, RSVD2, RSVD3, 0xd0e0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1815 PINGROUP(gp_pwm6_pl6, GP, RSVD1, RSVD2, RSVD3, 0xd0e8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1816 PINGROUP(ufs0_rst_pbb1, UFS0, RSVD1, RSVD2, RSVD3, 0x11000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1817 PINGROUP(ufs0_ref_clk_pbb0, UFS0, RSVD1, RSVD2, RSVD3, 0x11008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, 15, 17, Y),
1818};
1819
1820static const struct tegra_pinctrl_soc_data tegra186_pinctrl = {
1821 .pins = tegra186_pins,
1822 .npins = ARRAY_SIZE(tegra186_pins),
1823 .functions = tegra186_functions,
1824 .nfunctions = ARRAY_SIZE(tegra186_functions),
1825 .groups = tegra186_groups,
1826 .ngroups = ARRAY_SIZE(tegra186_groups),
1827 .hsm_in_mux = false,
1828 .schmitt_in_mux = true,
1829 .drvtype_in_mux = true,
1830 .sfsel_in_mux = true,
1831};
1832
1833static const struct pinctrl_pin_desc tegra186_aon_pins[] = {
1834 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PS0, "PWR_I2C_SCL_PS0"),
1835 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PS1, "PWR_I2C_SDA_PS1"),
1836 PINCTRL_PIN(TEGRA_PIN_BATT_OC_PS2, "BATT_OC_PS2"),
1837 PINCTRL_PIN(TEGRA_PIN_SAFE_STATE_PS3, "SAFE_STATE_PS3"),
1838 PINCTRL_PIN(TEGRA_PIN_VCOMP_ALERT_PS4, "VCOMP_ALERT_PS4"),
1839 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS0_PU0, "GPIO_DIS0_PU0"),
1840 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS1_PU1, "GPIO_DIS1_PU1"),
1841 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS2_PU2, "GPIO_DIS2_PU2"),
1842 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS3_PU3, "GPIO_DIS3_PU3"),
1843 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS4_PU4, "GPIO_DIS4_PU4"),
1844 PINCTRL_PIN(TEGRA_PIN_GPIO_DIS5_PU5, "GPIO_DIS5_PU5"),
1845 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN0_PV0, "GPIO_SEN0_PV0"),
1846 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN1_PV1, "GPIO_SEN1_PV1"),
1847 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN2_PV2, "GPIO_SEN2_PV2"),
1848 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN3_PV3, "GPIO_SEN3_PV3"),
1849 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN4_PV4, "GPIO_SEN4_PV4"),
1850 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN5_PV5, "GPIO_SEN5_PV5"),
1851 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN6_PV6, "GPIO_SEN6_PV6"),
1852 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN7_PV7, "GPIO_SEN7_PV7"),
1853 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SCL_PW0, "GEN8_I2C_SCL_PW0"),
1854 PINCTRL_PIN(TEGRA_PIN_GEN8_I2C_SDA_PW1, "GEN8_I2C_SDA_PW1"),
1855 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PW2, "UART3_TX_PW2"),
1856 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PW3, "UART3_RX_PW3"),
1857 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PW4, "UART3_RTS_PW4"),
1858 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PW5, "UART3_CTS_PW5"),
1859 PINCTRL_PIN(TEGRA_PIN_UART7_TX_PW6, "UART7_TX_PW6"),
1860 PINCTRL_PIN(TEGRA_PIN_UART7_RX_PW7, "UART7_RX_PW7"),
1861 PINCTRL_PIN(TEGRA_PIN_CAN1_DOUT_PZ0, "CAN1_DOUT_PZ0"),
1862 PINCTRL_PIN(TEGRA_PIN_CAN1_DIN_PZ1, "CAN1_DIN_PZ1"),
1863 PINCTRL_PIN(TEGRA_PIN_CAN0_DOUT_PZ2, "CAN0_DOUT_PZ2"),
1864 PINCTRL_PIN(TEGRA_PIN_CAN0_DIN_PZ3, "CAN0_DIN_PZ3"),
1865 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO0_PAA0, "CAN_GPIO0_PAA0"),
1866 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO1_PAA1, "CAN_GPIO1_PAA1"),
1867 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO2_PAA2, "CAN_GPIO2_PAA2"),
1868 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO3_PAA3, "CAN_GPIO3_PAA3"),
1869 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO4_PAA4, "CAN_GPIO4_PAA4"),
1870 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO5_PAA5, "CAN_GPIO5_PAA5"),
1871 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO6_PAA6, "CAN_GPIO6_PAA6"),
1872 PINCTRL_PIN(TEGRA_PIN_CAN_GPIO7_PAA7, "CAN_GPIO7_PAA7"),
1873 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN8_PEE0, "GPIO_SEN8_PEE0"),
1874 PINCTRL_PIN(TEGRA_PIN_GPIO_SEN9_PEE1, "GPIO_SEN9_PEE1"),
1875 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PEE2, "TOUCH_CLK_PEE2"),
1876 PINCTRL_PIN(TEGRA_PIN_POWER_ON_PFF0, "POWER_ON_PFF0"),
1877 PINCTRL_PIN(TEGRA_PIN_GPIO_SW1_PFF1, "GPIO_SW1_PFF1"),
1878 PINCTRL_PIN(TEGRA_PIN_GPIO_SW2_PFF2, "GPIO_SW2_PFF2"),
1879 PINCTRL_PIN(TEGRA_PIN_GPIO_SW3_PFF3, "GPIO_SW3_PFF3"),
1880 PINCTRL_PIN(TEGRA_PIN_GPIO_SW4_PFF4, "GPIO_SW4_PFF4"),
1881 PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
1882 PINCTRL_PIN(TEGRA_PIN_PMU_INT, "PMU_INT"),
1883 PINCTRL_PIN(TEGRA_PIN_SOC_PWR_REQ, "SOC_PWR_REQ"),
1884 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
1885};
1886
1887static const struct tegra_pingroup tegra186_aon_groups[] = {
1888 PINGROUP(touch_clk_pee2, TOUCH, RSVD1, RSVD2, RSVD3, 0x2000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1889 PINGROUP(uart3_cts_pw5, UARTC, RSVD1, RSVD2, RSVD3, 0x2008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1890 PINGROUP(uart3_rts_pw4, UARTC, RSVD1, RSVD2, RSVD3, 0x2010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1891 PINGROUP(uart3_rx_pw3, UARTC, RSVD1, RSVD2, RSVD3, 0x2018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1892 PINGROUP(uart3_tx_pw2, UARTC, RSVD1, RSVD2, RSVD3, 0x2020, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1893 PINGROUP(gen8_i2c_sda_pw1, I2C8, RSVD1, RSVD2, RSVD3, 0x2028, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1894 PINGROUP(gen8_i2c_scl_pw0, I2C8, RSVD1, RSVD2, RSVD3, 0x2030, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1895 PINGROUP(uart7_rx_pw7, UARTG, RSVD1, RSVD2, RSVD3, 0x2038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1896 PINGROUP(uart7_tx_pw6, UARTG, RSVD1, RSVD2, RSVD3, 0x2040, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1897 PINGROUP(gpio_sen0_pv0, RSVD0, RSVD1, RSVD2, RSVD3, 0x2048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1898 PINGROUP(gpio_sen1_pv1, SPI2, RSVD1, RSVD2, RSVD3, 0x2050, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1899 PINGROUP(gpio_sen2_pv2, SPI2, RSVD1, RSVD2, RSVD3, 0x2058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1900 PINGROUP(gpio_sen3_pv3, SPI2, RSVD1, RSVD2, RSVD3, 0x2060, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1901 PINGROUP(gpio_sen4_pv4, SPI2, RSVD1, RSVD2, RSVD3, 0x2068, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1902 PINGROUP(gpio_sen5_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x2070, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1903 PINGROUP(gpio_sen6_pv6, RSVD0, GP, RSVD2, RSVD3, 0x2078, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1904 PINGROUP(gpio_sen7_pv7, RSVD0, WDT, RSVD2, RSVD3, 0x2080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1905 PINGROUP(gpio_sen8_pee0, RSVD0, I2C2, RSVD2, RSVD3, 0x2088, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1906 PINGROUP(gpio_sen9_pee1, RSVD0, I2C2, RSVD2, RSVD3, 0x2090, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1907 PINGROUP(can_gpio7_paa7, RSVD0, WDT, RSVD2, RSVD3, 0x3000, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1908 PINGROUP(can1_dout_pz0, CAN1, RSVD1, RSVD2, RSVD3, 0x3008, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1909 PINGROUP(can1_din_pz1, CAN1, RSVD1, RSVD2, RSVD3, 0x3010, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1910 PINGROUP(can0_dout_pz2, CAN0, RSVD1, RSVD2, RSVD3, 0x3018, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1911 PINGROUP(can0_din_pz3, CAN0, RSVD1, RSVD2, RSVD3, 0x3020, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1912 PINGROUP(can_gpio0_paa0, RSVD0, DMIC3, DMIC5, RSVD3, 0x3028, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1913 PINGROUP(can_gpio1_paa1, RSVD0, DMIC3, DMIC5, RSVD3, 0x3030, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1914 PINGROUP(can_gpio2_paa2, GPIO, RSVD1, RSVD2, RSVD3, 0x3038, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1915 PINGROUP(can_gpio3_paa3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3040, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1916 PINGROUP(can_gpio4_paa4, RSVD0, RSVD1, RSVD2, RSVD3, 0x3048, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1917 PINGROUP(can_gpio5_paa5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3050, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1918 PINGROUP(can_gpio6_paa6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3058, 0, Y, -1, -1, 6, -1, 9, 10, -1, 12, Y, -1, -1, Y),
1919 PINGROUP(gpio_sw1_pff1, RSVD0, RSVD1, RSVD2, RSVD3, 0x1000, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1920 PINGROUP(gpio_sw2_pff2, RSVD0, RSVD1, RSVD2, RSVD3, 0x1008, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1921 PINGROUP(gpio_sw3_pff3, RSVD0, RSVD1, RSVD2, RSVD3, 0x1010, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1922 PINGROUP(gpio_sw4_pff4, RSVD0, RSVD1, RSVD2, RSVD3, 0x1018, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1923 PINGROUP(shutdown, RSVD0, RSVD1, RSVD2, RSVD3, 0x1020, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1924 PINGROUP(pmu_int, RSVD0, RSVD1, RSVD2, RSVD3, 0x1028, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1925 PINGROUP(safe_state_ps3, SCE, RSVD1, RSVD2, RSVD3, 0x1030, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1926 PINGROUP(vcomp_alert_ps4, SOC, RSVD1, RSVD2, RSVD3, 0x1038, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1927 PINGROUP(soc_pwr_req, RSVD0, RSVD1, RSVD2, RSVD3, 0x1040, 0, Y, -1, -1, 6, 8, -1, -1, -1, 12, N, -1, -1, N),
1928 PINGROUP(batt_oc_ps2, SOC, RSVD1, RSVD2, RSVD3, 0x1048, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1929 PINGROUP(clk_32k_in, RSVD0, RSVD1, RSVD2, RSVD3, 0x1050, 0, Y, -1, -1, 6, 8, -1, -1, -1, -1, N, -1, -1, N),
1930 PINGROUP(power_on_pff0, RSVD0, RSVD1, RSVD2, RSVD3, 0x1058, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1931 PINGROUP(pwr_i2c_scl_ps0, I2C5, RSVD1, RSVD2, RSVD3, 0x1060, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1932 PINGROUP(pwr_i2c_sda_ps1, I2C5, RSVD1, RSVD2, RSVD3, 0x1068, 0, Y, 5, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1933 PINGROUP(gpio_dis0_pu0, RSVD0, GP, DCB, DCC, 0x1080, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1934 PINGROUP(gpio_dis1_pu1, RSVD0, RSVD1, DISPLAYA, RSVD3, 0x1088, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1935 PINGROUP(gpio_dis2_pu2, RSVD0, GP, DCA, RSVD3, 0x1090, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1936 PINGROUP(gpio_dis3_pu3, RSVD0, RSVD1, DISPLAYB, DCC, 0x1098, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1937 PINGROUP(gpio_dis4_pu4, RSVD0, SOC, DCA, RSVD3, 0x10a0, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1938 PINGROUP(gpio_dis5_pu5, RSVD0, GP, DCC, DCB, 0x10a8, 0, Y, -1, -1, 6, 8, -1, 10, 11, 12, N, -1, -1, N),
1939};
1940
1941static const struct tegra_pinctrl_soc_data tegra186_pinctrl_aon = {
1942 .pins = tegra186_aon_pins,
1943 .npins = ARRAY_SIZE(tegra186_aon_pins),
1944 .functions = tegra186_functions,
1945 .nfunctions = ARRAY_SIZE(tegra186_functions),
1946 .groups = tegra186_aon_groups,
1947 .ngroups = ARRAY_SIZE(tegra186_aon_groups),
1948 .hsm_in_mux = false,
1949 .schmitt_in_mux = true,
1950 .drvtype_in_mux = true,
1951 .sfsel_in_mux = true,
1952};
1953
1954static int tegra186_pinctrl_probe(struct platform_device *pdev)
1955{
1956 const struct tegra_pinctrl_soc_data *soc = of_device_get_match_data(&pdev->dev);
1957
1958 return tegra_pinctrl_probe(pdev, soc);
1959}
1960
1961static const struct of_device_id tegra186_pinctrl_of_match[] = {
1962 { .compatible = "nvidia,tegra186-pinmux", .data = &tegra186_pinctrl },
1963 { .compatible = "nvidia,tegra186-pinmux-aon", .data = &tegra186_pinctrl_aon },
1964 { },
1965};
1966
1967static struct platform_driver tegra186_pinctrl_driver = {
1968 .driver = {
1969 .name = "tegra186-pinctrl",
1970 .of_match_table = tegra186_pinctrl_of_match,
1971 },
1972 .probe = tegra186_pinctrl_probe,
1973};
1974
1975static int __init tegra186_pinctrl_init(void)
1976{
1977 return platform_driver_register(&tegra186_pinctrl_driver);
1978}
1979arch_initcall(tegra186_pinctrl_init);