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1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
4 *
5 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
7 * Copyright (c) 2012 Linaro Ltd
8 * http://www.linaro.org
9 *
10 * This file contains the Exynos specific definitions for the Samsung
11 * pinctrl/gpiolib interface drivers.
12 *
13 * Author: Thomas Abraham <thomas.ab@samsung.com>
14 */
15
16#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
17#define __PINCTRL_SAMSUNG_EXYNOS_H
18
19/* Values for the pin CON register */
20#define EXYNOS_PIN_CON_FUNC_EINT 0xf
21
22/* External GPIO and wakeup interrupt related definitions */
23#define EXYNOS_GPIO_ECON_OFFSET 0x700
24#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
25#define EXYNOS_GPIO_EMASK_OFFSET 0x900
26#define EXYNOS_GPIO_EPEND_OFFSET 0xA00
27#define EXYNOS_WKUP_ECON_OFFSET 0xE00
28#define EXYNOS_WKUP_EMASK_OFFSET 0xF00
29#define EXYNOS_WKUP_EPEND_OFFSET 0xF40
30#define EXYNOS7_WKUP_ECON_OFFSET 0x700
31#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
32#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
33#define EXYNOS_SVC_OFFSET 0xB08
34#define EXYNOSAUTO_SVC_OFFSET 0xF008
35
36/* helpers to access interrupt service register */
37#define EXYNOS_SVC_GROUP_SHIFT 3
38#define EXYNOS_SVC_GROUP_MASK 0x1f
39#define EXYNOS_SVC_NUM_MASK 7
40#define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
41 EXYNOS_SVC_GROUP_MASK)
42
43/* Exynos specific external interrupt trigger types */
44#define EXYNOS_EINT_LEVEL_LOW 0
45#define EXYNOS_EINT_LEVEL_HIGH 1
46#define EXYNOS_EINT_EDGE_FALLING 2
47#define EXYNOS_EINT_EDGE_RISING 3
48#define EXYNOS_EINT_EDGE_BOTH 4
49#define EXYNOS_EINT_CON_MASK 0xF
50#define EXYNOS_EINT_CON_LEN 4
51
52#define EXYNOS_EINT_MAX_PER_BANK 8
53#define EXYNOS_EINT_NR_WKUP_EINT
54
55/*
56 * EINT filter configuration register (on alive banks) has
57 * the following layout.
58 *
59 * BitfieldName[PinNum][Bit:Bit]
60 * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24]
61 * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16]
62 * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8]
63 * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0]
64 *
65 * FLT_EN 0x0 = Disable, 0x1=Enable
66 * FLT_SEL 0x0 = Analog delay filter, 0x1 Digital filter (clock count)
67 * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1
68 */
69
70#define EXYNOS_FLTCON_EN BIT(7)
71#define EXYNOS_FLTCON_DIGITAL BIT(6)
72#define EXYNOS_FLTCON_ANALOG (0 << 6)
73#define EXYNOS_FLTCON_LEN 8
74
75#define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
76 { \
77 .type = &bank_type_off, \
78 .pctl_offset = reg, \
79 .nr_pins = pins, \
80 .eint_type = EINT_TYPE_NONE, \
81 .name = id \
82 }
83
84#define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
85 { \
86 .type = &bank_type_off, \
87 .pctl_offset = reg, \
88 .nr_pins = pins, \
89 .eint_type = EINT_TYPE_GPIO, \
90 .eint_offset = offs, \
91 .name = id \
92 }
93
94#define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
95 { \
96 .type = &bank_type_alive, \
97 .pctl_offset = reg, \
98 .nr_pins = pins, \
99 .eint_type = EINT_TYPE_WKUP, \
100 .eint_offset = offs, \
101 .name = id \
102 }
103
104#define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
105 { \
106 .type = &exynos5433_bank_type_off, \
107 .pctl_offset = reg, \
108 .nr_pins = pins, \
109 .eint_type = EINT_TYPE_GPIO, \
110 .eint_offset = offs, \
111 .name = id \
112 }
113
114#define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
115 { \
116 .type = &exynos5433_bank_type_alive, \
117 .pctl_offset = reg, \
118 .nr_pins = pins, \
119 .eint_type = EINT_TYPE_WKUP, \
120 .eint_offset = offs, \
121 .name = id \
122 }
123
124#define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
125 { \
126 .type = &exynos5433_bank_type_off, \
127 .pctl_offset = reg, \
128 .nr_pins = pins, \
129 .eint_type = EINT_TYPE_WKUP, \
130 .eint_offset = offs, \
131 .name = id, \
132 .pctl_res_idx = pctl_idx, \
133 } \
134
135#define EXYNOS7870_PIN_BANK_EINTN(pins, reg, id) \
136 { \
137 .type = &exynos7870_bank_type_alive, \
138 .pctl_offset = reg, \
139 .nr_pins = pins, \
140 .eint_type = EINT_TYPE_NONE, \
141 .name = id \
142 }
143
144#define EXYNOS7870_PIN_BANK_EINTW(pins, reg, id, offs) \
145 { \
146 .type = &exynos7870_bank_type_alive, \
147 .pctl_offset = reg, \
148 .nr_pins = pins, \
149 .eint_type = EINT_TYPE_WKUP, \
150 .eint_offset = offs, \
151 .name = id \
152 }
153
154#define EXYNOS850_PIN_BANK_EINTN(pins, reg, id) \
155 { \
156 .type = &exynos850_bank_type_alive, \
157 .pctl_offset = reg, \
158 .nr_pins = pins, \
159 .eint_type = EINT_TYPE_NONE, \
160 .name = id \
161 }
162
163#define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs) \
164 { \
165 .type = &exynos850_bank_type_off, \
166 .pctl_offset = reg, \
167 .nr_pins = pins, \
168 .eint_type = EINT_TYPE_GPIO, \
169 .eint_offset = offs, \
170 .name = id \
171 }
172
173#define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs) \
174 { \
175 .type = &exynos850_bank_type_alive, \
176 .pctl_offset = reg, \
177 .nr_pins = pins, \
178 .eint_type = EINT_TYPE_WKUP, \
179 .eint_offset = offs, \
180 .name = id \
181 }
182
183#define EXYNOS8895_PIN_BANK_EINTG(pins, reg, id, offs) \
184 { \
185 .type = &exynos8895_bank_type_off, \
186 .pctl_offset = reg, \
187 .nr_pins = pins, \
188 .eint_type = EINT_TYPE_GPIO, \
189 .eint_offset = offs, \
190 .name = id \
191 }
192
193#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \
194 { \
195 .type = &exynos850_bank_type_off, \
196 .pctl_offset = reg, \
197 .nr_pins = pins, \
198 .eint_type = EINT_TYPE_GPIO, \
199 .eint_con_offset = con_offs, \
200 .eint_mask_offset = mask_offs, \
201 .eint_pend_offset = pend_offs, \
202 .name = id \
203 }
204
205#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \
206 { \
207 .type = &exynos850_bank_type_alive, \
208 .pctl_offset = reg, \
209 .nr_pins = pins, \
210 .eint_type = EINT_TYPE_WKUP, \
211 .eint_con_offset = con_offs, \
212 .eint_mask_offset = mask_offs, \
213 .eint_pend_offset = pend_offs, \
214 .name = id \
215 }
216
217#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \
218 { \
219 .type = &exynos850_bank_type_off, \
220 .pctl_offset = reg, \
221 .nr_pins = pins, \
222 .eint_type = EINT_TYPE_GPIO, \
223 .eint_offset = offs, \
224 .eint_fltcon_offset = fltcon_offs, \
225 .name = id \
226 }
227
228#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \
229 { \
230 .type = &exynos850_bank_type_alive, \
231 .pctl_offset = reg, \
232 .nr_pins = pins, \
233 .eint_type = EINT_TYPE_WKUP, \
234 .eint_offset = offs, \
235 .eint_fltcon_offset = fltcon_offs, \
236 .name = id \
237 }
238
239#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \
240 { \
241 .type = &artpec_bank_type_off, \
242 .pctl_offset = reg, \
243 .nr_pins = pins, \
244 .eint_type = EINT_TYPE_GPIO, \
245 .eint_offset = offs, \
246 .name = id \
247 }
248
249/**
250 * struct exynos_weint_data: irq specific data for all the wakeup interrupts
251 * generated by the external wakeup interrupt controller.
252 * @irq: interrupt number within the domain.
253 * @bank: bank responsible for this interrupt
254 */
255struct exynos_weint_data {
256 unsigned int irq;
257 struct samsung_pin_bank *bank;
258};
259
260/**
261 * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
262 * generated by the external wakeup interrupt controller.
263 * @nr_banks: count of banks being part of the mux
264 * @banks: array of banks being part of the mux
265 */
266struct exynos_muxed_weint_data {
267 unsigned int nr_banks;
268 struct samsung_pin_bank *banks[] __counted_by(nr_banks);
269};
270
271int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
272int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
273void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
274void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
275void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
276void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
277void gs101_pinctrl_suspend(struct samsung_pin_bank *bank);
278void gs101_pinctrl_resume(struct samsung_pin_bank *bank);
279struct samsung_retention_ctrl *
280exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
281 const struct samsung_retention_data *data);
282
283#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */