tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel / drivers / pinctrl / qcom / pinctrl-sdm670.c
at master 1351 lines 42 kB view raw
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Richard Acayan. All rights reserved. 5 */ 6 7#include <linux/module.h> 8#include <linux/of.h> 9#include <linux/platform_device.h> 10 11#include "pinctrl-msm.h" 12 13#define NORTH 0x00500000 14#define SOUTH 0x00900000 15#define WEST 0x00100000 16 17#define REG_SIZE 0x1000 18#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ 19 { \ 20 .grp = PINCTRL_PINGROUP("gpio" #id, \ 21 gpio##id##_pins, \ 22 ARRAY_SIZE(gpio##id##_pins)), \ 23 .funcs = (int[]){ \ 24 msm_mux_gpio, /* gpio mode */ \ 25 msm_mux_##f1, \ 26 msm_mux_##f2, \ 27 msm_mux_##f3, \ 28 msm_mux_##f4, \ 29 msm_mux_##f5, \ 30 msm_mux_##f6, \ 31 msm_mux_##f7, \ 32 msm_mux_##f8, \ 33 msm_mux_##f9 \ 34 }, \ 35 .nfuncs = 10, \ 36 .ctl_reg = base + REG_SIZE * id, \ 37 .io_reg = base + 0x4 + REG_SIZE * id, \ 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \ 39 .intr_status_reg = base + 0xc + REG_SIZE * id, \ 40 .mux_bit = 2, \ 41 .pull_bit = 0, \ 42 .drv_bit = 6, \ 43 .oe_bit = 9, \ 44 .in_bit = 0, \ 45 .out_bit = 1, \ 46 .intr_enable_bit = 0, \ 47 .intr_status_bit = 0, \ 48 .intr_target_bit = 5, \ 49 .intr_target_kpss_val = 3, \ 50 .intr_raw_status_bit = 4, \ 51 .intr_polarity_bit = 1, \ 52 .intr_detection_bit = 2, \ 53 .intr_detection_width = 2, \ 54 } 55 56/* 57 * A dummy pingroup is a pin group that cannot be assigned a function and has 58 * no registers to control or monitor it. 59 */ 60#define PINGROUP_DUMMY(id) \ 61 { \ 62 .grp = PINCTRL_PINGROUP("gpio" #id, \ 63 gpio##id##_pins, \ 64 ARRAY_SIZE(gpio##id##_pins)), \ 65 .ctl_reg = 0, \ 66 .io_reg = 0, \ 67 .intr_cfg_reg = 0, \ 68 .intr_status_reg = 0, \ 69 .mux_bit = -1, \ 70 .pull_bit = -1, \ 71 .drv_bit = -1, \ 72 .oe_bit = -1, \ 73 .in_bit = -1, \ 74 .out_bit = -1, \ 75 .intr_enable_bit = -1, \ 76 .intr_status_bit = -1, \ 77 .intr_target_bit = -1, \ 78 .intr_raw_status_bit = -1, \ 79 .intr_polarity_bit = -1, \ 80 .intr_detection_bit = -1, \ 81 .intr_detection_width = -1, \ 82 } 83 84#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ 85 { \ 86 .grp = PINCTRL_PINGROUP(#pg_name, \ 87 pg_name##_pins, \ 88 ARRAY_SIZE(pg_name##_pins)), \ 89 .ctl_reg = ctl, \ 90 .io_reg = 0, \ 91 .intr_cfg_reg = 0, \ 92 .intr_status_reg = 0, \ 93 .mux_bit = -1, \ 94 .pull_bit = pull, \ 95 .drv_bit = drv, \ 96 .oe_bit = -1, \ 97 .in_bit = -1, \ 98 .out_bit = -1, \ 99 .intr_enable_bit = -1, \ 100 .intr_status_bit = -1, \ 101 .intr_target_bit = -1, \ 102 .intr_raw_status_bit = -1, \ 103 .intr_polarity_bit = -1, \ 104 .intr_detection_bit = -1, \ 105 .intr_detection_width = -1, \ 106 } 107 108#define UFS_RESET(pg_name, offset) \ 109 { \ 110 .grp = PINCTRL_PINGROUP(#pg_name, \ 111 pg_name##_pins, \ 112 ARRAY_SIZE(pg_name##_pins)), \ 113 .ctl_reg = offset, \ 114 .io_reg = offset + 0x4, \ 115 .intr_cfg_reg = 0, \ 116 .intr_status_reg = 0, \ 117 .mux_bit = -1, \ 118 .pull_bit = 3, \ 119 .drv_bit = 0, \ 120 .oe_bit = -1, \ 121 .in_bit = -1, \ 122 .out_bit = 0, \ 123 .intr_enable_bit = -1, \ 124 .intr_status_bit = -1, \ 125 .intr_target_bit = -1, \ 126 .intr_raw_status_bit = -1, \ 127 .intr_polarity_bit = -1, \ 128 .intr_detection_bit = -1, \ 129 .intr_detection_width = -1, \ 130 } 131 132static const struct pinctrl_pin_desc sdm670_pins[] = { 133 PINCTRL_PIN(0, "GPIO_0"), 134 PINCTRL_PIN(1, "GPIO_1"), 135 PINCTRL_PIN(2, "GPIO_2"), 136 PINCTRL_PIN(3, "GPIO_3"), 137 PINCTRL_PIN(4, "GPIO_4"), 138 PINCTRL_PIN(5, "GPIO_5"), 139 PINCTRL_PIN(6, "GPIO_6"), 140 PINCTRL_PIN(7, "GPIO_7"), 141 PINCTRL_PIN(8, "GPIO_8"), 142 PINCTRL_PIN(9, "GPIO_9"), 143 PINCTRL_PIN(10, "GPIO_10"), 144 PINCTRL_PIN(11, "GPIO_11"), 145 PINCTRL_PIN(12, "GPIO_12"), 146 PINCTRL_PIN(13, "GPIO_13"), 147 PINCTRL_PIN(14, "GPIO_14"), 148 PINCTRL_PIN(15, "GPIO_15"), 149 PINCTRL_PIN(16, "GPIO_16"), 150 PINCTRL_PIN(17, "GPIO_17"), 151 PINCTRL_PIN(18, "GPIO_18"), 152 PINCTRL_PIN(19, "GPIO_19"), 153 PINCTRL_PIN(20, "GPIO_20"), 154 PINCTRL_PIN(21, "GPIO_21"), 155 PINCTRL_PIN(22, "GPIO_22"), 156 PINCTRL_PIN(23, "GPIO_23"), 157 PINCTRL_PIN(24, "GPIO_24"), 158 PINCTRL_PIN(25, "GPIO_25"), 159 PINCTRL_PIN(26, "GPIO_26"), 160 PINCTRL_PIN(27, "GPIO_27"), 161 PINCTRL_PIN(28, "GPIO_28"), 162 PINCTRL_PIN(29, "GPIO_29"), 163 PINCTRL_PIN(30, "GPIO_30"), 164 PINCTRL_PIN(31, "GPIO_31"), 165 PINCTRL_PIN(32, "GPIO_32"), 166 PINCTRL_PIN(33, "GPIO_33"), 167 PINCTRL_PIN(34, "GPIO_34"), 168 PINCTRL_PIN(35, "GPIO_35"), 169 PINCTRL_PIN(36, "GPIO_36"), 170 PINCTRL_PIN(37, "GPIO_37"), 171 PINCTRL_PIN(38, "GPIO_38"), 172 PINCTRL_PIN(39, "GPIO_39"), 173 PINCTRL_PIN(40, "GPIO_40"), 174 PINCTRL_PIN(41, "GPIO_41"), 175 PINCTRL_PIN(42, "GPIO_42"), 176 PINCTRL_PIN(43, "GPIO_43"), 177 PINCTRL_PIN(44, "GPIO_44"), 178 PINCTRL_PIN(45, "GPIO_45"), 179 PINCTRL_PIN(46, "GPIO_46"), 180 PINCTRL_PIN(47, "GPIO_47"), 181 PINCTRL_PIN(48, "GPIO_48"), 182 PINCTRL_PIN(49, "GPIO_49"), 183 PINCTRL_PIN(50, "GPIO_50"), 184 PINCTRL_PIN(51, "GPIO_51"), 185 PINCTRL_PIN(52, "GPIO_52"), 186 PINCTRL_PIN(53, "GPIO_53"), 187 PINCTRL_PIN(54, "GPIO_54"), 188 PINCTRL_PIN(55, "GPIO_55"), 189 PINCTRL_PIN(56, "GPIO_56"), 190 PINCTRL_PIN(57, "GPIO_57"), 191 PINCTRL_PIN(58, "GPIO_58"), 192 PINCTRL_PIN(59, "GPIO_59"), 193 PINCTRL_PIN(60, "GPIO_60"), 194 PINCTRL_PIN(61, "GPIO_61"), 195 PINCTRL_PIN(62, "GPIO_62"), 196 PINCTRL_PIN(63, "GPIO_63"), 197 PINCTRL_PIN(64, "GPIO_64"), 198 PINCTRL_PIN(65, "GPIO_65"), 199 PINCTRL_PIN(66, "GPIO_66"), 200 PINCTRL_PIN(67, "GPIO_67"), 201 PINCTRL_PIN(68, "GPIO_68"), 202 PINCTRL_PIN(69, "GPIO_69"), 203 PINCTRL_PIN(70, "GPIO_70"), 204 PINCTRL_PIN(71, "GPIO_71"), 205 PINCTRL_PIN(72, "GPIO_72"), 206 PINCTRL_PIN(73, "GPIO_73"), 207 PINCTRL_PIN(74, "GPIO_74"), 208 PINCTRL_PIN(75, "GPIO_75"), 209 PINCTRL_PIN(76, "GPIO_76"), 210 PINCTRL_PIN(77, "GPIO_77"), 211 PINCTRL_PIN(78, "GPIO_78"), 212 PINCTRL_PIN(79, "GPIO_79"), 213 PINCTRL_PIN(80, "GPIO_80"), 214 PINCTRL_PIN(81, "GPIO_81"), 215 PINCTRL_PIN(82, "GPIO_82"), 216 PINCTRL_PIN(83, "GPIO_83"), 217 PINCTRL_PIN(84, "GPIO_84"), 218 PINCTRL_PIN(85, "GPIO_85"), 219 PINCTRL_PIN(86, "GPIO_86"), 220 PINCTRL_PIN(87, "GPIO_87"), 221 PINCTRL_PIN(88, "GPIO_88"), 222 PINCTRL_PIN(89, "GPIO_89"), 223 PINCTRL_PIN(90, "GPIO_90"), 224 PINCTRL_PIN(91, "GPIO_91"), 225 PINCTRL_PIN(92, "GPIO_92"), 226 PINCTRL_PIN(93, "GPIO_93"), 227 PINCTRL_PIN(94, "GPIO_94"), 228 PINCTRL_PIN(95, "GPIO_95"), 229 PINCTRL_PIN(96, "GPIO_96"), 230 PINCTRL_PIN(97, "GPIO_97"), 231 PINCTRL_PIN(98, "GPIO_98"), 232 PINCTRL_PIN(99, "GPIO_99"), 233 PINCTRL_PIN(100, "GPIO_100"), 234 PINCTRL_PIN(101, "GPIO_101"), 235 PINCTRL_PIN(102, "GPIO_102"), 236 PINCTRL_PIN(103, "GPIO_103"), 237 PINCTRL_PIN(104, "GPIO_104"), 238 PINCTRL_PIN(105, "GPIO_105"), 239 PINCTRL_PIN(106, "GPIO_106"), 240 PINCTRL_PIN(107, "GPIO_107"), 241 PINCTRL_PIN(108, "GPIO_108"), 242 PINCTRL_PIN(109, "GPIO_109"), 243 PINCTRL_PIN(110, "GPIO_110"), 244 PINCTRL_PIN(111, "GPIO_111"), 245 PINCTRL_PIN(112, "GPIO_112"), 246 PINCTRL_PIN(113, "GPIO_113"), 247 PINCTRL_PIN(114, "GPIO_114"), 248 PINCTRL_PIN(115, "GPIO_115"), 249 PINCTRL_PIN(116, "GPIO_116"), 250 PINCTRL_PIN(117, "GPIO_117"), 251 PINCTRL_PIN(118, "GPIO_118"), 252 PINCTRL_PIN(119, "GPIO_119"), 253 PINCTRL_PIN(120, "GPIO_120"), 254 PINCTRL_PIN(121, "GPIO_121"), 255 PINCTRL_PIN(122, "GPIO_122"), 256 PINCTRL_PIN(123, "GPIO_123"), 257 PINCTRL_PIN(124, "GPIO_124"), 258 PINCTRL_PIN(125, "GPIO_125"), 259 PINCTRL_PIN(126, "GPIO_126"), 260 PINCTRL_PIN(127, "GPIO_127"), 261 PINCTRL_PIN(128, "GPIO_128"), 262 PINCTRL_PIN(129, "GPIO_129"), 263 PINCTRL_PIN(130, "GPIO_130"), 264 PINCTRL_PIN(131, "GPIO_131"), 265 PINCTRL_PIN(132, "GPIO_132"), 266 PINCTRL_PIN(133, "GPIO_133"), 267 PINCTRL_PIN(134, "GPIO_134"), 268 PINCTRL_PIN(135, "GPIO_135"), 269 PINCTRL_PIN(136, "GPIO_136"), 270 PINCTRL_PIN(137, "GPIO_137"), 271 PINCTRL_PIN(138, "GPIO_138"), 272 PINCTRL_PIN(139, "GPIO_139"), 273 PINCTRL_PIN(140, "GPIO_140"), 274 PINCTRL_PIN(141, "GPIO_141"), 275 PINCTRL_PIN(142, "GPIO_142"), 276 PINCTRL_PIN(143, "GPIO_143"), 277 PINCTRL_PIN(144, "GPIO_144"), 278 PINCTRL_PIN(145, "GPIO_145"), 279 PINCTRL_PIN(146, "GPIO_146"), 280 PINCTRL_PIN(147, "GPIO_147"), 281 PINCTRL_PIN(148, "GPIO_148"), 282 PINCTRL_PIN(149, "GPIO_149"), 283 PINCTRL_PIN(150, "UFS_RESET"), 284 PINCTRL_PIN(151, "SDC1_RCLK"), 285 PINCTRL_PIN(152, "SDC1_CLK"), 286 PINCTRL_PIN(153, "SDC1_CMD"), 287 PINCTRL_PIN(154, "SDC1_DATA"), 288 PINCTRL_PIN(155, "SDC2_CLK"), 289 PINCTRL_PIN(156, "SDC2_CMD"), 290 PINCTRL_PIN(157, "SDC2_DATA"), 291}; 292 293#define DECLARE_MSM_GPIO_PINS(pin) \ 294 static const unsigned int gpio##pin##_pins[] = { pin } 295DECLARE_MSM_GPIO_PINS(0); 296DECLARE_MSM_GPIO_PINS(1); 297DECLARE_MSM_GPIO_PINS(2); 298DECLARE_MSM_GPIO_PINS(3); 299DECLARE_MSM_GPIO_PINS(4); 300DECLARE_MSM_GPIO_PINS(5); 301DECLARE_MSM_GPIO_PINS(6); 302DECLARE_MSM_GPIO_PINS(7); 303DECLARE_MSM_GPIO_PINS(8); 304DECLARE_MSM_GPIO_PINS(9); 305DECLARE_MSM_GPIO_PINS(10); 306DECLARE_MSM_GPIO_PINS(11); 307DECLARE_MSM_GPIO_PINS(12); 308DECLARE_MSM_GPIO_PINS(13); 309DECLARE_MSM_GPIO_PINS(14); 310DECLARE_MSM_GPIO_PINS(15); 311DECLARE_MSM_GPIO_PINS(16); 312DECLARE_MSM_GPIO_PINS(17); 313DECLARE_MSM_GPIO_PINS(18); 314DECLARE_MSM_GPIO_PINS(19); 315DECLARE_MSM_GPIO_PINS(20); 316DECLARE_MSM_GPIO_PINS(21); 317DECLARE_MSM_GPIO_PINS(22); 318DECLARE_MSM_GPIO_PINS(23); 319DECLARE_MSM_GPIO_PINS(24); 320DECLARE_MSM_GPIO_PINS(25); 321DECLARE_MSM_GPIO_PINS(26); 322DECLARE_MSM_GPIO_PINS(27); 323DECLARE_MSM_GPIO_PINS(28); 324DECLARE_MSM_GPIO_PINS(29); 325DECLARE_MSM_GPIO_PINS(30); 326DECLARE_MSM_GPIO_PINS(31); 327DECLARE_MSM_GPIO_PINS(32); 328DECLARE_MSM_GPIO_PINS(33); 329DECLARE_MSM_GPIO_PINS(34); 330DECLARE_MSM_GPIO_PINS(35); 331DECLARE_MSM_GPIO_PINS(36); 332DECLARE_MSM_GPIO_PINS(37); 333DECLARE_MSM_GPIO_PINS(38); 334DECLARE_MSM_GPIO_PINS(39); 335DECLARE_MSM_GPIO_PINS(40); 336DECLARE_MSM_GPIO_PINS(41); 337DECLARE_MSM_GPIO_PINS(42); 338DECLARE_MSM_GPIO_PINS(43); 339DECLARE_MSM_GPIO_PINS(44); 340DECLARE_MSM_GPIO_PINS(45); 341DECLARE_MSM_GPIO_PINS(46); 342DECLARE_MSM_GPIO_PINS(47); 343DECLARE_MSM_GPIO_PINS(48); 344DECLARE_MSM_GPIO_PINS(49); 345DECLARE_MSM_GPIO_PINS(50); 346DECLARE_MSM_GPIO_PINS(51); 347DECLARE_MSM_GPIO_PINS(52); 348DECLARE_MSM_GPIO_PINS(53); 349DECLARE_MSM_GPIO_PINS(54); 350DECLARE_MSM_GPIO_PINS(55); 351DECLARE_MSM_GPIO_PINS(56); 352DECLARE_MSM_GPIO_PINS(57); 353DECLARE_MSM_GPIO_PINS(58); 354DECLARE_MSM_GPIO_PINS(59); 355DECLARE_MSM_GPIO_PINS(60); 356DECLARE_MSM_GPIO_PINS(61); 357DECLARE_MSM_GPIO_PINS(62); 358DECLARE_MSM_GPIO_PINS(63); 359DECLARE_MSM_GPIO_PINS(64); 360DECLARE_MSM_GPIO_PINS(65); 361DECLARE_MSM_GPIO_PINS(66); 362DECLARE_MSM_GPIO_PINS(67); 363DECLARE_MSM_GPIO_PINS(68); 364DECLARE_MSM_GPIO_PINS(69); 365DECLARE_MSM_GPIO_PINS(70); 366DECLARE_MSM_GPIO_PINS(71); 367DECLARE_MSM_GPIO_PINS(72); 368DECLARE_MSM_GPIO_PINS(73); 369DECLARE_MSM_GPIO_PINS(74); 370DECLARE_MSM_GPIO_PINS(75); 371DECLARE_MSM_GPIO_PINS(76); 372DECLARE_MSM_GPIO_PINS(77); 373DECLARE_MSM_GPIO_PINS(78); 374DECLARE_MSM_GPIO_PINS(79); 375DECLARE_MSM_GPIO_PINS(80); 376DECLARE_MSM_GPIO_PINS(81); 377DECLARE_MSM_GPIO_PINS(82); 378DECLARE_MSM_GPIO_PINS(83); 379DECLARE_MSM_GPIO_PINS(84); 380DECLARE_MSM_GPIO_PINS(85); 381DECLARE_MSM_GPIO_PINS(86); 382DECLARE_MSM_GPIO_PINS(87); 383DECLARE_MSM_GPIO_PINS(88); 384DECLARE_MSM_GPIO_PINS(89); 385DECLARE_MSM_GPIO_PINS(90); 386DECLARE_MSM_GPIO_PINS(91); 387DECLARE_MSM_GPIO_PINS(92); 388DECLARE_MSM_GPIO_PINS(93); 389DECLARE_MSM_GPIO_PINS(94); 390DECLARE_MSM_GPIO_PINS(95); 391DECLARE_MSM_GPIO_PINS(96); 392DECLARE_MSM_GPIO_PINS(97); 393DECLARE_MSM_GPIO_PINS(98); 394DECLARE_MSM_GPIO_PINS(99); 395DECLARE_MSM_GPIO_PINS(100); 396DECLARE_MSM_GPIO_PINS(101); 397DECLARE_MSM_GPIO_PINS(102); 398DECLARE_MSM_GPIO_PINS(103); 399DECLARE_MSM_GPIO_PINS(104); 400DECLARE_MSM_GPIO_PINS(105); 401DECLARE_MSM_GPIO_PINS(106); 402DECLARE_MSM_GPIO_PINS(107); 403DECLARE_MSM_GPIO_PINS(108); 404DECLARE_MSM_GPIO_PINS(109); 405DECLARE_MSM_GPIO_PINS(110); 406DECLARE_MSM_GPIO_PINS(111); 407DECLARE_MSM_GPIO_PINS(112); 408DECLARE_MSM_GPIO_PINS(113); 409DECLARE_MSM_GPIO_PINS(114); 410DECLARE_MSM_GPIO_PINS(115); 411DECLARE_MSM_GPIO_PINS(116); 412DECLARE_MSM_GPIO_PINS(117); 413DECLARE_MSM_GPIO_PINS(118); 414DECLARE_MSM_GPIO_PINS(119); 415DECLARE_MSM_GPIO_PINS(120); 416DECLARE_MSM_GPIO_PINS(121); 417DECLARE_MSM_GPIO_PINS(122); 418DECLARE_MSM_GPIO_PINS(123); 419DECLARE_MSM_GPIO_PINS(124); 420DECLARE_MSM_GPIO_PINS(125); 421DECLARE_MSM_GPIO_PINS(126); 422DECLARE_MSM_GPIO_PINS(127); 423DECLARE_MSM_GPIO_PINS(128); 424DECLARE_MSM_GPIO_PINS(129); 425DECLARE_MSM_GPIO_PINS(130); 426DECLARE_MSM_GPIO_PINS(131); 427DECLARE_MSM_GPIO_PINS(132); 428DECLARE_MSM_GPIO_PINS(133); 429DECLARE_MSM_GPIO_PINS(134); 430DECLARE_MSM_GPIO_PINS(135); 431DECLARE_MSM_GPIO_PINS(136); 432DECLARE_MSM_GPIO_PINS(137); 433DECLARE_MSM_GPIO_PINS(138); 434DECLARE_MSM_GPIO_PINS(139); 435DECLARE_MSM_GPIO_PINS(140); 436DECLARE_MSM_GPIO_PINS(141); 437DECLARE_MSM_GPIO_PINS(142); 438DECLARE_MSM_GPIO_PINS(143); 439DECLARE_MSM_GPIO_PINS(144); 440DECLARE_MSM_GPIO_PINS(145); 441DECLARE_MSM_GPIO_PINS(146); 442DECLARE_MSM_GPIO_PINS(147); 443DECLARE_MSM_GPIO_PINS(148); 444DECLARE_MSM_GPIO_PINS(149); 445 446static const unsigned int ufs_reset_pins[] = { 150 }; 447static const unsigned int sdc1_rclk_pins[] = { 151 }; 448static const unsigned int sdc1_clk_pins[] = { 152 }; 449static const unsigned int sdc1_cmd_pins[] = { 153 }; 450static const unsigned int sdc1_data_pins[] = { 154 }; 451static const unsigned int sdc2_clk_pins[] = { 155 }; 452static const unsigned int sdc2_cmd_pins[] = { 156 }; 453static const unsigned int sdc2_data_pins[] = { 157 }; 454 455enum sdm670_functions { 456 msm_mux_gpio, 457 msm_mux_adsp_ext, 458 msm_mux_agera_pll, 459 msm_mux_atest_char, 460 msm_mux_atest_tsens, 461 msm_mux_atest_tsens2, 462 msm_mux_atest_usb1, 463 msm_mux_atest_usb10, 464 msm_mux_atest_usb11, 465 msm_mux_atest_usb12, 466 msm_mux_atest_usb13, 467 msm_mux_atest_usb2, 468 msm_mux_atest_usb20, 469 msm_mux_atest_usb21, 470 msm_mux_atest_usb22, 471 msm_mux_atest_usb23, 472 msm_mux_cam_mclk, 473 msm_mux_cci_async, 474 msm_mux_cci_i2c, 475 msm_mux_cci_timer0, 476 msm_mux_cci_timer1, 477 msm_mux_cci_timer2, 478 msm_mux_cci_timer3, 479 msm_mux_cci_timer4, 480 msm_mux_copy_gp, 481 msm_mux_copy_phase, 482 msm_mux_dbg_out, 483 msm_mux_ddr_bist, 484 msm_mux_ddr_pxi0, 485 msm_mux_ddr_pxi1, 486 msm_mux_ddr_pxi2, 487 msm_mux_ddr_pxi3, 488 msm_mux_edp_hot, 489 msm_mux_edp_lcd, 490 msm_mux_gcc_gp1, 491 msm_mux_gcc_gp2, 492 msm_mux_gcc_gp3, 493 msm_mux_gp_pdm0, 494 msm_mux_gp_pdm1, 495 msm_mux_gp_pdm2, 496 msm_mux_gps_tx, 497 msm_mux_jitter_bist, 498 msm_mux_ldo_en, 499 msm_mux_ldo_update, 500 msm_mux_lpass_slimbus, 501 msm_mux_m_voc, 502 msm_mux_mdp_vsync, 503 msm_mux_mdp_vsync0, 504 msm_mux_mdp_vsync1, 505 msm_mux_mdp_vsync2, 506 msm_mux_mdp_vsync3, 507 msm_mux_mss_lte, 508 msm_mux_nav_pps, 509 msm_mux_pa_indicator, 510 msm_mux_pci_e0, 511 msm_mux_pci_e1, 512 msm_mux_phase_flag, 513 msm_mux_pll_bist, 514 msm_mux_pll_bypassnl, 515 msm_mux_pll_reset, 516 msm_mux_pri_mi2s, 517 msm_mux_pri_mi2s_ws, 518 msm_mux_prng_rosc, 519 msm_mux_qdss_cti, 520 msm_mux_qdss, 521 msm_mux_qlink_enable, 522 msm_mux_qlink_request, 523 msm_mux_qua_mi2s, 524 msm_mux_qup0, 525 msm_mux_qup1, 526 msm_mux_qup10, 527 msm_mux_qup11, 528 msm_mux_qup12, 529 msm_mux_qup13, 530 msm_mux_qup14, 531 msm_mux_qup15, 532 msm_mux_qup2, 533 msm_mux_qup3, 534 msm_mux_qup4, 535 msm_mux_qup5, 536 msm_mux_qup6, 537 msm_mux_qup7, 538 msm_mux_qup8, 539 msm_mux_qup9, 540 msm_mux_qup_l4, 541 msm_mux_qup_l5, 542 msm_mux_qup_l6, 543 msm_mux_sd_write, 544 msm_mux_sdc4_clk, 545 msm_mux_sdc4_cmd, 546 msm_mux_sdc4_data, 547 msm_mux_sec_mi2s, 548 msm_mux_ter_mi2s, 549 msm_mux_tgu_ch0, 550 msm_mux_tgu_ch1, 551 msm_mux_tgu_ch2, 552 msm_mux_tgu_ch3, 553 msm_mux_tsif1_clk, 554 msm_mux_tsif1_data, 555 msm_mux_tsif1_en, 556 msm_mux_tsif1_error, 557 msm_mux_tsif1_sync, 558 msm_mux_tsif2_clk, 559 msm_mux_tsif2_data, 560 msm_mux_tsif2_en, 561 msm_mux_tsif2_error, 562 msm_mux_tsif2_sync, 563 msm_mux_uim1_clk, 564 msm_mux_uim1_data, 565 msm_mux_uim1_present, 566 msm_mux_uim1_reset, 567 msm_mux_uim2_clk, 568 msm_mux_uim2_data, 569 msm_mux_uim2_present, 570 msm_mux_uim2_reset, 571 msm_mux_uim_batt, 572 msm_mux_usb_phy, 573 msm_mux_vfr_1, 574 msm_mux_vsense_trigger, 575 msm_mux_wlan1_adc0, 576 msm_mux_wlan1_adc1, 577 msm_mux_wlan2_adc0, 578 msm_mux_wlan2_adc1, 579 msm_mux_wsa_clk, 580 msm_mux_wsa_data, 581 msm_mux__, 582}; 583 584static const char * const gpio_groups[] = { 585 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", 586 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", 587 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", 588 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", 589 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", 590 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", 591 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", 592 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 593 "gpio57", "gpio65", "gpio66", "gpio67", "gpio68", "gpio75", "gpio76", 594 "gpio77", "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 595 "gpio84", "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", 596 "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", 597 "gpio98", "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", 598 "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", 599 "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", 600 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 601 "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", 602 "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", 603 "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", 604 "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", 605 "gpio147", "gpio148", "gpio149", 606}; 607static const char * const qup0_groups[] = { 608 "gpio0", "gpio1", "gpio2", "gpio3", 609}; 610static const char * const qup9_groups[] = { 611 "gpio4", "gpio5", "gpio6", "gpio7", 612}; 613static const char * const qdss_cti_groups[] = { 614 "gpio4", "gpio5", "gpio51", "gpio52", "gpio90", "gpio91", 615}; 616static const char * const ddr_pxi0_groups[] = { 617 "gpio6", "gpio7", 618}; 619static const char * const ddr_bist_groups[] = { 620 "gpio7", "gpio8", "gpio9", "gpio10", 621}; 622static const char * const atest_tsens2_groups[] = { 623 "gpio7", 624}; 625static const char * const vsense_trigger_groups[] = { 626 "gpio7", 627}; 628static const char * const atest_usb1_groups[] = { 629 "gpio7", 630}; 631static const char * const qup_l4_groups[] = { 632 "gpio8", "gpio35", "gpio75", "gpio105", "gpio123", 633}; 634static const char * const gp_pdm1_groups[] = { 635 "gpio8", "gpio66", 636}; 637static const char * const qup_l5_groups[] = { 638 "gpio9", "gpio36", "gpio76", "gpio106", "gpio124", 639}; 640static const char * const mdp_vsync_groups[] = { 641 "gpio10", "gpio11", "gpio12", "gpio97", "gpio98", 642}; 643static const char * const qup_l6_groups[] = { 644 "gpio10", "gpio37", "gpio77", "gpio107", "gpio125", 645}; 646static const char * const wlan2_adc1_groups[] = { 647 "gpio10", 648}; 649static const char * const atest_usb11_groups[] = { 650 "gpio10", 651}; 652static const char * const ddr_pxi2_groups[] = { 653 "gpio10", "gpio11", 654}; 655static const char * const edp_lcd_groups[] = { 656 "gpio11", 657}; 658static const char * const dbg_out_groups[] = { 659 "gpio11", 660}; 661static const char * const wlan2_adc0_groups[] = { 662 "gpio11", 663}; 664static const char * const atest_usb10_groups[] = { 665 "gpio11", 666}; 667static const char * const m_voc_groups[] = { 668 "gpio12", 669}; 670static const char * const tsif1_sync_groups[] = { 671 "gpio12", 672}; 673static const char * const ddr_pxi3_groups[] = { 674 "gpio12", "gpio13", 675}; 676static const char * const cam_mclk_groups[] = { 677 "gpio13", "gpio14", "gpio15", "gpio16", 678}; 679static const char * const pll_bypassnl_groups[] = { 680 "gpio13", 681}; 682static const char * const qdss_groups[] = { 683 "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", 684 "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", 685 "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43", 686 "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93", 687 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", 688 "gpio123", "gpio124", 689}; 690static const char * const pll_reset_groups[] = { 691 "gpio14", 692}; 693static const char * const cci_i2c_groups[] = { 694 "gpio17", "gpio18", "gpio19", "gpio20", 695}; 696static const char * const qup1_groups[] = { 697 "gpio17", "gpio18", "gpio19", "gpio20", 698}; 699static const char * const cci_timer0_groups[] = { 700 "gpio21", 701}; 702static const char * const gcc_gp2_groups[] = { 703 "gpio21", 704}; 705static const char * const cci_timer1_groups[] = { 706 "gpio22", 707}; 708static const char * const gcc_gp3_groups[] = { 709 "gpio22", 710}; 711static const char * const cci_timer2_groups[] = { 712 "gpio23", 713}; 714static const char * const cci_timer3_groups[] = { 715 "gpio24", 716}; 717static const char * const cci_async_groups[] = { 718 "gpio24", "gpio25", "gpio26", 719}; 720static const char * const cci_timer4_groups[] = { 721 "gpio25", 722}; 723static const char * const jitter_bist_groups[] = { 724 "gpio26", "gpio35", 725}; 726static const char * const qup2_groups[] = { 727 "gpio27", "gpio28", "gpio29", "gpio30", 728}; 729static const char * const pll_bist_groups[] = { 730 "gpio27", "gpio36", 731}; 732static const char * const agera_pll_groups[] = { 733 "gpio28", "gpio37", 734}; 735static const char * const atest_tsens_groups[] = { 736 "gpio29", 737}; 738static const char * const phase_flag_groups[] = { 739 "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", 740 "gpio57", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90", "gpio96", 741 "gpio99", "gpio100", "gpio101", "gpio137", "gpio138", "gpio139", 742 "gpio140", "gpio141", "gpio142", "gpio143", 743}; 744static const char * const qup11_groups[] = { 745 "gpio31", "gpio32", "gpio33", "gpio34", 746}; 747static const char * const qup14_groups[] = { 748 "gpio31", "gpio32", "gpio33", "gpio34", 749}; 750static const char * const pci_e0_groups[] = { 751 "gpio35", "gpio36", 752}; 753static const char * const usb_phy_groups[] = { 754 "gpio38", 755}; 756static const char * const lpass_slimbus_groups[] = { 757 "gpio39", 758}; 759static const char * const sd_write_groups[] = { 760 "gpio40", 761}; 762static const char * const tsif1_error_groups[] = { 763 "gpio40", 764}; 765static const char * const qup3_groups[] = { 766 "gpio41", "gpio42", "gpio43", "gpio44", 767}; 768static const char * const qup6_groups[] = { 769 "gpio45", "gpio46", "gpio47", "gpio48", 770}; 771static const char * const qup12_groups[] = { 772 "gpio49", "gpio50", "gpio51", "gpio52", 773}; 774static const char * const qup10_groups[] = { 775 "gpio53", "gpio54", "gpio55", "gpio56", 776}; 777static const char * const gp_pdm0_groups[] = { 778 "gpio54", "gpio95", 779}; 780static const char * const wlan1_adc1_groups[] = { 781 "gpio54", 782}; 783static const char * const atest_usb13_groups[] = { 784 "gpio54", 785}; 786static const char * const ddr_pxi1_groups[] = { 787 "gpio54", "gpio55", 788}; 789static const char * const wlan1_adc0_groups[] = { 790 "gpio55", 791}; 792static const char * const atest_usb12_groups[] = { 793 "gpio55", 794}; 795static const char * const qua_mi2s_groups[] = { 796 "gpio57", 797}; 798static const char * const gcc_gp1_groups[] = { 799 "gpio57", "gpio78", 800}; 801static const char * const pri_mi2s_groups[] = { 802 "gpio65", "gpio67", "gpio68", 803}; 804static const char * const qup8_groups[] = { 805 "gpio65", "gpio66", "gpio67", "gpio68", 806}; 807static const char * const wsa_clk_groups[] = { 808 "gpio65", 809}; 810static const char * const pri_mi2s_ws_groups[] = { 811 "gpio66", 812}; 813static const char * const wsa_data_groups[] = { 814 "gpio66", 815}; 816static const char * const atest_usb2_groups[] = { 817 "gpio67", 818}; 819static const char * const atest_usb23_groups[] = { 820 "gpio68", 821}; 822static const char * const ter_mi2s_groups[] = { 823 "gpio75", "gpio76", "gpio77", "gpio78", 824}; 825static const char * const atest_usb22_groups[] = { 826 "gpio75", 827}; 828static const char * const atest_usb21_groups[] = { 829 "gpio76", 830}; 831static const char * const atest_usb20_groups[] = { 832 "gpio77", 833}; 834static const char * const sec_mi2s_groups[] = { 835 "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", 836}; 837static const char * const gp_pdm2_groups[] = { 838 "gpio79", 839}; 840static const char * const qup15_groups[] = { 841 "gpio81", "gpio82", "gpio83", "gpio84", 842}; 843static const char * const qup5_groups[] = { 844 "gpio85", "gpio86", "gpio87", "gpio88", 845}; 846static const char * const copy_gp_groups[] = { 847 "gpio86", 848}; 849static const char * const tsif1_clk_groups[] = { 850 "gpio89", 851}; 852static const char * const qup4_groups[] = { 853 "gpio89", "gpio90", "gpio91", "gpio92", 854}; 855static const char * const tgu_ch3_groups[] = { 856 "gpio89", 857}; 858static const char * const tsif1_en_groups[] = { 859 "gpio90", 860}; 861static const char * const mdp_vsync0_groups[] = { 862 "gpio90", 863}; 864static const char * const mdp_vsync1_groups[] = { 865 "gpio90", 866}; 867static const char * const mdp_vsync2_groups[] = { 868 "gpio90", 869}; 870static const char * const mdp_vsync3_groups[] = { 871 "gpio90", 872}; 873static const char * const tgu_ch0_groups[] = { 874 "gpio90", 875}; 876static const char * const tsif1_data_groups[] = { 877 "gpio91", 878}; 879static const char * const sdc4_cmd_groups[] = { 880 "gpio91", 881}; 882static const char * const tgu_ch1_groups[] = { 883 "gpio91", 884}; 885static const char * const tsif2_error_groups[] = { 886 "gpio92", 887}; 888static const char * const vfr_1_groups[] = { 889 "gpio92", 890}; 891static const char * const tgu_ch2_groups[] = { 892 "gpio92", 893}; 894static const char * const sdc4_data_groups[] = { 895 "gpio92", "gpio94", "gpio95", "gpio96", 896}; 897static const char * const tsif2_clk_groups[] = { 898 "gpio93", 899}; 900static const char * const sdc4_clk_groups[] = { 901 "gpio93", 902}; 903static const char * const qup7_groups[] = { 904 "gpio93", "gpio94", "gpio95", "gpio96", 905}; 906static const char * const tsif2_en_groups[] = { 907 "gpio94", 908}; 909static const char * const tsif2_data_groups[] = { 910 "gpio95", 911}; 912static const char * const tsif2_sync_groups[] = { 913 "gpio96", 914}; 915static const char * const ldo_en_groups[] = { 916 "gpio97", 917}; 918static const char * const ldo_update_groups[] = { 919 "gpio98", 920}; 921static const char * const prng_rosc_groups[] = { 922 "gpio99", "gpio102", 923}; 924static const char * const pci_e1_groups[] = { 925 "gpio102", "gpio103", 926}; 927static const char * const copy_phase_groups[] = { 928 "gpio103", 929}; 930static const char * const uim2_data_groups[] = { 931 "gpio105", 932}; 933static const char * const qup13_groups[] = { 934 "gpio105", "gpio106", "gpio107", "gpio108", 935}; 936static const char * const uim2_clk_groups[] = { 937 "gpio106", 938}; 939static const char * const uim2_reset_groups[] = { 940 "gpio107", 941}; 942static const char * const uim2_present_groups[] = { 943 "gpio108", 944}; 945static const char * const uim1_data_groups[] = { 946 "gpio109", 947}; 948static const char * const uim1_clk_groups[] = { 949 "gpio110", 950}; 951static const char * const uim1_reset_groups[] = { 952 "gpio111", 953}; 954static const char * const uim1_present_groups[] = { 955 "gpio112", 956}; 957static const char * const uim_batt_groups[] = { 958 "gpio113", 959}; 960static const char * const edp_hot_groups[] = { 961 "gpio113", 962}; 963static const char * const nav_pps_groups[] = { 964 "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128", 965 "gpio129", "gpio129", "gpio143", "gpio143", 966}; 967static const char * const gps_tx_groups[] = { 968 "gpio114", "gpio115", "gpio128", "gpio129", "gpio143", "gpio145", 969}; 970static const char * const atest_char_groups[] = { 971 "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", 972}; 973static const char * const adsp_ext_groups[] = { 974 "gpio118", 975}; 976static const char * const qlink_request_groups[] = { 977 "gpio130", 978}; 979static const char * const qlink_enable_groups[] = { 980 "gpio131", 981}; 982static const char * const pa_indicator_groups[] = { 983 "gpio135", 984}; 985static const char * const mss_lte_groups[] = { 986 "gpio144", "gpio145", 987}; 988 989static const struct pinfunction sdm670_functions[] = { 990 MSM_GPIO_PIN_FUNCTION(gpio), 991 MSM_PIN_FUNCTION(adsp_ext), 992 MSM_PIN_FUNCTION(agera_pll), 993 MSM_PIN_FUNCTION(atest_char), 994 MSM_PIN_FUNCTION(atest_tsens), 995 MSM_PIN_FUNCTION(atest_tsens2), 996 MSM_PIN_FUNCTION(atest_usb1), 997 MSM_PIN_FUNCTION(atest_usb10), 998 MSM_PIN_FUNCTION(atest_usb11), 999 MSM_PIN_FUNCTION(atest_usb12), 1000 MSM_PIN_FUNCTION(atest_usb13), 1001 MSM_PIN_FUNCTION(atest_usb2), 1002 MSM_PIN_FUNCTION(atest_usb20), 1003 MSM_PIN_FUNCTION(atest_usb21), 1004 MSM_PIN_FUNCTION(atest_usb22), 1005 MSM_PIN_FUNCTION(atest_usb23), 1006 MSM_PIN_FUNCTION(cam_mclk), 1007 MSM_PIN_FUNCTION(cci_async), 1008 MSM_PIN_FUNCTION(cci_i2c), 1009 MSM_PIN_FUNCTION(cci_timer0), 1010 MSM_PIN_FUNCTION(cci_timer1), 1011 MSM_PIN_FUNCTION(cci_timer2), 1012 MSM_PIN_FUNCTION(cci_timer3), 1013 MSM_PIN_FUNCTION(cci_timer4), 1014 MSM_PIN_FUNCTION(copy_gp), 1015 MSM_PIN_FUNCTION(copy_phase), 1016 MSM_PIN_FUNCTION(dbg_out), 1017 MSM_PIN_FUNCTION(ddr_bist), 1018 MSM_PIN_FUNCTION(ddr_pxi0), 1019 MSM_PIN_FUNCTION(ddr_pxi1), 1020 MSM_PIN_FUNCTION(ddr_pxi2), 1021 MSM_PIN_FUNCTION(ddr_pxi3), 1022 MSM_PIN_FUNCTION(edp_hot), 1023 MSM_PIN_FUNCTION(edp_lcd), 1024 MSM_PIN_FUNCTION(gcc_gp1), 1025 MSM_PIN_FUNCTION(gcc_gp2), 1026 MSM_PIN_FUNCTION(gcc_gp3), 1027 MSM_PIN_FUNCTION(gp_pdm0), 1028 MSM_PIN_FUNCTION(gp_pdm1), 1029 MSM_PIN_FUNCTION(gp_pdm2), 1030 MSM_PIN_FUNCTION(gps_tx), 1031 MSM_PIN_FUNCTION(jitter_bist), 1032 MSM_PIN_FUNCTION(ldo_en), 1033 MSM_PIN_FUNCTION(ldo_update), 1034 MSM_PIN_FUNCTION(lpass_slimbus), 1035 MSM_PIN_FUNCTION(m_voc), 1036 MSM_PIN_FUNCTION(mdp_vsync), 1037 MSM_PIN_FUNCTION(mdp_vsync0), 1038 MSM_PIN_FUNCTION(mdp_vsync1), 1039 MSM_PIN_FUNCTION(mdp_vsync2), 1040 MSM_PIN_FUNCTION(mdp_vsync3), 1041 MSM_PIN_FUNCTION(mss_lte), 1042 MSM_PIN_FUNCTION(nav_pps), 1043 MSM_PIN_FUNCTION(pa_indicator), 1044 MSM_PIN_FUNCTION(pci_e0), 1045 MSM_PIN_FUNCTION(pci_e1), 1046 MSM_PIN_FUNCTION(phase_flag), 1047 MSM_PIN_FUNCTION(pll_bist), 1048 MSM_PIN_FUNCTION(pll_bypassnl), 1049 MSM_PIN_FUNCTION(pll_reset), 1050 MSM_PIN_FUNCTION(pri_mi2s), 1051 MSM_PIN_FUNCTION(pri_mi2s_ws), 1052 MSM_PIN_FUNCTION(prng_rosc), 1053 MSM_PIN_FUNCTION(qdss_cti), 1054 MSM_PIN_FUNCTION(qdss), 1055 MSM_PIN_FUNCTION(qlink_enable), 1056 MSM_PIN_FUNCTION(qlink_request), 1057 MSM_PIN_FUNCTION(qua_mi2s), 1058 MSM_PIN_FUNCTION(qup0), 1059 MSM_PIN_FUNCTION(qup1), 1060 MSM_PIN_FUNCTION(qup10), 1061 MSM_PIN_FUNCTION(qup11), 1062 MSM_PIN_FUNCTION(qup12), 1063 MSM_PIN_FUNCTION(qup13), 1064 MSM_PIN_FUNCTION(qup14), 1065 MSM_PIN_FUNCTION(qup15), 1066 MSM_PIN_FUNCTION(qup2), 1067 MSM_PIN_FUNCTION(qup3), 1068 MSM_PIN_FUNCTION(qup4), 1069 MSM_PIN_FUNCTION(qup5), 1070 MSM_PIN_FUNCTION(qup6), 1071 MSM_PIN_FUNCTION(qup7), 1072 MSM_PIN_FUNCTION(qup8), 1073 MSM_PIN_FUNCTION(qup9), 1074 MSM_PIN_FUNCTION(qup_l4), 1075 MSM_PIN_FUNCTION(qup_l5), 1076 MSM_PIN_FUNCTION(qup_l6), 1077 MSM_PIN_FUNCTION(sdc4_clk), 1078 MSM_PIN_FUNCTION(sdc4_cmd), 1079 MSM_PIN_FUNCTION(sdc4_data), 1080 MSM_PIN_FUNCTION(sd_write), 1081 MSM_PIN_FUNCTION(sec_mi2s), 1082 MSM_PIN_FUNCTION(ter_mi2s), 1083 MSM_PIN_FUNCTION(tgu_ch0), 1084 MSM_PIN_FUNCTION(tgu_ch1), 1085 MSM_PIN_FUNCTION(tgu_ch2), 1086 MSM_PIN_FUNCTION(tgu_ch3), 1087 MSM_PIN_FUNCTION(tsif1_clk), 1088 MSM_PIN_FUNCTION(tsif1_data), 1089 MSM_PIN_FUNCTION(tsif1_en), 1090 MSM_PIN_FUNCTION(tsif1_error), 1091 MSM_PIN_FUNCTION(tsif1_sync), 1092 MSM_PIN_FUNCTION(tsif2_clk), 1093 MSM_PIN_FUNCTION(tsif2_data), 1094 MSM_PIN_FUNCTION(tsif2_en), 1095 MSM_PIN_FUNCTION(tsif2_error), 1096 MSM_PIN_FUNCTION(tsif2_sync), 1097 MSM_PIN_FUNCTION(uim1_clk), 1098 MSM_PIN_FUNCTION(uim1_data), 1099 MSM_PIN_FUNCTION(uim1_present), 1100 MSM_PIN_FUNCTION(uim1_reset), 1101 MSM_PIN_FUNCTION(uim2_clk), 1102 MSM_PIN_FUNCTION(uim2_data), 1103 MSM_PIN_FUNCTION(uim2_present), 1104 MSM_PIN_FUNCTION(uim2_reset), 1105 MSM_PIN_FUNCTION(uim_batt), 1106 MSM_PIN_FUNCTION(usb_phy), 1107 MSM_PIN_FUNCTION(vfr_1), 1108 MSM_PIN_FUNCTION(vsense_trigger), 1109 MSM_PIN_FUNCTION(wlan1_adc0), 1110 MSM_PIN_FUNCTION(wlan1_adc1), 1111 MSM_PIN_FUNCTION(wlan2_adc0), 1112 MSM_PIN_FUNCTION(wlan2_adc1), 1113 MSM_PIN_FUNCTION(wsa_clk), 1114 MSM_PIN_FUNCTION(wsa_data), 1115}; 1116 1117/* 1118 * Each pin is individually controlled by its own group and gpios that cannot 1119 * be requested are represented by the PINGROUP_DUMMY macro so that the group 1120 * numbers and names correspond to their respective gpio. These dummy pins do 1121 * not have a valid set of pinfuncs or a valid ctl_reg and should not be 1122 * requested. 1123 */ 1124static const struct msm_pingroup sdm670_groups[] = { 1125 PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _), 1126 PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _), 1127 PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _), 1128 PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _), 1129 PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), 1130 PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _), 1131 PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _), 1132 PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _), 1133 PINGROUP(8, WEST, qup_l4, gp_pdm1, ddr_bist, _, _, _, _, _, _), 1134 PINGROUP(9, WEST, qup_l5, ddr_bist, _, _, _, _, _, _, _), 1135 PINGROUP(10, NORTH, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _), 1136 PINGROUP(11, NORTH, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _), 1137 PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _), 1138 PINGROUP(13, WEST, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _), 1139 PINGROUP(14, WEST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), 1140 PINGROUP(15, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), 1141 PINGROUP(16, WEST, cam_mclk, qdss, _, _, _, _, _, _, _), 1142 PINGROUP(17, WEST, cci_i2c, qup1, qdss, _, _, _, _, _, _), 1143 PINGROUP(18, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), 1144 PINGROUP(19, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), 1145 PINGROUP(20, WEST, cci_i2c, qup1, _, qdss, _, _, _, _, _), 1146 PINGROUP(21, WEST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _), 1147 PINGROUP(22, WEST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _), 1148 PINGROUP(23, WEST, cci_timer2, qdss, _, _, _, _, _, _, _), 1149 PINGROUP(24, WEST, cci_timer3, cci_async, qdss, _, _, _, _, _, _), 1150 PINGROUP(25, WEST, cci_timer4, cci_async, qdss, _, _, _, _, _, _), 1151 PINGROUP(26, WEST, cci_async, qdss, jitter_bist, _, _, _, _, _, _), 1152 PINGROUP(27, WEST, qup2, qdss, pll_bist, _, _, _, _, _, _), 1153 PINGROUP(28, WEST, qup2, qdss, agera_pll, _, _, _, _, _, _), 1154 PINGROUP(29, WEST, qup2, _, phase_flag, qdss, atest_tsens, _, _, _, _), 1155 PINGROUP(30, WEST, qup2, phase_flag, qdss, _, _, _, _, _, _), 1156 PINGROUP(31, WEST, qup11, qup14, _, _, _, _, _, _, _), 1157 PINGROUP(32, WEST, qup11, qup14, _, _, _, _, _, _, _), 1158 PINGROUP(33, WEST, qup11, qup14, _, _, _, _, _, _, _), 1159 PINGROUP(34, WEST, qup11, qup14, _, _, _, _, _, _, _), 1160 PINGROUP(35, NORTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _), 1161 PINGROUP(36, NORTH, pci_e0, qup_l5, pll_bist, _, _, _, _, _, _), 1162 PINGROUP(37, NORTH, qup_l6, agera_pll, _, _, _, _, _, _, _), 1163 PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _), 1164 PINGROUP(39, NORTH, lpass_slimbus, _, _, _, _, _, _, _, _), 1165 PINGROUP(40, NORTH, sd_write, tsif1_error, _, _, _, _, _, _, _), 1166 PINGROUP(41, SOUTH, qup3, _, qdss, _, _, _, _, _, _), 1167 PINGROUP(42, SOUTH, qup3, _, qdss, _, _, _, _, _, _), 1168 PINGROUP(43, SOUTH, qup3, _, qdss, _, _, _, _, _, _), 1169 PINGROUP(44, SOUTH, qup3, _, qdss, _, _, _, _, _, _), 1170 PINGROUP(45, SOUTH, qup6, _, _, _, _, _, _, _, _), 1171 PINGROUP(46, SOUTH, qup6, _, _, _, _, _, _, _, _), 1172 PINGROUP(47, SOUTH, qup6, _, _, _, _, _, _, _, _), 1173 PINGROUP(48, SOUTH, qup6, _, _, _, _, _, _, _, _), 1174 PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _), 1175 PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _), 1176 PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), 1177 PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _), 1178 PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), 1179 PINGROUP(54, NORTH, qup10, gp_pdm0, phase_flag, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), 1180 PINGROUP(55, NORTH, qup10, phase_flag, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _), 1181 PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _), 1182 PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _), 1183 PINGROUP_DUMMY(58), 1184 PINGROUP_DUMMY(59), 1185 PINGROUP_DUMMY(60), 1186 PINGROUP_DUMMY(61), 1187 PINGROUP_DUMMY(62), 1188 PINGROUP_DUMMY(63), 1189 PINGROUP_DUMMY(64), 1190 PINGROUP(65, NORTH, pri_mi2s, qup8, wsa_clk, _, _, _, _, _, _), 1191 PINGROUP(66, NORTH, pri_mi2s_ws, qup8, wsa_data, gp_pdm1, _, _, _, _, _), 1192 PINGROUP(67, NORTH, pri_mi2s, qup8, _, atest_usb2, _, _, _, _, _), 1193 PINGROUP(68, NORTH, pri_mi2s, qup8, _, atest_usb23, _, _, _, _, _), 1194 PINGROUP_DUMMY(69), 1195 PINGROUP_DUMMY(70), 1196 PINGROUP_DUMMY(71), 1197 PINGROUP_DUMMY(72), 1198 PINGROUP_DUMMY(73), 1199 PINGROUP_DUMMY(74), 1200 PINGROUP(75, NORTH, ter_mi2s, phase_flag, qdss, atest_usb22, qup_l4, _, _, _, _), 1201 PINGROUP(76, NORTH, ter_mi2s, phase_flag, qdss, atest_usb21, qup_l5, _, _, _, _), 1202 PINGROUP(77, NORTH, ter_mi2s, phase_flag, qdss, atest_usb20, qup_l6, _, _, _, _), 1203 PINGROUP(78, NORTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _), 1204 PINGROUP(79, NORTH, sec_mi2s, gp_pdm2, _, qdss, _, _, _, _, _), 1205 PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _), 1206 PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), 1207 PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), 1208 PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _), 1209 PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _), 1210 PINGROUP(85, SOUTH, qup5, _, _, _, _, _, _, _, _), 1211 PINGROUP(86, SOUTH, qup5, copy_gp, _, _, _, _, _, _, _), 1212 PINGROUP(87, SOUTH, qup5, _, _, _, _, _, _, _, _), 1213 PINGROUP(88, SOUTH, qup5, _, _, _, _, _, _, _, _), 1214 PINGROUP(89, SOUTH, tsif1_clk, qup4, tgu_ch3, phase_flag, _, _, _, _, _), 1215 PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti), 1216 PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, tgu_ch1, _, qdss_cti, _, _, _), 1217 PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, vfr_1, tgu_ch2, _, _, _, _), 1218 PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, _, qdss, _, _, _, _), 1219 PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, _, _, _, _, _, _), 1220 PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, gp_pdm0, _, _, _, _, _), 1221 PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _), 1222 PINGROUP(97, WEST, _, _, mdp_vsync, ldo_en, _, _, _, _, _), 1223 PINGROUP(98, WEST, _, mdp_vsync, ldo_update, _, _, _, _, _, _), 1224 PINGROUP(99, NORTH, phase_flag, prng_rosc, _, _, _, _, _, _, _), 1225 PINGROUP(100, WEST, phase_flag, _, _, _, _, _, _, _, _), 1226 PINGROUP(101, WEST, _, phase_flag, _, _, _, _, _, _, _), 1227 PINGROUP(102, WEST, pci_e1, prng_rosc, _, _, _, _, _, _, _), 1228 PINGROUP(103, WEST, pci_e1, copy_phase, _, _, _, _, _, _, _), 1229 PINGROUP_DUMMY(104), 1230 PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _), 1231 PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _), 1232 PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _), 1233 PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _), 1234 PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _), 1235 PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _), 1236 PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _), 1237 PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _), 1238 PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _), 1239 PINGROUP(114, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), 1240 PINGROUP(115, WEST, _, nav_pps, nav_pps, gps_tx, _, _, _, _, _), 1241 PINGROUP(116, SOUTH, _, _, _, _, _, _, _, _, _), 1242 PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _), 1243 PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _), 1244 PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _), 1245 PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _), 1246 PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _), 1247 PINGROUP(122, NORTH, _, qdss, _, _, _, _, _, _, _), 1248 PINGROUP(123, NORTH, qup_l4, _, qdss, _, _, _, _, _, _), 1249 PINGROUP(124, NORTH, qup_l5, _, qdss, _, _, _, _, _, _), 1250 PINGROUP(125, NORTH, qup_l6, _, _, _, _, _, _, _, _), 1251 PINGROUP(126, NORTH, _, _, _, _, _, _, _, _, _), 1252 PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _), 1253 PINGROUP(128, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), 1254 PINGROUP(129, WEST, nav_pps, nav_pps, gps_tx, _, _, _, _, _, _), 1255 PINGROUP(130, WEST, qlink_request, _, _, _, _, _, _, _, _), 1256 PINGROUP(131, WEST, qlink_enable, _, _, _, _, _, _, _, _), 1257 PINGROUP(132, WEST, _, _, _, _, _, _, _, _, _), 1258 PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _), 1259 PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _), 1260 PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _), 1261 PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _), 1262 PINGROUP(137, WEST, _, _, phase_flag, _, _, _, _, _, _), 1263 PINGROUP(138, WEST, _, _, phase_flag, _, _, _, _, _, _), 1264 PINGROUP(139, WEST, _, phase_flag, _, _, _, _, _, _, _), 1265 PINGROUP(140, WEST, _, _, phase_flag, _, _, _, _, _, _), 1266 PINGROUP(141, WEST, _, phase_flag, _, _, _, _, _, _, _), 1267 PINGROUP(142, WEST, _, phase_flag, _, _, _, _, _, _, _), 1268 PINGROUP(143, WEST, _, nav_pps, nav_pps, gps_tx, phase_flag, _, _, _, _), 1269 PINGROUP(144, SOUTH, mss_lte, _, _, _, _, _, _, _, _), 1270 PINGROUP(145, SOUTH, mss_lte, gps_tx, _, _, _, _, _, _, _), 1271 PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), 1272 PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), 1273 PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), 1274 PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), 1275 UFS_RESET(ufs_reset, 0x99d000), 1276 SDC_QDSD_PINGROUP(sdc1_rclk, 0x99000, 15, 0), 1277 SDC_QDSD_PINGROUP(sdc1_clk, 0x99000, 13, 6), 1278 SDC_QDSD_PINGROUP(sdc1_cmd, 0x99000, 11, 3), 1279 SDC_QDSD_PINGROUP(sdc1_data, 0x99000, 9, 0), 1280 SDC_QDSD_PINGROUP(sdc2_clk, 0x9a000, 14, 6), 1281 SDC_QDSD_PINGROUP(sdc2_cmd, 0x9a000, 11, 3), 1282 SDC_QDSD_PINGROUP(sdc2_data, 0x9a000, 9, 0), 1283}; 1284 1285static const int sdm670_reserved_gpios[] = { 1286 58, 59, 60, 61, 62, 63, 64, 69, 70, 71, 72, 73, 74, 104, -1 1287}; 1288 1289static const struct msm_gpio_wakeirq_map sdm670_pdc_map[] = { 1290 { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 }, 1291 { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 }, 1292 { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 }, 1293 { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 }, 1294 { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 }, 1295 { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 66, 66 }, 1296 { 68, 67 }, { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, 1297 { 84, 74 }, { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, 1298 { 91, 79 }, { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, 1299 { 101, 84 }, { 103, 85 }, { 115, 90 }, { 116, 91 }, { 117, 92 }, 1300 { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 }, 1301 { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 }, 1302 { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 }, 1303}; 1304 1305static const struct msm_pinctrl_soc_data sdm670_pinctrl = { 1306 .pins = sdm670_pins, 1307 .npins = ARRAY_SIZE(sdm670_pins), 1308 .functions = sdm670_functions, 1309 .nfunctions = ARRAY_SIZE(sdm670_functions), 1310 .groups = sdm670_groups, 1311 .ngroups = ARRAY_SIZE(sdm670_groups), 1312 .ngpios = 151, 1313 .reserved_gpios = sdm670_reserved_gpios, 1314 .wakeirq_map = sdm670_pdc_map, 1315 .nwakeirq_map = ARRAY_SIZE(sdm670_pdc_map), 1316 .wakeirq_dual_edge_errata = true, 1317}; 1318 1319static int sdm670_pinctrl_probe(struct platform_device *pdev) 1320{ 1321 return msm_pinctrl_probe(pdev, &sdm670_pinctrl); 1322} 1323 1324static const struct of_device_id sdm670_pinctrl_of_match[] = { 1325 { .compatible = "qcom,sdm670-tlmm", }, 1326 { }, 1327}; 1328MODULE_DEVICE_TABLE(of, sdm670_pinctrl_of_match); 1329 1330static struct platform_driver sdm670_pinctrl_driver = { 1331 .driver = { 1332 .name = "sdm670-pinctrl", 1333 .of_match_table = sdm670_pinctrl_of_match, 1334 }, 1335 .probe = sdm670_pinctrl_probe, 1336}; 1337 1338static int __init sdm670_pinctrl_init(void) 1339{ 1340 return platform_driver_register(&sdm670_pinctrl_driver); 1341} 1342arch_initcall(sdm670_pinctrl_init); 1343 1344static void __exit sdm670_pinctrl_exit(void) 1345{ 1346 platform_driver_unregister(&sdm670_pinctrl_driver); 1347} 1348module_exit(sdm670_pinctrl_exit); 1349 1350MODULE_DESCRIPTION("Qualcomm SDM670 TLMM pinctrl driver"); 1351MODULE_LICENSE("GPL");