tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef DEBUG_H
18#define DEBUG_H
19
20#include "hw.h"
21#include "dfs_debug.h"
22
23struct ath_txq;
24struct ath_buf;
25struct fft_sample_tlv;
26
27#ifdef CONFIG_ATH9K_DEBUGFS
28#define TX_STAT_INC(sc, q, c) do { (sc)->debug.stats.txstats[q].c++; } while (0)
29#define RX_STAT_INC(sc, c) do { (sc)->debug.stats.rxstats.c++; } while (0)
30#define RESET_STAT_INC(sc, type) do { (sc)->debug.stats.reset[type]++; } while (0)
31#define ANT_STAT_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].c++; } while (0)
32#define ANT_LNA_INC(sc, i, c) do { (sc)->debug.stats.ant_stats[i].lna_recv_cnt[c]++; } while (0)
33#else
34#define TX_STAT_INC(sc, q, c) do { (void)(sc); } while (0)
35#define RX_STAT_INC(sc, c) do { (void)(sc); } while (0)
36#define RESET_STAT_INC(sc, type) do { (void)(sc); } while (0)
37#define ANT_STAT_INC(sc, i, c) do { (void)(sc); } while (0)
38#define ANT_LNA_INC(sc, i, c) do { (void)(sc); } while (0)
39#endif
40
41enum ath_reset_type {
42 RESET_TYPE_USER,
43 RESET_TYPE_BB_HANG,
44 RESET_TYPE_BB_WATCHDOG,
45 RESET_TYPE_FATAL_INT,
46 RESET_TYPE_TX_ERROR,
47 RESET_TYPE_TX_GTT,
48 RESET_TYPE_TX_HANG,
49 RESET_TYPE_PLL_HANG,
50 RESET_TYPE_MAC_HANG,
51 RESET_TYPE_BEACON_STUCK,
52 RESET_TYPE_MCI,
53 RESET_TYPE_CALIBRATION,
54 RESET_TX_DMA_ERROR,
55 RESET_RX_DMA_ERROR,
56 RESET_TYPE_RX_INACTIVE,
57 __RESET_TYPE_MAX
58};
59
60#ifdef CONFIG_ATH9K_DEBUGFS
61
62/**
63 * struct ath_interrupt_stats - Contains statistics about interrupts
64 * @total: Total no. of interrupts generated so far
65 * @rxok: RX with no errors
66 * @rxlp: RX with low priority RX
67 * @rxhp: RX with high priority, uapsd only
68 * @rxeol: RX with no more RXDESC available
69 * @rxorn: RX FIFO overrun
70 * @txok: TX completed at the requested rate
71 * @txurn: TX FIFO underrun
72 * @mib: MIB regs reaching its threshold
73 * @rxphyerr: RX with phy errors
74 * @rx_keycache_miss: RX with key cache misses
75 * @swba: Software Beacon Alert
76 * @bmiss: Beacon Miss
77 * @bnr: Beacon Not Ready
78 * @cst: Carrier Sense TImeout
79 * @gtt: Global TX Timeout
80 * @tim: RX beacon TIM occurrence
81 * @cabend: RX End of CAB traffic
82 * @dtimsync: DTIM sync lossage
83 * @dtim: RX Beacon with DTIM
84 * @bb_watchdog: Baseband watchdog
85 * @tsfoor: TSF out of range, indicates that the corrected TSF received
86 * from a beacon differs from the PCU's internal TSF by more than a
87 * (programmable) threshold
88 * @local_timeout: Internal bus timeout.
89 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
90 * @gen_timer: Generic hardware timer interrupt
91 */
92struct ath_interrupt_stats {
93 u32 total;
94 u32 rxok;
95 u32 rxlp;
96 u32 rxhp;
97 u32 rxeol;
98 u32 rxorn;
99 u32 txok;
100 u32 txeol;
101 u32 txurn;
102 u32 mib;
103 u32 rxphyerr;
104 u32 rx_keycache_miss;
105 u32 swba;
106 u32 bmiss;
107 u32 bnr;
108 u32 cst;
109 u32 gtt;
110 u32 tim;
111 u32 cabend;
112 u32 dtimsync;
113 u32 dtim;
114 u32 bb_watchdog;
115 u32 tsfoor;
116 u32 mci;
117 u32 gen_timer;
118
119 /* Sync-cause stats */
120 u32 sync_cause_all;
121 u32 sync_rtc_irq;
122 u32 sync_mac_irq;
123 u32 eeprom_illegal_access;
124 u32 apb_timeout;
125 u32 pci_mode_conflict;
126 u32 host1_fatal;
127 u32 host1_perr;
128 u32 trcv_fifo_perr;
129 u32 radm_cpl_ep;
130 u32 radm_cpl_dllp_abort;
131 u32 radm_cpl_tlp_abort;
132 u32 radm_cpl_ecrc_err;
133 u32 radm_cpl_timeout;
134 u32 local_timeout;
135 u32 pm_access;
136 u32 mac_awake;
137 u32 mac_asleep;
138 u32 mac_sleep_access;
139};
140
141
142/**
143 * struct ath_tx_stats - Statistics about TX
144 * @tx_pkts_all: No. of total frames transmitted, including ones that
145 * may have had errors.
146 * @tx_bytes_all: No. of total bytes transmitted, including ones that
147 * may have had errors.
148 * @queued: Total MPDUs (non-aggr) queued
149 * @completed: Total MPDUs (non-aggr) completed
150 * @xretries: Total MPDUs with xretries
151 * @a_aggr: Total no. of aggregates queued
152 * @a_queued_hw: Total AMPDUs queued to hardware
153 * @a_completed: Total AMPDUs completed
154 * @a_retries: No. of AMPDUs retried (SW)
155 * @a_xretries: No. of AMPDUs dropped due to xretries
156 * @txerr_filtered: No. of frames with TXERR_FILT flag set.
157 * @fifo_underrun: FIFO underrun occurrences
158 * Valid only for:
159 * - non-aggregate condition.
160 * - first packet of aggregate.
161 * @xtxop: No. of frames filtered because of TXOP limit
162 * @timer_exp: Transmit timer expiry
163 * @desc_cfg_err: Descriptor configuration errors
164 * @data_underrun: TX data underrun errors
165 * @delim_underrun: TX delimiter underrun errors
166 * @puttxbuf: Number of times hardware was given txbuf to write.
167 * @txstart: Number of times hardware was told to start tx.
168 * @txprocdesc: Number of times tx descriptor was processed
169 * @txfailed: Out-of-memory or other errors in xmit path.
170 */
171struct ath_tx_stats {
172 u32 tx_pkts_all;
173 u32 tx_bytes_all;
174 u32 queued;
175 u32 completed;
176 u32 xretries;
177 u32 a_aggr;
178 u32 a_queued_hw;
179 u32 a_completed;
180 u32 a_retries;
181 u32 a_xretries;
182 u32 txerr_filtered;
183 u32 fifo_underrun;
184 u32 xtxop;
185 u32 timer_exp;
186 u32 desc_cfg_err;
187 u32 data_underrun;
188 u32 delim_underrun;
189 u32 puttxbuf;
190 u32 txstart;
191 u32 txprocdesc;
192 u32 txfailed;
193};
194
195/*
196 * Various utility macros to print TX/Queue counters.
197 */
198#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
199#define TXSTATS sc->debug.stats.txstats
200#define PR(str, elem) \
201 do { \
202 seq_printf(file, "%s%13u%11u%10u%10u\n", str, \
203 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
204 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
205 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
206 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
207 } while(0)
208
209struct ath_rx_rate_stats {
210 struct {
211 u32 ht20_cnt;
212 u32 ht40_cnt;
213 u32 sgi_cnt;
214 u32 lgi_cnt;
215 } ht_stats[24];
216
217 struct {
218 u32 ofdm_cnt;
219 } ofdm_stats[8];
220
221 struct {
222 u32 cck_lp_cnt;
223 u32 cck_sp_cnt;
224 } cck_stats[4];
225};
226
227struct ath_airtime_stats {
228 u32 rx_airtime;
229 u32 tx_airtime;
230};
231
232#define ANT_MAIN 0
233#define ANT_ALT 1
234
235struct ath_antenna_stats {
236 u32 recv_cnt;
237 u32 rssi_avg;
238 u32 lna_recv_cnt[4];
239 u32 lna_attempt_cnt[4];
240};
241
242struct ath_stats {
243 struct ath_interrupt_stats istats;
244 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
245 struct ath_rx_stats rxstats;
246 struct ath_dfs_stats dfs_stats;
247 struct ath_antenna_stats ant_stats[2];
248 u32 reset[__RESET_TYPE_MAX];
249};
250
251struct ath9k_debug {
252 struct dentry *debugfs_phy;
253 u32 regidx;
254 struct ath_stats stats;
255};
256
257int ath9k_init_debug(struct ath_hw *ah);
258void ath9k_deinit_debug(struct ath_softc *sc);
259
260void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
261void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
262 struct ath_tx_status *ts, struct ath_txq *txq,
263 unsigned int flags);
264void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
265int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
266 struct ieee80211_vif *vif, int sset);
267void ath9k_get_et_stats(struct ieee80211_hw *hw,
268 struct ieee80211_vif *vif,
269 struct ethtool_stats *stats, u64 *data);
270void ath9k_get_et_strings(struct ieee80211_hw *hw,
271 struct ieee80211_vif *vif,
272 u32 sset, u8 *data);
273void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
274 struct ieee80211_vif *vif,
275 struct ieee80211_sta *sta,
276 struct dentry *dir);
277void ath9k_debug_stat_ant(struct ath_softc *sc,
278 struct ath_hw_antcomb_conf *div_ant_conf,
279 int main_rssi_avg, int alt_rssi_avg);
280void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
281
282#else
283
284static inline int ath9k_init_debug(struct ath_hw *ah)
285{
286 return 0;
287}
288
289static inline void ath9k_deinit_debug(struct ath_softc *sc)
290{
291}
292static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
293 enum ath9k_int status)
294{
295}
296static inline void ath_debug_stat_tx(struct ath_softc *sc,
297 struct ath_buf *bf,
298 struct ath_tx_status *ts,
299 struct ath_txq *txq,
300 unsigned int flags)
301{
302}
303static inline void ath_debug_stat_rx(struct ath_softc *sc,
304 struct ath_rx_status *rs)
305{
306}
307static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
308 struct ath_hw_antcomb_conf *div_ant_conf,
309 int main_rssi_avg, int alt_rssi_avg)
310{
311
312}
313
314static inline void
315ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
316{
317}
318
319#endif /* CONFIG_ATH9K_DEBUGFS */
320
321#ifdef CONFIG_ATH9K_STATION_STATISTICS
322void ath_debug_rate_stats(struct ath_softc *sc,
323 struct ath_rx_status *rs,
324 struct sk_buff *skb);
325#else
326static inline void ath_debug_rate_stats(struct ath_softc *sc,
327 struct ath_rx_status *rs,
328 struct sk_buff *skb)
329{
330}
331#endif /* CONFIG_ATH9K_STATION_STATISTICS */
332
333#endif /* DEBUG_H */