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Linux kernel mirror (for testing)
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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2025, Intel Corporation. */
3
4#ifndef _ICE_TSPLL_H_
5#define _ICE_TSPLL_H_
6
7/**
8 * struct ice_tspll_params_e82x - E82X TSPLL parameters
9 * @refclk_pre_div: Reference clock pre-divisor
10 * @post_pll_div: Post PLL divisor
11 * @feedback_div: Feedback divisor
12 * @frac_n_div: Fractional divisor
13 *
14 * Clock Generation Unit parameters used to program the PLL based on the
15 * selected TIME_REF/TCXO frequency.
16 */
17struct ice_tspll_params_e82x {
18 u8 refclk_pre_div;
19 u8 post_pll_div;
20 u8 feedback_div;
21 u32 frac_n_div;
22};
23
24#define ICE_CGU_NET_REF_CLK0 0x0
25#define ICE_CGU_REF_CLK_BYP0 0x5
26#define ICE_CGU_REF_CLK_BYP0_DIV 0x0
27#define ICE_CGU_REF_CLK_BYP1 0x4
28#define ICE_CGU_REF_CLK_BYP1_DIV 0x1
29
30#define ICE_TSPLL_CK_REFCLKFREQ_E825 0x1F
31#define ICE_TSPLL_NDIVRATIO_E825 5
32#define ICE_TSPLL_FBDIV_INTGR_E825 256
33
34int ice_tspll_cfg_pps_out_e825c(struct ice_hw *hw, bool enable);
35int ice_tspll_init(struct ice_hw *hw);
36int ice_tspll_bypass_mux_active_e825c(struct ice_hw *hw, u8 port, bool *active,
37 enum ice_synce_clk output);
38int ice_tspll_cfg_bypass_mux_e825c(struct ice_hw *hw, bool ena, u32 port_num,
39 enum ice_synce_clk output);
40int ice_tspll_cfg_synce_ethdiv_e825c(struct ice_hw *hw,
41 enum ice_synce_clk output);
42#endif /* _ICE_TSPLL_H_ */