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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6#ifndef __IRIS_PLATFORM_COMMON_H__
7#define __IRIS_PLATFORM_COMMON_H__
8
9#include <linux/bits.h>
10#include "iris_buffer.h"
11
12struct iris_core;
13struct iris_inst;
14
15#define IRIS_PAS_ID 9
16#define HW_RESPONSE_TIMEOUT_VALUE (1000) /* milliseconds */
17#define AUTOSUSPEND_DELAY_VALUE (HW_RESPONSE_TIMEOUT_VALUE + 500) /* milliseconds */
18
19#define REGISTER_BIT_DEPTH(luma, chroma) ((luma) << 16 | (chroma))
20#define BIT_DEPTH_8 REGISTER_BIT_DEPTH(8, 8)
21#define CODED_FRAMES_PROGRESSIVE 0x0
22#define DEFAULT_MAX_HOST_BUF_COUNT 64
23#define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256
24#define DEFAULT_FPS 30
25#define MAXIMUM_FPS 480
26#define NUM_MBS_8K ((8192 * 4352) / 256)
27#define MIN_QP_8BIT 1
28#define MAX_QP 51
29#define MAX_QP_HEVC 63
30#define DEFAULT_QP 20
31#define BITRATE_DEFAULT 20000000
32
33enum stage_type {
34 STAGE_1 = 1,
35 STAGE_2 = 2,
36};
37
38enum pipe_type {
39 PIPE_1 = 1,
40 PIPE_2 = 2,
41 PIPE_4 = 4,
42};
43
44extern const struct iris_platform_data qcs8300_data;
45extern const struct iris_platform_data sc7280_data;
46extern const struct iris_platform_data sm8250_data;
47extern const struct iris_platform_data sm8550_data;
48extern const struct iris_platform_data sm8650_data;
49extern const struct iris_platform_data sm8750_data;
50
51enum platform_clk_type {
52 IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
53 IRIS_CTRL_CLK,
54 IRIS_AHB_CLK,
55 IRIS_HW_CLK,
56 IRIS_HW_AHB_CLK,
57 IRIS_AXI1_CLK,
58 IRIS_CTRL_FREERUN_CLK,
59 IRIS_HW_FREERUN_CLK,
60 IRIS_BSE_HW_CLK,
61 IRIS_VPP0_HW_CLK,
62 IRIS_VPP1_HW_CLK,
63 IRIS_APV_HW_CLK,
64};
65
66struct platform_clk_data {
67 enum platform_clk_type clk_type;
68 const char *clk_name;
69};
70
71struct tz_cp_config {
72 u32 cp_start;
73 u32 cp_size;
74 u32 cp_nonpixel_start;
75 u32 cp_nonpixel_size;
76};
77
78struct ubwc_config_data {
79 u32 max_channels;
80 u32 mal_length;
81 u32 highest_bank_bit;
82 u32 bank_swzl_level;
83 u32 bank_swz2_level;
84 u32 bank_swz3_level;
85 u32 bank_spreading;
86};
87
88struct platform_inst_caps {
89 u32 min_frame_width;
90 u32 max_frame_width;
91 u32 min_frame_height;
92 u32 max_frame_height;
93 u32 max_mbpf;
94 u32 mb_cycles_vsp;
95 u32 mb_cycles_vpp;
96 u32 mb_cycles_fw;
97 u32 mb_cycles_fw_vpp;
98 u32 num_comv;
99 u32 max_frame_rate;
100 u32 max_operating_rate;
101};
102
103enum platform_inst_fw_cap_type {
104 PROFILE_H264 = 1,
105 PROFILE_HEVC,
106 PROFILE_VP9,
107 LEVEL_H264,
108 LEVEL_HEVC,
109 LEVEL_VP9,
110 PROFILE_AV1,
111 LEVEL_AV1,
112 TIER_AV1,
113 DRAP,
114 FILM_GRAIN,
115 SUPER_BLOCK,
116 ENH_LAYER_COUNT,
117 INPUT_BUF_HOST_MAX_COUNT,
118 OUTPUT_BUF_HOST_MAX_COUNT,
119 STAGE,
120 PIPE,
121 POC,
122 CODED_FRAMES,
123 BIT_DEPTH,
124 RAP_FRAME,
125 TIER,
126 HEADER_MODE,
127 PREPEND_SPSPPS_TO_IDR,
128 BITRATE,
129 BITRATE_PEAK,
130 BITRATE_MODE,
131 FRAME_SKIP_MODE,
132 FRAME_RC_ENABLE,
133 GOP_SIZE,
134 ENTROPY_MODE,
135 MIN_FRAME_QP_H264,
136 MIN_FRAME_QP_HEVC,
137 MAX_FRAME_QP_H264,
138 MAX_FRAME_QP_HEVC,
139 I_FRAME_MIN_QP_H264,
140 I_FRAME_MIN_QP_HEVC,
141 P_FRAME_MIN_QP_H264,
142 P_FRAME_MIN_QP_HEVC,
143 B_FRAME_MIN_QP_H264,
144 B_FRAME_MIN_QP_HEVC,
145 I_FRAME_MAX_QP_H264,
146 I_FRAME_MAX_QP_HEVC,
147 P_FRAME_MAX_QP_H264,
148 P_FRAME_MAX_QP_HEVC,
149 B_FRAME_MAX_QP_H264,
150 B_FRAME_MAX_QP_HEVC,
151 I_FRAME_QP_H264,
152 I_FRAME_QP_HEVC,
153 P_FRAME_QP_H264,
154 P_FRAME_QP_HEVC,
155 B_FRAME_QP_H264,
156 B_FRAME_QP_HEVC,
157 ROTATION,
158 HFLIP,
159 VFLIP,
160 IR_TYPE,
161 IR_PERIOD,
162 INST_FW_CAP_MAX,
163};
164
165enum platform_inst_fw_cap_flags {
166 CAP_FLAG_DYNAMIC_ALLOWED = BIT(0),
167 CAP_FLAG_MENU = BIT(1),
168 CAP_FLAG_INPUT_PORT = BIT(2),
169 CAP_FLAG_OUTPUT_PORT = BIT(3),
170 CAP_FLAG_CLIENT_SET = BIT(4),
171 CAP_FLAG_BITMASK = BIT(5),
172 CAP_FLAG_VOLATILE = BIT(6),
173};
174
175struct platform_inst_fw_cap {
176 enum platform_inst_fw_cap_type cap_id;
177 s64 min;
178 s64 max;
179 s64 step_or_mask;
180 s64 value;
181 u32 hfi_id;
182 enum platform_inst_fw_cap_flags flags;
183 int (*set)(struct iris_inst *inst,
184 enum platform_inst_fw_cap_type cap_id);
185};
186
187struct bw_info {
188 u32 mbs_per_sec;
189 u32 bw_ddr;
190};
191
192struct iris_core_power {
193 u64 clk_freq;
194 u64 icc_bw;
195};
196
197struct iris_inst_power {
198 u64 min_freq;
199 u32 icc_bw;
200};
201
202struct icc_vote_data {
203 u32 height, width;
204 u32 fps;
205};
206
207enum platform_pm_domain_type {
208 IRIS_CTRL_POWER_DOMAIN,
209 IRIS_HW_POWER_DOMAIN,
210 IRIS_VPP0_HW_POWER_DOMAIN,
211 IRIS_VPP1_HW_POWER_DOMAIN,
212 IRIS_APV_HW_POWER_DOMAIN,
213};
214
215struct iris_platform_data {
216 void (*init_hfi_command_ops)(struct iris_core *core);
217 void (*init_hfi_response_ops)(struct iris_core *core);
218 struct iris_inst *(*get_instance)(void);
219 u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type buffer_type);
220 const struct vpu_ops *vpu_ops;
221 void (*set_preset_registers)(struct iris_core *core);
222 const struct icc_info *icc_tbl;
223 unsigned int icc_tbl_size;
224 const struct bw_info *bw_tbl_dec;
225 unsigned int bw_tbl_dec_size;
226 const char * const *pmdomain_tbl;
227 unsigned int pmdomain_tbl_size;
228 const char * const *opp_pd_tbl;
229 unsigned int opp_pd_tbl_size;
230 const struct platform_clk_data *clk_tbl;
231 const char * const *opp_clk_tbl;
232 unsigned int clk_tbl_size;
233 const char * const *clk_rst_tbl;
234 unsigned int clk_rst_tbl_size;
235 const char * const *controller_rst_tbl;
236 unsigned int controller_rst_tbl_size;
237 u64 dma_mask;
238 const char *fwname;
239 u32 pas_id;
240 struct iris_fmt *inst_iris_fmts;
241 u32 inst_iris_fmts_size;
242 struct platform_inst_caps *inst_caps;
243 const struct platform_inst_fw_cap *inst_fw_caps_dec;
244 u32 inst_fw_caps_dec_size;
245 const struct platform_inst_fw_cap *inst_fw_caps_enc;
246 u32 inst_fw_caps_enc_size;
247 const struct tz_cp_config *tz_cp_config_data;
248 u32 tz_cp_config_data_size;
249 u32 core_arch;
250 u32 hw_response_timeout;
251 struct ubwc_config_data *ubwc_config;
252 u32 num_vpp_pipe;
253 bool no_aon;
254 u32 max_session_count;
255 /* max number of macroblocks per frame supported */
256 u32 max_core_mbpf;
257 /* max number of macroblocks per second supported */
258 u32 max_core_mbps;
259 const u32 *dec_input_config_params_default;
260 unsigned int dec_input_config_params_default_size;
261 const u32 *dec_input_config_params_hevc;
262 unsigned int dec_input_config_params_hevc_size;
263 const u32 *dec_input_config_params_vp9;
264 unsigned int dec_input_config_params_vp9_size;
265 const u32 *dec_input_config_params_av1;
266 unsigned int dec_input_config_params_av1_size;
267 const u32 *dec_output_config_params;
268 unsigned int dec_output_config_params_size;
269 const u32 *enc_input_config_params;
270 unsigned int enc_input_config_params_size;
271 const u32 *enc_output_config_params;
272 unsigned int enc_output_config_params_size;
273 const u32 *dec_input_prop;
274 unsigned int dec_input_prop_size;
275 const u32 *dec_output_prop_avc;
276 unsigned int dec_output_prop_avc_size;
277 const u32 *dec_output_prop_hevc;
278 unsigned int dec_output_prop_hevc_size;
279 const u32 *dec_output_prop_vp9;
280 unsigned int dec_output_prop_vp9_size;
281 const u32 *dec_output_prop_av1;
282 unsigned int dec_output_prop_av1_size;
283 const u32 *dec_ip_int_buf_tbl;
284 unsigned int dec_ip_int_buf_tbl_size;
285 const u32 *dec_op_int_buf_tbl;
286 unsigned int dec_op_int_buf_tbl_size;
287 const u32 *enc_ip_int_buf_tbl;
288 unsigned int enc_ip_int_buf_tbl_size;
289 const u32 *enc_op_int_buf_tbl;
290 unsigned int enc_op_int_buf_tbl_size;
291};
292
293#endif