tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Holmes Chiou <holmes.chiou@mediatek.com>
5 * Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
6 */
7
8#ifndef __MTK_IMG_IPI_H__
9#define __MTK_IMG_IPI_H__
10
11#include <linux/err.h>
12#include "mdp_sm_mt8183.h"
13#include "mdp_sm_mt8195.h"
14#include "mtk-mdp3-type.h"
15
16/* ISP-MDP generic input information */
17
18#define IMG_IPI_INIT 1
19#define IMG_IPI_DEINIT 2
20#define IMG_IPI_FRAME 3
21#define IMG_IPI_DEBUG 4
22
23struct img_timeval {
24 u32 tv_sec;
25 u32 tv_usec;
26} __packed;
27
28struct img_addr {
29 u64 va; /* Used for Linux OS access */
30 u32 pa; /* Used for CM4 access */
31 u32 iova; /* Used for IOMMU HW access */
32} __packed;
33
34struct tuning_addr {
35 u64 present;
36 u32 pa; /* Used for CM4 access */
37 u32 iova; /* Used for IOMMU HW access */
38} __packed;
39
40struct img_sw_addr {
41 u64 va; /* Used for APMCU access */
42 u32 pa; /* Used for CM4 access */
43} __packed;
44
45struct img_plane_format {
46 u32 size;
47 u32 stride;
48} __packed;
49
50struct img_pix_format {
51 u32 width;
52 u32 height;
53 u32 colorformat; /* enum mdp_color */
54 u32 ycbcr_prof; /* enum mdp_ycbcr_profile */
55 struct img_plane_format plane_fmt[IMG_MAX_PLANES];
56} __packed;
57
58struct img_image_buffer {
59 struct img_pix_format format;
60 u32 iova[IMG_MAX_PLANES];
61 /* enum mdp_buffer_usage, FD or advanced ISP usages */
62 u32 usage;
63} __packed;
64
65#define IMG_SUBPIXEL_SHIFT 20
66
67#define IMG_CTRL_FLAG_HFLIP BIT(0)
68#define IMG_CTRL_FLAG_DITHER BIT(1)
69#define IMG_CTRL_FLAG_SHARPNESS BIT(4)
70#define IMG_CTRL_FLAG_HDR BIT(5)
71#define IMG_CTRL_FLAG_DRE BIT(6)
72
73struct img_input {
74 struct img_image_buffer buffer;
75 u32 flags; /* HDR, DRE, dither */
76} __packed;
77
78struct img_output {
79 struct img_image_buffer buffer;
80 struct img_crop crop;
81 s32 rotation;
82 u32 flags; /* H-flip, sharpness, dither */
83} __packed;
84
85struct img_ipi_frameparam {
86 u32 index;
87 u32 frame_no;
88 struct img_timeval timestamp;
89 u32 type; /* enum mdp_stream_type */
90 u32 state;
91 u32 num_inputs;
92 u32 num_outputs;
93 u64 drv_data;
94 struct img_input inputs[IMG_MAX_HW_INPUTS];
95 struct img_output outputs[IMG_MAX_HW_OUTPUTS];
96 struct tuning_addr tuning_data;
97 struct img_addr subfrm_data;
98 struct img_sw_addr config_data;
99 struct img_sw_addr self_data;
100} __packed;
101
102struct img_sw_buffer {
103 u64 handle; /* Used for APMCU access */
104 u32 scp_addr; /* Used for CM4 access */
105} __packed;
106
107struct img_ipi_param {
108 u32 usage;
109 struct img_sw_buffer frm_param;
110} __packed;
111
112struct img_frameparam {
113 struct list_head list_entry;
114 struct img_ipi_frameparam frameparam;
115} __packed;
116
117/* Platform config indicator */
118#define MT8183 8183
119#define MT8188 8195
120#define MT8195 8195
121
122#define CFG_CHECK(plat, p_id) ((plat) == (p_id))
123
124#define _CFG_OFST(plat, cfg, ofst) ((void *)(&((cfg)->config_##plat) + (ofst)))
125#define CFG_OFST(plat, cfg, ofst) \
126 (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_OFST(plat, cfg, ofst))
127
128#define _CFG_ADDR(plat, cfg, mem) (&((cfg)->config_##plat.mem))
129#define CFG_ADDR(plat, cfg, mem) \
130 (IS_ERR_OR_NULL(cfg) ? NULL : _CFG_ADDR(plat, cfg, mem))
131
132#define _CFG_GET(plat, cfg, mem) ((cfg)->config_##plat.mem)
133#define CFG_GET(plat, cfg, mem) \
134 (IS_ERR_OR_NULL(cfg) ? 0 : _CFG_GET(plat, cfg, mem))
135
136#define _CFG_COMP(plat, comp, mem) ((comp)->comp_##plat.mem)
137#define CFG_COMP(plat, comp, mem) \
138 (IS_ERR_OR_NULL(comp) ? 0 : _CFG_COMP(plat, comp, mem))
139
140struct img_config {
141 union {
142 struct img_config_8183 config_8183;
143 struct img_config_8195 config_8195;
144 };
145} __packed;
146
147struct img_compparam {
148 union {
149 struct img_compparam_8183 comp_8183;
150 struct img_compparam_8195 comp_8195;
151 };
152} __packed;
153
154#endif /* __MTK_IMG_IPI_H__ */