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Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Abilis Systems interrupt controller driver
4 *
5 * Copyright (C) Abilis Systems 2012
6 *
7 * Author: Christian Ruppert <christian.ruppert@abilis.com>
8 */
9
10#include <linux/interrupt.h>
11#include <linux/irqdomain.h>
12#include <linux/irq.h>
13#include <linux/irqchip.h>
14#include <linux/of_irq.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/bitops.h>
19
20#define AB_IRQCTL_INT_ENABLE 0x00
21#define AB_IRQCTL_INT_STATUS 0x04
22#define AB_IRQCTL_SRC_MODE 0x08
23#define AB_IRQCTL_SRC_POLARITY 0x0C
24#define AB_IRQCTL_INT_MODE 0x10
25#define AB_IRQCTL_INT_POLARITY 0x14
26#define AB_IRQCTL_INT_FORCE 0x18
27
28#define AB_IRQCTL_MAXIRQ 32
29
30static inline void ab_irqctl_writereg(struct irq_chip_generic *gc, u32 reg,
31 u32 val)
32{
33 irq_reg_writel(gc, val, reg);
34}
35
36static inline u32 ab_irqctl_readreg(struct irq_chip_generic *gc, u32 reg)
37{
38 return irq_reg_readl(gc, reg);
39}
40
41static int tb10x_irq_set_type(struct irq_data *data, unsigned int flow_type)
42{
43 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
44 uint32_t mod, pol, im = data->mask;
45
46 guard(raw_spinlock)(&gc->lock);
47
48 mod = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_MODE) | im;
49 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im;
50
51 switch (flow_type & IRQF_TRIGGER_MASK) {
52 case IRQ_TYPE_EDGE_FALLING:
53 pol ^= im;
54 break;
55 case IRQ_TYPE_LEVEL_HIGH:
56 mod ^= im;
57 break;
58 case IRQ_TYPE_NONE:
59 flow_type = IRQ_TYPE_LEVEL_LOW;
60 fallthrough;
61 case IRQ_TYPE_LEVEL_LOW:
62 mod ^= im;
63 pol ^= im;
64 break;
65 case IRQ_TYPE_EDGE_RISING:
66 break;
67 default:
68 pr_err("%s: Cannot assign multiple trigger modes to IRQ %d.\n", __func__, data->irq);
69 return -EBADR;
70 }
71
72 irqd_set_trigger_type(data, flow_type);
73 irq_setup_alt_chip(data, flow_type);
74
75 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_MODE, mod);
76 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol);
77 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, im);
78 return IRQ_SET_MASK_OK;
79}
80
81static void tb10x_irq_cascade(struct irq_desc *desc)
82{
83 struct irq_domain *domain = irq_desc_get_handler_data(desc);
84 unsigned int irq = irq_desc_get_irq(desc);
85
86 generic_handle_domain_irq(domain, irq);
87}
88
89static int __init of_tb10x_init_irq(struct device_node *ictl,
90 struct device_node *parent)
91{
92 int i, ret, nrirqs = of_irq_count(ictl);
93 struct resource mem;
94 struct irq_chip_generic *gc;
95 struct irq_domain *domain;
96 void __iomem *reg_base;
97
98 if (of_address_to_resource(ictl, 0, &mem)) {
99 pr_err("%pOFn: No registers declared in DeviceTree.\n",
100 ictl);
101 return -EINVAL;
102 }
103
104 if (!request_mem_region(mem.start, resource_size(&mem),
105 ictl->full_name)) {
106 pr_err("%pOFn: Request mem region failed.\n", ictl);
107 return -EBUSY;
108 }
109
110 reg_base = ioremap(mem.start, resource_size(&mem));
111 if (!reg_base) {
112 ret = -EBUSY;
113 pr_err("%pOFn: ioremap failed.\n", ictl);
114 goto ioremap_fail;
115 }
116
117 domain = irq_domain_create_linear(of_fwnode_handle(ictl), AB_IRQCTL_MAXIRQ,
118 &irq_generic_chip_ops, NULL);
119 if (!domain) {
120 ret = -ENOMEM;
121 pr_err("%pOFn: Could not register interrupt domain.\n",
122 ictl);
123 goto irq_domain_create_fail;
124 }
125
126 ret = irq_alloc_domain_generic_chips(domain, AB_IRQCTL_MAXIRQ,
127 2, ictl->name, handle_level_irq,
128 IRQ_NOREQUEST, IRQ_NOPROBE,
129 IRQ_GC_INIT_MASK_CACHE);
130 if (ret) {
131 pr_err("%pOFn: Could not allocate generic interrupt chip.\n",
132 ictl);
133 goto gc_alloc_fail;
134 }
135
136 gc = domain->gc->gc[0];
137 gc->reg_base = reg_base;
138
139 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
140 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
141 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
142 gc->chip_types[0].chip.irq_set_type = tb10x_irq_set_type;
143 gc->chip_types[0].regs.mask = AB_IRQCTL_INT_ENABLE;
144
145 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
146 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
147 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
148 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
149 gc->chip_types[1].chip.irq_set_type = tb10x_irq_set_type;
150 gc->chip_types[1].regs.ack = AB_IRQCTL_INT_STATUS;
151 gc->chip_types[1].regs.mask = AB_IRQCTL_INT_ENABLE;
152 gc->chip_types[1].handler = handle_edge_irq;
153
154 for (i = 0; i < nrirqs; i++) {
155 unsigned int irq = irq_of_parse_and_map(ictl, i);
156
157 irq_set_chained_handler_and_data(irq, tb10x_irq_cascade,
158 domain);
159 }
160
161 ab_irqctl_writereg(gc, AB_IRQCTL_INT_ENABLE, 0);
162 ab_irqctl_writereg(gc, AB_IRQCTL_INT_MODE, 0);
163 ab_irqctl_writereg(gc, AB_IRQCTL_INT_POLARITY, 0);
164 ab_irqctl_writereg(gc, AB_IRQCTL_INT_STATUS, ~0UL);
165
166 return 0;
167
168gc_alloc_fail:
169 irq_domain_remove(domain);
170irq_domain_create_fail:
171 iounmap(reg_base);
172ioremap_fail:
173 release_mem_region(mem.start, resource_size(&mem));
174 return ret;
175}
176IRQCHIP_DECLARE(tb10x_intc, "abilis,tb10x-ictl", of_tb10x_init_irq);