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(I'm so sorry!) Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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SPDX-License-Identifier: GPL-2.0-only/* * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. * */
#include <linux/device.h>#include <linux/interconnect.h>#include <linux/interconnect-provider.h>#include <linux/module.h>#include <linux/of_platform.h>#include <dt-bindings/interconnect/qcom,maili-rpmh.h>
#include "bcm-voter.h"#include "icc-rpmh.h"
static struct qcom_icc_node ddr_eff_veto_slave = { .name = "ddr_eff_veto_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup0_core_slave = { .name = "qup0_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup1_core_slave = { .name = "qup1_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup2_core_slave = { .name = "qup2_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup3_core_slave = { .name = "qup3_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup4_core_slave = { .name = "qup4_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qup5_core_slave = { .name = "qup5_core_slave", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_aoss = { .name = "qhs_aoss", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_ipa = { .name = "qhs_ipa", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_ipc_router_fence = { .name = "qhs_ipc_router_fence", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_soccp = { .name = "qhs_soccp", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_tme_cfg = { .name = "qhs_tme_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qss_ddrss_cfg = { .name = "qss_ddrss_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qxs_imem = { .name = "qxs_imem", .channels = 1, .buswidth = 8,};
static struct qcom_icc_node xs_pcie = { .name = "xs_pcie", .channels = 1, .buswidth = 8,};
static struct qcom_icc_node xs_pcie_g4x1 = { .name = "xs_pcie_g4x1", .channels = 1, .buswidth = 8,};
static struct qcom_icc_node qhs_lpi_cc = { .name = "qhs_lpi_cc", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qns_lb = { .name = "qns_lb", .channels = 4, .buswidth = 16,};
static struct qcom_icc_node srvc_llclpi_noc = { .name = "srvc_llclpi_noc", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node srvc_llclpi_noc_chipcx = { .name = "srvc_llclpi_noc_chipcx", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node ebi = { .name = "ebi", .channels = 4, .buswidth = 4,};
static struct qcom_icc_node ddr_rt_slave = { .name = "ddr_rt_slave", .channels = 4, .buswidth = 4,};
static struct qcom_icc_node srvc_pcie_aggre_noc = { .name = "srvc_pcie_aggre_noc", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_ahb2phy0 = { .name = "qhs_ahb2phy0", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_boot_rom = { .name = "qhs_boot_rom", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_camera_cfg = { .name = "qhs_camera_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_clk_ctl = { .name = "qhs_clk_ctl", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_crypto_cfg = { .name = "qhs_crypto_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_display_cfg = { .name = "qhs_display_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_eva_cfg = { .name = "qhs_eva_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_gpuss_cfg = { .name = "qhs_gpuss_cfg", .channels = 1, .buswidth = 8,};
static struct qcom_icc_node qhs_i2c = { .name = "qhs_i2c", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_imem_cfg = { .name = "qhs_imem_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_ipc_router = { .name = "qhs_ipc_router", .channels = 4, .buswidth = 4,};
static struct qcom_icc_node qhs_iris_cfg = { .name = "qhs_iris_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_mss_cfg = { .name = "qhs_mss_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_pcie_cfg = { .name = "qhs_pcie_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_pcie_g4x1_cfg = { .name = "qhs_pcie_g4x1_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_prng = { .name = "qhs_prng", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qspi = { .name = "qhs_qspi", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qup1 = { .name = "qhs_qup1", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qup2 = { .name = "qhs_qup2", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qup3 = { .name = "qhs_qup3", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qup4 = { .name = "qhs_qup4", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_qup5 = { .name = "qhs_qup5", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_sdc2 = { .name = "qhs_sdc2", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_sdc4 = { .name = "qhs_sdc4", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_tlmm = { .name = "qhs_tlmm", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_ufs_mem_cfg = { .name = "qhs_ufs_mem_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_usb3 = { .name = "qhs_usb3", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = { .name = "qhs_vsense_ctrl_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qss_qdss_cfg = { .name = "qss_qdss_cfg", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qss_qdss_stm = { .name = "qss_qdss_stm", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node qss_tcsr = { .name = "qss_tcsr", .channels = 1, .buswidth = 4,};
static struct qcom_icc_node xs_sys_tcu_cfg = { .name = "xs_sys_tcu_cfg", .channels = 1, .buswidth = 8,};
static struct qcom_icc_node ddr_eff_veto_master = { .name = "ddr_eff_veto_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &ddr_eff_veto_slave },};
static struct qcom_icc_node qup0_core_master = { .name = "qup0_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup0_core_slave },};
static struct qcom_icc_node qup1_core_master = { .name = "qup1_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup1_core_slave },};
static struct qcom_icc_node qup2_core_master = { .name = "qup2_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup2_core_slave },};
static struct qcom_icc_node qup3_core_master = { .name = "qup3_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup3_core_slave },};
static struct qcom_icc_node qup4_core_master = { .name = "qup4_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup4_core_slave },};
static struct qcom_icc_node qup5_core_master = { .name = "qup5_core_master", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qup5_core_slave },};
static struct qcom_icc_node qnm_gemnoc_pcie = { .name = "qnm_gemnoc_pcie", .channels = 1, .buswidth = 8, .num_links = 2, .link_nodes = { &xs_pcie, &xs_pcie_g4x1 },};
static struct qcom_icc_node qnm_lpiaon_noc_llclpi_noc = { .name = "qnm_lpiaon_noc_llclpi_noc", .channels = 1, .buswidth = 16, .num_links = 4, .link_nodes = { &qhs_lpi_cc, &qns_lb, &srvc_llclpi_noc, &srvc_llclpi_noc_chipcx },};
static struct qcom_icc_node llcc_mc = { .name = "llcc_mc", .channels = 4, .buswidth = 4, .num_links = 1, .link_nodes = { &ebi },};
static struct qcom_icc_node ddr_rt_mc = { .name = "ddr_rt_mc", .channels = 4, .buswidth = 4, .num_links = 1, .link_nodes = { &ddr_rt_slave },};
static struct qcom_icc_node qsm_pcie_anoc_cfg = { .name = "qsm_pcie_anoc_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &srvc_pcie_aggre_noc },};
static struct qcom_icc_node qsm_cfg_center = { .name = "qsm_cfg_center", .channels = 1, .buswidth = 4, .num_links = 14, .link_nodes = { &qhs_boot_rom, &qhs_clk_ctl, &qhs_crypto_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipc_router, &qhs_mss_cfg, &qhs_prng, &qhs_tlmm, &qhs_vsense_ctrl_cfg, &qss_qdss_cfg, &qss_qdss_stm, &qss_tcsr, &xs_sys_tcu_cfg },};
static struct qcom_icc_node qsm_cfg_east = { .name = "qsm_cfg_east", .channels = 1, .buswidth = 4, .num_links = 2, .link_nodes = { &qhs_qup2, &qhs_qup4 },};
static struct qcom_icc_node qsm_cfg_mm_hf = { .name = "qsm_cfg_mm_hf", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qhs_display_cfg },};
static struct qcom_icc_node qsm_cfg_mm_sf = { .name = "qsm_cfg_mm_sf", .channels = 1, .buswidth = 4, .num_links = 3, .link_nodes = { &qhs_camera_cfg, &qhs_eva_cfg, &qhs_iris_cfg },};
static struct qcom_icc_node qsm_cfg_north = { .name = "qsm_cfg_north", .channels = 1, .buswidth = 4, .num_links = 3, .link_nodes = { &qhs_ahb2phy0, &qhs_ufs_mem_cfg, &qhs_usb3 },};
static struct qcom_icc_node qsm_cfg_west = { .name = "qsm_cfg_west", .channels = 1, .buswidth = 4, .num_links = 2, .link_nodes = { &qhs_qup1, &qhs_sdc2 },};
static struct qcom_icc_node qns_llcc = { .name = "qns_llcc", .channels = 4, .buswidth = 16, .num_links = 1, .link_nodes = { &llcc_mc },};
static struct qcom_icc_node qns_pcie = { .name = "qns_pcie", .channels = 1, .buswidth = 8, .num_links = 1, .link_nodes = { &qnm_gemnoc_pcie },};
static struct qcom_icc_node qns_llc_lpinoc = { .name = "qns_llc_lpinoc", .channels = 1, .buswidth = 16, .num_links = 1, .link_nodes = { &qnm_lpiaon_noc_llclpi_noc },};
static struct qcom_icc_node qss_pcie_anoc_cfg = { .name = "qss_pcie_anoc_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_pcie_anoc_cfg },};
static struct qcom_icc_node qss_stdst_center_cfg = { .name = "qss_stdst_center_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_center },};
static struct qcom_icc_node qss_stdst_east_cfg = { .name = "qss_stdst_east_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_east },};
static struct qcom_icc_node qss_stdst_mm_hf_cfg = { .name = "qss_stdst_mm_hf_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_mm_hf },};
static struct qcom_icc_node qss_stdst_mm_sf_cfg = { .name = "qss_stdst_mm_sf_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_mm_sf },};
static struct qcom_icc_node qss_stdst_north_cfg = { .name = "qss_stdst_north_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_north },};
static struct qcom_icc_node qss_stdst_west_cfg = { .name = "qss_stdst_west_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_west },};
static struct qcom_icc_node alm_gic = { .name = "alm_gic", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x14d000 }, .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_llcc },};
static struct qcom_icc_node qnm_qpace = { .name = "qnm_qpace", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x153000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_llcc },};
static struct qcom_icc_node qsm_cfg_south = { .name = "qsm_cfg_south", .channels = 1, .buswidth = 4, .num_links = 8, .link_nodes = { &qhs_i2c, &qhs_pcie_cfg, &qhs_pcie_g4x1_cfg, &qhs_qspi, &qhs_qup3, &qhs_qup5, &qhs_sdc4, &qss_pcie_anoc_cfg },};
static struct qcom_icc_node qss_stdst_south_cfg = { .name = "qss_stdst_south_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cfg_south },};
static struct qcom_icc_node qsm_cnoc_main = { .name = "qsm_cnoc_main", .channels = 1, .buswidth = 4, .num_links = 7, .link_nodes = { &qss_stdst_center_cfg, &qss_stdst_east_cfg, &qss_stdst_mm_hf_cfg, &qss_stdst_mm_sf_cfg, &qss_stdst_north_cfg, &qss_stdst_south_cfg, &qss_stdst_west_cfg },};
static struct qcom_icc_node qss_cfg = { .name = "qss_cfg", .channels = 1, .buswidth = 4, .num_links = 1, .link_nodes = { &qsm_cnoc_main },};
static struct qcom_icc_node qnm_gemnoc_cnoc = { .name = "qnm_gemnoc_cnoc", .channels = 1, .buswidth = 16, .num_links = 8, .link_nodes = { &qhs_aoss, &qhs_ipa, &qhs_ipc_router_fence, &qhs_soccp, &qhs_tme_cfg, &qss_cfg, &qss_ddrss_cfg, &qxs_imem },};
static struct qcom_icc_node qns_gem_noc_cnoc = { .name = "qns_gem_noc_cnoc", .channels = 1, .buswidth = 16, .num_links = 1, .link_nodes = { &qnm_gemnoc_cnoc },};
static struct qcom_icc_node alm_gpu_tcu = { .name = "alm_gpu_tcu", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x145000 }, .prio = 1, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },};
static struct qcom_icc_node alm_sys_tcu = { .name = "alm_sys_tcu", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x147000 }, .prio = 6, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },};
static struct qcom_icc_node chm_apps = { .name = "chm_apps", .channels = 2, .buswidth = 32, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_gpu = { .name = "qnm_gpu", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x51000, 0xd1000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_lpass_gemnoc = { .name = "qnm_lpass_gemnoc", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x149000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_mdsp = { .name = "qnm_mdsp", .channels = 1, .buswidth = 16, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_mnoc_hf = { .name = "qnm_mnoc_hf", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x55000, 0xd5000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_mnoc_sf = { .name = "qnm_mnoc_sf", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x57000, 0xd7000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_nsp_gemnoc = { .name = "qnm_nsp_gemnoc", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x59000, 0xd9000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_pcie = { .name = "qnm_pcie", .channels = 1, .buswidth = 16, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x14b000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 2, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },};
static struct qcom_icc_node qnm_snoc_sf = { .name = "qnm_snoc_sf", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x14f000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qnm_wlan_q6 = { .name = "qnm_wlan_q6", .channels = 1, .buswidth = 8, .num_links = 3, .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, &qns_pcie },};
static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { .name = "qns_lpass_ag_noc_gemnoc", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_lpass_gemnoc },};
static struct qcom_icc_node qns_mem_noc_hf = { .name = "qns_mem_noc_hf", .channels = 2, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_mnoc_hf },};
static struct qcom_icc_node qns_mem_noc_sf = { .name = "qns_mem_noc_sf", .channels = 2, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_mnoc_sf },};
static struct qcom_icc_node qns_nsp_gemnoc = { .name = "qns_nsp_gemnoc", .channels = 2, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_nsp_gemnoc },};
static struct qcom_icc_node qns_pcie_gemnoc = { .name = "qns_pcie_gemnoc", .channels = 1, .buswidth = 16, .num_links = 1, .link_nodes = { &qnm_pcie },};
static struct qcom_icc_node qns_gemnoc_sf = { .name = "qns_gemnoc_sf", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_snoc_sf },};
static struct qcom_icc_node qnm_lpiaon_noc = { .name = "qnm_lpiaon_noc", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qns_lpass_ag_noc_gemnoc },};
static struct qcom_icc_node qnm_camnoc_hf = { .name = "qnm_camnoc_hf", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x50000, 0x51000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_hf },};
static struct qcom_icc_node qnm_mdp = { .name = "qnm_mdp", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x52000, 0x53000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_hf },};
static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { .name = "qnm_camnoc_nrt_icp_sf", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x20000 }, .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { .name = "qnm_camnoc_rt_cdm_sf", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x28000 }, .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_camnoc_sf = { .name = "qnm_camnoc_sf", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x21000, 0x22000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_mdss_dcp = { .name = "qnm_mdss_dcp", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x29000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_vapss_hcp = { .name = "qnm_vapss_hcp", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_video_cv_cpu = { .name = "qnm_video_cv_cpu", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x24000 }, .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_video_eva = { .name = "qnm_video_eva", .channels = 2, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 2, .port_offsets = { 0x25000, 0x26000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_video_mvp = { .name = "qnm_video_mvp", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x23000 }, .prio = 0, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_video_v_cpu = { .name = "qnm_video_v_cpu", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x27000 }, .prio = 4, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_mem_noc_sf },};
static struct qcom_icc_node qnm_nsp = { .name = "qnm_nsp", .channels = 2, .buswidth = 32, .num_links = 1, .link_nodes = { &qns_nsp_gemnoc },};
static struct qcom_icc_node xm_pcie = { .name = "xm_pcie", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0xc000 }, .prio = 3, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_pcie_gemnoc },};
static struct qcom_icc_node xm_pcie_g4x1 = { .name = "xm_pcie_g4x1", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0xd000 }, .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_pcie_gemnoc },};
static struct qcom_icc_node qnm_aggre_noc = { .name = "qnm_aggre_noc", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x20000 }, .prio = 2, .urg_fwd = 1, .prio_fwd_disable = 0, }, .num_links = 1, .link_nodes = { &qns_gemnoc_sf },};
static struct qcom_icc_node qnm_apss_noc = { .name = "qnm_apss_noc", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x1e000 }, .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_gemnoc_sf },};
static struct qcom_icc_node qnm_cnoc_data = { .name = "qnm_cnoc_data", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x1f000 }, .prio = 2, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_gemnoc_sf },};
static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_aggre_noc },};
static struct qcom_icc_node qns_lpass_aggnoc = { .name = "qns_lpass_aggnoc", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_lpiaon_noc },};
static struct qcom_icc_node qhm_qspi = { .name = "qhm_qspi", .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x49000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qhm_qup2 = { .name = "qhm_qup2", .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x48000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qhm_qup3 = { .name = "qhm_qup3", .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x46000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qhm_qup4 = { .name = "qhm_qup4", .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x47000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qhm_qup5 = { .name = "qhm_qup5", .channels = 1, .buswidth = 4, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x4e000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qxm_crypto = { .name = "qxm_crypto", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x40000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qxm_ipa = { .name = "qxm_ipa", .channels = 1, .buswidth = 16, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x41000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qxm_qup1 = { .name = "qxm_qup1", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x4d000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qxm_soccp = { .name = "qxm_soccp", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x45000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_qdss_etr_0 = { .name = "xm_qdss_etr_0", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x42000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_qdss_etr_1 = { .name = "xm_qdss_etr_1", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x43000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_sdc2 = { .name = "xm_sdc2", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x44000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_sdc4 = { .name = "xm_sdc4", .channels = 1, .buswidth = 8, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_ufs_mem = { .name = "xm_ufs_mem", .channels = 1, .buswidth = 32, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x4b000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node xm_usb3 = { .name = "xm_usb3", .channels = 1, .buswidth = 8, .qosbox = &(const struct qcom_icc_qosbox) { .num_ports = 1, .port_offsets = { 0x4c000 }, .prio = 0, .urg_fwd = 0, .prio_fwd_disable = 1, }, .num_links = 1, .link_nodes = { &qns_a1noc_snoc },};
static struct qcom_icc_node qnm_lpass_lpinoc = { .name = "qnm_lpass_lpinoc", .channels = 1, .buswidth = 32, .num_links = 2, .link_nodes = { &qns_llc_lpinoc, &qns_lpass_aggnoc },};
static struct qcom_icc_node qns_lpi_aon_noc = { .name = "qns_lpi_aon_noc", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qnm_lpass_lpinoc },};
static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { .name = "qnm_lpinoc_dsp_qns4m", .channels = 1, .buswidth = 32, .num_links = 1, .link_nodes = { &qns_lpi_aon_noc },};
static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .enable_mask = BIT(3), .num_nodes = 1, .nodes = { &ebi },};
static struct qcom_icc_bcm bcm_ce0 = { .name = "CE0", .num_nodes = 1, .nodes = { &qxm_crypto },};
static struct qcom_icc_bcm bcm_cn0 = { .name = "CN0", .enable_mask = BIT(0), .keepalive = true, .num_nodes = 25, .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, &qhs_aoss, &qhs_ipa, &qhs_ipc_router_fence, &qhs_soccp, &qhs_tme_cfg, &qss_cfg, &qss_ddrss_cfg, &qxs_imem, &xs_pcie, &xs_pcie_g4x1, &qsm_cfg_center, &qsm_cfg_east, &qsm_cfg_mm_hf, &qsm_cfg_mm_sf, &qsm_cfg_north, &qsm_cfg_south, &qsm_cfg_west, &qhs_ahb2phy0, &qhs_boot_rom, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_crypto_cfg, &qhs_eva_cfg },};
static struct qcom_icc_bcm bcm_cn1 = { .name = "CN1", .num_nodes = 6, .nodes = { &qhs_display_cfg, &qhs_qup1, &qhs_qup2, &qhs_qup3, &qhs_qup4, &qhs_qup5 },};
static struct qcom_icc_bcm bcm_co0 = { .name = "CO0", .enable_mask = BIT(0), .num_nodes = 2, .nodes = { &qnm_nsp, &qns_nsp_gemnoc },};
static struct qcom_icc_bcm bcm_de0 = { .name = "DE0", .enable_mask = BIT(0), .num_nodes = 1, .nodes = { &ddr_eff_veto_slave },};
static struct qcom_icc_bcm bcm_lp0 = { .name = "LP0", .num_nodes = 5, .nodes = { &qnm_lpiaon_noc_llclpi_noc, &qns_lb, &qnm_lpass_lpinoc, &qns_llc_lpinoc, &qns_lpass_aggnoc },};
static struct qcom_icc_bcm bcm_mc0 = { .name = "MC0", .keepalive = true, .num_nodes = 1, .nodes = { &ebi },};
static struct qcom_icc_bcm bcm_mc5 = { .name = "MC5", .num_nodes = 1, .nodes = { &ddr_rt_slave },};
static struct qcom_icc_bcm bcm_mm0 = { .name = "MM0", .num_nodes = 1, .nodes = { &qns_mem_noc_hf },};
static struct qcom_icc_bcm bcm_mm1 = { .name = "MM1", .enable_mask = BIT(0), .num_nodes = 9, .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, &qnm_vapss_hcp, &qnm_video_cv_cpu, &qnm_video_mvp, &qnm_video_v_cpu, &qns_mem_noc_sf },};
static struct qcom_icc_bcm bcm_qpc0 = { .name = "QPC0", .num_nodes = 1, .nodes = { &qnm_qpace },};
static struct qcom_icc_bcm bcm_qup0 = { .name = "QUP0", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup0_core_slave },};
static struct qcom_icc_bcm bcm_qup1 = { .name = "QUP1", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup1_core_slave },};
static struct qcom_icc_bcm bcm_qup2 = { .name = "QUP2", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup2_core_slave },};
static struct qcom_icc_bcm bcm_qup3 = { .name = "QUP3", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup3_core_slave },};
static struct qcom_icc_bcm bcm_qup4 = { .name = "QUP4", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup4_core_slave },};
static struct qcom_icc_bcm bcm_qup5 = { .name = "QUP5", .vote_scale = 1, .keepalive = true, .num_nodes = 1, .nodes = { &qup5_core_slave },};
static struct qcom_icc_bcm bcm_sh0 = { .name = "SH0", .keepalive = true, .num_nodes = 1, .nodes = { &qns_llcc },};
static struct qcom_icc_bcm bcm_sh1 = { .name = "SH1", .enable_mask = BIT(0), .num_nodes = 15, .nodes = { &alm_gic, &alm_gpu_tcu, &alm_sys_tcu, &chm_apps, &qnm_gpu, &qnm_lpass_gemnoc, &qnm_mdsp, &qnm_mnoc_hf, &qnm_mnoc_sf, &qnm_nsp_gemnoc, &qnm_pcie, &qnm_snoc_sf, &qnm_wlan_q6, &qns_gem_noc_cnoc, &qns_pcie },};
static struct qcom_icc_bcm bcm_sn0 = { .name = "SN0", .keepalive = true, .num_nodes = 1, .nodes = { &qns_gemnoc_sf },};
static struct qcom_icc_bcm bcm_sn2 = { .name = "SN2", .num_nodes = 1, .nodes = { &qnm_aggre_noc },};
static struct qcom_icc_bcm bcm_sn3 = { .name = "SN3", .num_nodes = 1, .nodes = { &qns_pcie_gemnoc },};
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { &bcm_ce0,};
static struct qcom_icc_node * const aggre1_noc_nodes[] = { [MASTER_QSPI_0] = &qhm_qspi, [MASTER_QUP_2] = &qhm_qup2, [MASTER_QUP_3] = &qhm_qup3, [MASTER_QUP_4] = &qhm_qup4, [MASTER_QUP_5] = &qhm_qup5, [MASTER_CRYPTO] = &qxm_crypto, [MASTER_IPA] = &qxm_ipa, [MASTER_QUP_1] = &qxm_qup1, [MASTER_SOCCP_PROC] = &qxm_soccp, [MASTER_QDSS_ETR] = &xm_qdss_etr_0, [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, [MASTER_SDCC_2] = &xm_sdc2, [MASTER_SDCC_4] = &xm_sdc4, [MASTER_UFS_MEM] = &xm_ufs_mem, [MASTER_USB3] = &xm_usb3, [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,};
static const struct regmap_config maili_aggre1_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x56200, .fast_io = true,};
static const struct qcom_icc_desc maili_aggre1_noc = { .config = &maili_aggre1_noc_regmap_config, .nodes = aggre1_noc_nodes, .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), .bcms = aggre1_noc_bcms, .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), .qos_requires_clocks = true,};
static struct qcom_icc_bcm * const clk_virt_bcms[] = { &bcm_de0, &bcm_qup0, &bcm_qup1, &bcm_qup2, &bcm_qup3, &bcm_qup4, &bcm_qup5,};
static struct qcom_icc_node * const clk_virt_nodes[] = { [MASTER_DDR_EFF_VETO] = &ddr_eff_veto_master, [MASTER_QUP_CORE_0] = &qup0_core_master, [MASTER_QUP_CORE_1] = &qup1_core_master, [MASTER_QUP_CORE_2] = &qup2_core_master, [MASTER_QUP_CORE_3] = &qup3_core_master, [MASTER_QUP_CORE_4] = &qup4_core_master, [MASTER_QUP_CORE_5] = &qup5_core_master, [SLAVE_DDR_EFF_VETO] = &ddr_eff_veto_slave, [SLAVE_QUP_CORE_0] = &qup0_core_slave, [SLAVE_QUP_CORE_1] = &qup1_core_slave, [SLAVE_QUP_CORE_2] = &qup2_core_slave, [SLAVE_QUP_CORE_3] = &qup3_core_slave, [SLAVE_QUP_CORE_4] = &qup4_core_slave, [SLAVE_QUP_CORE_5] = &qup5_core_slave,};
static const struct qcom_icc_desc maili_clk_virt = { .nodes = clk_virt_nodes, .num_nodes = ARRAY_SIZE(clk_virt_nodes), .bcms = clk_virt_bcms, .num_bcms = ARRAY_SIZE(clk_virt_bcms),};
static struct qcom_icc_bcm * const cnoc_main_bcms[] = { &bcm_cn0,};
static struct qcom_icc_node * const cnoc_main_nodes[] = { [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, [SLAVE_AOSS] = &qhs_aoss, [SLAVE_IPA_CFG] = &qhs_ipa, [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence, [SLAVE_SOCCP] = &qhs_soccp, [SLAVE_TME_CFG] = &qhs_tme_cfg, [SLAVE_CNOC_CFG] = &qss_cfg, [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, [SLAVE_IMEM] = &qxs_imem, [SLAVE_PCIE_0] = &xs_pcie, [SLAVE_PCIE_1] = &xs_pcie_g4x1,};
static const struct regmap_config maili_cnoc_main_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x20000, .fast_io = true,};
static const struct qcom_icc_desc maili_cnoc_main = { .config = &maili_cnoc_main_regmap_config, .nodes = cnoc_main_nodes, .num_nodes = ARRAY_SIZE(cnoc_main_nodes), .bcms = cnoc_main_bcms, .num_bcms = ARRAY_SIZE(cnoc_main_bcms),};
static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_qpc0, &bcm_sh0, &bcm_sh1,};
static struct qcom_icc_node * const gem_noc_nodes[] = { [MASTER_GIC] = &alm_gic, [MASTER_GPU_TCU] = &alm_gpu_tcu, [MASTER_SYS_TCU] = &alm_sys_tcu, [MASTER_APPSS_PROC] = &chm_apps, [MASTER_GFX3D] = &qnm_gpu, [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, [MASTER_MSS_PROC] = &qnm_mdsp, [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, [MASTER_QPACE] = &qnm_qpace, [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, [MASTER_WLAN_Q6] = &qnm_wlan_q6, [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, [SLAVE_LLCC] = &qns_llcc, [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,};
static const struct regmap_config maili_gem_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x160200, .fast_io = true,};
static const struct qcom_icc_desc maili_gem_noc = { .config = &maili_gem_noc_regmap_config, .nodes = gem_noc_nodes, .num_nodes = ARRAY_SIZE(gem_noc_nodes), .bcms = gem_noc_bcms, .num_bcms = ARRAY_SIZE(gem_noc_bcms),};
static struct qcom_icc_bcm * const llclpi_noc_bcms[] = { &bcm_lp0,};
static struct qcom_icc_node * const llclpi_noc_nodes[] = { [MASTER_LPIAON_NOC_LLCLPI_NOC] = &qnm_lpiaon_noc_llclpi_noc, [SLAVE_LPASS_LPI_CC] = &qhs_lpi_cc, [SLAVE_LLCC_ISLAND] = &qns_lb, [SLAVE_SERVICE_LLCLPI_NOC] = &srvc_llclpi_noc, [SLAVE_SERVICE_LLCLPI_NOC_CHIPCX] = &srvc_llclpi_noc_chipcx,};
static const struct regmap_config maili_llclpi_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x17200, .fast_io = true,};
static const struct qcom_icc_desc maili_llclpi_noc = { .config = &maili_llclpi_noc_regmap_config, .nodes = llclpi_noc_nodes, .num_nodes = ARRAY_SIZE(llclpi_noc_nodes), .bcms = llclpi_noc_bcms, .num_bcms = ARRAY_SIZE(llclpi_noc_bcms),};
static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc,};
static const struct regmap_config maili_lpass_ag_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0xc080, .fast_io = true,};
static const struct qcom_icc_desc maili_lpass_ag_noc = { .config = &maili_lpass_ag_noc_regmap_config, .nodes = lpass_ag_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),};
static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { &bcm_lp0,};
static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, [SLAVE_LPIAON_NOC_LLCLPI_NOC] = &qns_llc_lpinoc, [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc,};
static const struct regmap_config maili_lpass_lpiaon_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x19080, .fast_io = true,};
static const struct qcom_icc_desc maili_lpass_lpiaon_noc = { .config = &maili_lpass_lpiaon_noc_regmap_config, .nodes = lpass_lpiaon_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms = lpass_lpiaon_noc_bcms, .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms),};
static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc,};
static const struct regmap_config maili_lpass_lpicx_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x46080, .fast_io = true,};
static const struct qcom_icc_desc maili_lpass_lpicx_noc = { .config = &maili_lpass_lpicx_noc_regmap_config, .nodes = lpass_lpicx_noc_nodes, .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes),};
static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, &bcm_mc5,};
static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [MASTER_DDR_RT] = &ddr_rt_mc, [SLAVE_EBI1] = &ebi, [SLAVE_DDR_RT] = &ddr_rt_slave,};
static const struct qcom_icc_desc maili_mc_virt = { .nodes = mc_virt_nodes, .num_nodes = ARRAY_SIZE(mc_virt_nodes), .bcms = mc_virt_bcms, .num_bcms = ARRAY_SIZE(mc_virt_bcms),};
static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1,};
static struct qcom_icc_node * const mmss_noc_nodes[] = { [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, [MASTER_MDP] = &qnm_mdp, [MASTER_MDSS_DCP] = &qnm_mdss_dcp, [MASTER_CDSP_HCP] = &qnm_vapss_hcp, [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, [MASTER_VIDEO_EVA] = &qnm_video_eva, [MASTER_VIDEO_MVP] = &qnm_video_mvp, [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,};
static const struct regmap_config maili_mmss_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x5f800, .fast_io = true,};
static const struct qcom_icc_desc maili_mmss_noc = { .config = &maili_mmss_noc_regmap_config, .nodes = mmss_noc_nodes, .num_nodes = ARRAY_SIZE(mmss_noc_nodes), .bcms = mmss_noc_bcms, .num_bcms = ARRAY_SIZE(mmss_noc_bcms),};
static struct qcom_icc_bcm * const nsp_noc_bcms[] = { &bcm_co0,};
static struct qcom_icc_node * const nsp_noc_nodes[] = { [MASTER_CDSP_PROC] = &qnm_nsp, [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,};
static const struct regmap_config maili_nsp_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x21280, .fast_io = true,};
static const struct qcom_icc_desc maili_nsp_noc = { .config = &maili_nsp_noc_regmap_config, .nodes = nsp_noc_nodes, .num_nodes = ARRAY_SIZE(nsp_noc_nodes), .bcms = nsp_noc_bcms, .num_bcms = ARRAY_SIZE(nsp_noc_bcms),};
static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { &bcm_sn3,};
static struct qcom_icc_node * const pcie_anoc_nodes[] = { [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, [MASTER_PCIE_0] = &xm_pcie, [MASTER_PCIE_1] = &xm_pcie_g4x1, [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc,};
static const struct regmap_config maili_pcie_anoc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x12400, .fast_io = true,};
static const struct qcom_icc_desc maili_pcie_anoc = { .config = &maili_pcie_anoc_regmap_config, .nodes = pcie_anoc_nodes, .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), .bcms = pcie_anoc_bcms, .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), .qos_requires_clocks = true,};
static struct qcom_icc_bcm * const stdst_cfg_bcms[] = { &bcm_cn0, &bcm_cn1,};
static struct qcom_icc_node * const stdst_cfg_nodes[] = { [MASTER_CFG_CENTER] = &qsm_cfg_center, [MASTER_CFG_EAST] = &qsm_cfg_east, [MASTER_CFG_MM_HF] = &qsm_cfg_mm_hf, [MASTER_CFG_MM_SF] = &qsm_cfg_mm_sf, [MASTER_CFG_NORTH] = &qsm_cfg_north, [MASTER_CFG_SOUTH] = &qsm_cfg_south, [MASTER_CFG_WEST] = &qsm_cfg_west, [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, [SLAVE_BOOT_ROM] = &qhs_boot_rom, [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, [SLAVE_CLK_CTL] = &qhs_clk_ctl, [SLAVE_CRYPTO_CFG] = &qhs_crypto_cfg, [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, [SLAVE_EVA_CFG] = &qhs_eva_cfg, [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, [SLAVE_I2C] = &qhs_i2c, [SLAVE_IMEM_CFG] = &qhs_imem_cfg, [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, [SLAVE_IRIS_CFG] = &qhs_iris_cfg, [SLAVE_CNOC_MSS] = &qhs_mss_cfg, [SLAVE_PCIE_0_CFG] = &qhs_pcie_cfg, [SLAVE_PCIE_1_CFG] = &qhs_pcie_g4x1_cfg, [SLAVE_PRNG] = &qhs_prng, [SLAVE_QSPI_0] = &qhs_qspi, [SLAVE_QUP_1] = &qhs_qup1, [SLAVE_QUP_2] = &qhs_qup2, [SLAVE_QUP_3] = &qhs_qup3, [SLAVE_QUP_4] = &qhs_qup4, [SLAVE_QUP_5] = &qhs_qup5, [SLAVE_SDCC_2] = &qhs_sdc2, [SLAVE_SDCC_4] = &qhs_sdc4, [SLAVE_TLMM] = &qhs_tlmm, [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, [SLAVE_USB3] = &qhs_usb3, [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, [SLAVE_QDSS_CFG] = &qss_qdss_cfg, [SLAVE_QDSS_STM] = &qss_qdss_stm, [SLAVE_TCSR] = &qss_tcsr, [SLAVE_TCU] = &xs_sys_tcu_cfg,};
static const struct regmap_config maili_stdst_cfg_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x9000, .fast_io = true,};
static const struct qcom_icc_desc maili_stdst_cfg = { .config = &maili_stdst_cfg_regmap_config, .nodes = stdst_cfg_nodes, .num_nodes = ARRAY_SIZE(stdst_cfg_nodes), .bcms = stdst_cfg_bcms, .num_bcms = ARRAY_SIZE(stdst_cfg_bcms),};
static struct qcom_icc_node * const stdst_main_nodes[] = { [MASTER_CNOC_STARDUST] = &qsm_cnoc_main, [SLAVE_STARDUST_CENTER_CFG] = &qss_stdst_center_cfg, [SLAVE_STARDUST_EAST_CFG] = &qss_stdst_east_cfg, [SLAVE_STARDUST_MM_HF_CFG] = &qss_stdst_mm_hf_cfg, [SLAVE_STARDUST_MM_SF_CFG] = &qss_stdst_mm_sf_cfg, [SLAVE_STARDUST_NORTH_CFG] = &qss_stdst_north_cfg, [SLAVE_STARDUST_SOUTH_CFG] = &qss_stdst_south_cfg, [SLAVE_STARDUST_WEST_CFG] = &qss_stdst_west_cfg,};
static const struct regmap_config maili_stdst_main_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0xf9000, .fast_io = true,};
static const struct qcom_icc_desc maili_stdst_main = { .config = &maili_stdst_main_regmap_config, .nodes = stdst_main_nodes, .num_nodes = ARRAY_SIZE(stdst_main_nodes),};
static struct qcom_icc_bcm * const system_noc_bcms[] = { &bcm_sn0, &bcm_sn2,};
static struct qcom_icc_node * const system_noc_nodes[] = { [MASTER_A1NOC_SNOC] = &qnm_aggre_noc, [MASTER_APSS_NOC] = &qnm_apss_noc, [MASTER_CNOC_SNOC] = &qnm_cnoc_data, [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,};
static const struct regmap_config maili_system_noc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, .max_register = 0x20080, .fast_io = true,};
static const struct qcom_icc_desc maili_system_noc = { .config = &maili_system_noc_regmap_config, .nodes = system_noc_nodes, .num_nodes = ARRAY_SIZE(system_noc_nodes), .bcms = system_noc_bcms, .num_bcms = ARRAY_SIZE(system_noc_bcms),};
static const struct of_device_id qnoc_of_match[] = { { .compatible = "qcom,maili-aggre-noc", .data = &maili_aggre1_noc }, { .compatible = "qcom,maili-clk-virt", .data = &maili_clk_virt }, { .compatible = "qcom,maili-cnoc-main", .data = &maili_cnoc_main }, { .compatible = "qcom,maili-gem-noc", .data = &maili_gem_noc }, { .compatible = "qcom,maili-llclpi-noc", .data = &maili_llclpi_noc }, { .compatible = "qcom,maili-lpass-ag-noc", .data = &maili_lpass_ag_noc }, { .compatible = "qcom,maili-lpass-lpiaon-noc", .data = &maili_lpass_lpiaon_noc }, { .compatible = "qcom,maili-lpass-lpicx-noc", .data = &maili_lpass_lpicx_noc }, { .compatible = "qcom,maili-mc-virt", .data = &maili_mc_virt }, { .compatible = "qcom,maili-mmss-noc", .data = &maili_mmss_noc }, { .compatible = "qcom,maili-nsp-noc", .data = &maili_nsp_noc }, { .compatible = "qcom,maili-pcie-anoc", .data = &maili_pcie_anoc }, { .compatible = "qcom,maili-stdst-cfg", .data = &maili_stdst_cfg }, { .compatible = "qcom,maili-stdst-main", .data = &maili_stdst_main }, { .compatible = "qcom,maili-system-noc", .data = &maili_system_noc }, { }};MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = { .probe = qcom_icc_rpmh_probe, .remove = qcom_icc_rpmh_remove, .driver = { .name = "qnoc-maili", .of_match_table = qnoc_of_match, .sync_state = icc_sync_state, },};
static int __init qnoc_driver_init(void){ return platform_driver_register(&qnoc_driver);}core_initcall(qnoc_driver_init);
static void __exit qnoc_driver_exit(void){ platform_driver_unregister(&qnoc_driver);}module_exit(qnoc_driver_exit);
MODULE_DESCRIPTION("Qualcomm Maili NoC driver");MODULE_LICENSE("GPL");